A Simple Autonomous Current-Sharing Control Strategy for Fast Dynamic Response of Parallel Inverters in Islanded Microgrids

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1 Aalborg Uiversitet A Simple Autoomous Curret-Sharig Cotrol Strategy for Fast Dyamic Respose of Parallel Iverters i Isled Microgrids Gua, Yajua; Vasquez, Jua Carlos; Guerrero, Josep M. Published i: Proceedigs of the 4 IEEE Iteratioal Eergy Coferece (ENERGYCON DOI (lik to publicatio from Publisher:.9/ENERGYCON Publicatio date: 4 Documet Versio Early versio, also kow as pre-prit Lik to publicatio from Aalborg Uiversity Citatio for published versio (APA: Gua, Y., Vasquez, J. C., & Guerrero, J. M. (4. A Simple Autoomous Curret-Sharig Cotrol Strategy for Fast Dyamic Respose of Parallel Iverters i Isled Microgrids. I Proceedigs of the 4 IEEE Iteratioal Eergy Coferece (ENERGYCON (pp IEEE Press. I E E E Iteratioal Eergy Coferece. ENERGYCON proceedigs Geeral rights Copyright moral rights for the publicatios made accessible i the public portal are retaied by the authors /or other copyright owers it is a coditio of accessig publicatios that users recogise abide by the legal requiremets associated with these rights.? Users may dowload prit oe copy of ay publicatio from the public portal for the purpose of private study or research.? You may ot further distribute the material or use it for ay profit-makig activity or commercial gai? You may freely distribute the URL idetifyig the publicatio i the public portal? Take dow policy If you believe that this documet breaches copyright please cotact us at vb@aub.aau.dk providig details, we will remove access to the work immediately ivestigate your claim.

2 This documet is a preprit of the fial paper: Y. Gua, J. C. Vasquez, J. M. Guerrero A simple autoomous curret-sharig cotrol strategy for fast dyamic respose of parallel iverters i isled microgrids, i Proc. IEEE Iteratioal Eergy Coferece (EergyCo 4, 4. A Simple Autoomous Curret-Sharig Cotrol Strategy for Fast Dyamic Respose of Parallel Iverters i Isled Microgrids Yajua Gua #, Jua C. Vasquez #, Josep M. Guerrero # # Istitute of Eergy Techology, Aalborg Uiversity, Demark Microgrids Research Programme Istitute of Electrical Egieerig, Chiese Academy of Scieces, Beijig, Chia {ygu,juq,joz}@et.aau.dk Abstract This paper proposed a ovel cotrol strategy based o a virtual resistace a phase locked loop for parallel threephase iverters. The proposed cotroller ca overcome the drawbacks of the covetioal droop cotrol such as slow trasiet respose, complex desig, limited stability margis. The load sharig capability ca be also obtaied uder asymmetrical output impedaces i which the covetioal droop cotroller was ot properly workig. The proposed approach has bee verified by meas of simulatios experimetal results i a laboratory-scale prototype. Keywords: Parallel iverters, droop cotrol, phase-locked loop, virtual resistace. I. INTRODUCTION roop cotrol method emulates the behavior of a D sychroous geerators by measurig active adjustig frequecy accordigly. I a similar way, reactive power ca also be cotrolled by adjustig voltage amplitude []. These droop schemes are ofte amed P f Q V droops []. They have bee usually preferred for the autoomous cotrol of parallel iverters i the last decade i isled applicatios such as distributed uiterruptible power systems or microgrids [], [3]. The covetioal droop cotrol presets active reactive power couplig poor trasiet respose [4]. I order to improve the active reactive power decouplig performace, improved droop cotrollers are reported i [5] [6]. Also, a ehaced droop cotroller featurig trasiet droop performace is proposed i [7]. The improved cotrollers are proposed based o the static droop characteristics combied with a derivative terms which ca yield to a two degrees of freedom (-DOF tuable cotrol i [8-]. It is also well kow that the performace of the covetioal droop cotrol is seriously affected by the iductace-to-resistace (X/R ratio of output the lie impedace. Microgrids, similarly as electrical distributio etworks, preset a low X/R ratio, so that voltage amplitude is geerally used to cotrol active power, while the agle domiates reactive power so that ca be cotrolled by the system frequecy. This scheme is also amed P V Q f droop. I order to cotrol active reactive power accordig to the power lie X/R ratio, resistive virtual impedace loops has bee added to the droop cotrol. I this sese, we ca have a cotrol framework that icludes three cotrol loops [], []: (i virtual resistace; (ii P V droop; (iii Q f droop. However it is complex to desig the virtual resistace the P V droop coefficiets sice both affect voltage amplitude regulatio with cotrol loops that preset differet cotrol bwidths. Further, a orthogoal liear rotatioal trasformatio matrix T ca be employed to trasform active reactive power to a ew trasformed active reactive powers whe both X R eed to be cosidered [3]. However this method requires precise lie impedace value estimatio, which is difficult to kow. I order to reduce the ifluece of the R/X ratio o droop cotroller improve the active reactive power decouplig performace, a fast cotrol loop amed virtual impedace is added ito the droop cotroller [4], [5]. However, all abovemetioed improved approaches preset the iheret drawback of eedig to calculate istataeous active reactive powers, thus eedig for low-pass filters to average values which bwidth will impact the system trasiet respose [6]. Eve i the case of three-phase systems that the active reactive power ca be calculated by usig the istataeous power theory, a postfilter processig is ecessary i order to elimiate the distorted power compoets [7]. Furthermore, i practical situatios the load sharig performace of the covetioal droop cotrol is degraded whe usig short lies with small impedace, especially i low voltage etworks. I this case, a very small deviatio i voltage frequecy amplitude will result i large power oscillatio eve istabilities [6]. With the aim to overcome the aforemetioed problems, a cotrol strategy by usig a differet view poit is proposed i this paper. The approach is based o usig a virtual resistace loop to substitute the whole droop cotrol by a phase locked loop (PLL. This way, the PLL adjust the phase of the iverter, the system is cotrolled by a virtual resistace cotrollig curret as i a dc electrical system, i a sharp

3 cotrast as i ac systems, i which active reactive power sharig is required. I compariso with the traditioal virtual resistace plus P V Q f droop cotrol framework, the proposed cotroller edows a faster dyamic respose to the paralleled system, allowig higher stability margis easy to implemet to desig. The proposed approach has bee verified by usig simulatio experimetal results i laboratory prototypes. II. A REVIEW OF THE POWER FLOW ANALYSIS IN DROOP CONTROLLED MICROGRIDS Fig. shows the equivalet circuit of two iverters coected i parallel sharig a commo load, which ca be cosidered as a subset of the distributed power etwork operatig i autoomous isled mode. The system model cosist of two voltage sources coected through a series equivalet impedace ( ϕ ϕ, which ecompases the iverter output impedace ( o ϕo o ϕo the lie impedace ( lie ϕlie lie ϕlie. The output voltage of each iverter is deoted byv ϕ Vo ϕo the voltage for poit of commo couplig by Vbus ϕbus. ϕ ϕ ϕo lie ϕlie I I H I o lie ϕlie o ϕo V ϕ I o V V ϕ bus ϕbus o o Iverter # Iverter # Fig.. Equivalet circuit of two iverters operatig i autoomous mode. I traditioal power systems, the equivalet impedaces betwee the paralleled iverters preset high X/R ratio, that measϕlie 9. Thus the output active reactive powers P Q of iverter (=, ca be preseted as follows ( Q VoVbus si( ϕo ϕbus P = ( o VV bus ϕo ϕbus V cos( =. ( From equatios ( (, a set of partial differetial equatios ca be derived as follows: P VoVbus cos( ϕo ϕbus = (3 ϕ P U Q ϕ si( ϕ ϕ bus o bus V = si( ϕ ϕ o bus o bus V V = (4 (5 Q Vo Vbus cos( ϕo ϕbus = U By cosiderig ϕ o ϕ bus large eough, we ca easily adjust active power P with the output voltage agle ϕ o reactive power Q with the output voltage amplitude V o. Based o this power flow aalysis, the droop cotrol law ca be expressed as: ω = ω + k ( P P (7 where, ω pω qv (6 V = V + k ( Q Q (8 V are the ormal output frequecy voltage amplitude, respectively. However, i a practical situatio the load sharig performace of the covetioal droop cotrol is degraded whe usig short lies with small impedaces, especially i low voltage etworks. The reaso of this is that sice [si (ϕ o ϕ bus] / (ϕ o ϕ bus / will ot be eglect whe ϕ ϕ com or is too small. I this case, each equatio from (3 to (6 caot be well approximated to zero, so that the output power (P Q, output voltage amplitude (V frequecy (ω are coupled, which will result i imprecise power cotrol. Furthermore, covetioal droop cotrolled systems may preset istabilities sice small voltage frequecy or amplitude deviatios may result i large power oscillatios whe is very small. III. CURRENT FLOW ANALYSIS THE CHANGE OF PARADIGM Fig. ca be further simplified to a equivalet circuit of a two-paralleled iverter system icludig output voltages ( V V o, output impedaces ( o, virtual resistaces ( R vir R vir, lie impedaces ( lie lie of each iverter as show i Fig.. R I V vir lie R I o vir V o lie o Vbus Fig.. Equivalet circuit of a parallel iverter system with virtual resistaces. This way, each iverter ca be modeled by a two-termial Thévei equivalet circuit as follows [ ] V (s = G(s V (s (s + (s + R I (s (9 bus ref o lie vir o

4 3 vo G ( v s G ( s KPWM I vir ( s Ls + r Virtual Impedace Loop Fig. 3. Block diagram of the closed loop system icludig virtual impedace. where V (s is the output voltage referece G (s is the ref voltage trackig gai, G(s V ref (s presets the geerate voltage of the iverter V o. The output impedace of iverter o(s is ot oly affected by the filter parameters but also iflueced by the cotroller structure parameters. The ier curret voltage loops will be resposible to make o(s as small as possible. I this paper, proportioal-resoat (PR cotrollers tued at the lie frequecy are used to make o(s equals to zero at 5Hz. The block diagram of ier curret voltage loop with virtual impedace is show i Fig. 3. From Fig. 3, the closed loop output impedace o ( s which is modified by virtual impedace vir ( s ca be obtaied as follows: Magitude (abs ; Phase (deg = 4 = = Bode Diagram (a Virtual resistace (b Virtual iductace i o Cs = -9 = 4 = Frequecy (Hz Magitude (abs ; Phase (deg = 4 = = Bode Diagram 9 = 4 = -9 = Frequecy (Hz Fig. 4. Bode diagram of the closed-loop output impedace with virtual impedace. vo u ( s o o ( s = = io ( s Ls+ r+ vir ( s KPWMGu( s Gi( s LCs + [ r+ KPWMGi(] s Cs+ KPWMGu( s Gi( s + ( where vir ( s is the virtual impedace, K PWM is the gai of the pulse width modulatio (PWM, Gu ( s is the voltage loop PR cotroller, Gi ( s is the Proportioal cotroller of the curret loop, L C are the LC output filter parameters. The frequecy respose of the closed-loop output impedace ' o (s for vir (s = R vir vir (s = jx vir cases are both show i Fig. 4. From this figure it ca be see that o ( s is highly depedet o the virtual impedace magitude agle. I additio, sice is practically very small i low (s lie scale electrical systems such as microgrids, R vir becomes the predomiat compoet, so that ( ca be expressed i Laplace domai as Vbus (s = G(s Vref (s Io(s ( which correspods to a Thévei equivalet circuit, as illustrated i Fig. 5. I this paper, proportioal-resoat (PR cotrollers are used to make G(s equals to at 5Hz. Hece, the relatioship of the commo bus voltage ( V bus, referece voltage ( V ref, output curret ( I o vectors ca be expressed i Euler form as follows: Vbus = Vref Io = ( Vref cosϕ Io cos φ + j( Vref siϕ Io si φ ( beig ϕ the voltage referece agle φ the output curret agle. From Fig. 6 we ca see that whe varyig will result i differet output curret vectors ( I o. We ca also express the vectors i a sychroous referece frame by decomposig direct quadrature compoets as follows Vbus = Vrefd Iod (3a = Vrefq Ioq (3b G(s V ref (s R vir (s I o Fig. 5. Iverter closed-loop equivalet Thévei circuit. (s V bus

5 4 Vref ϕ ϕ Io φ I Vbus φ R vir Fig. 6. Vector diagram of the cocept. v q PI va ω ref dq abc vb vc /π Fig. 8. Detail of the block diagram of the SRF-PLL. where V V are the d axis q axis compoet of each iverter s output-voltage refereces separately. I oq refd refq are d axis q axis compoets of output curret. s f θ Thus, the relatioship betwee I od, I oq R vir ca be geeralized expressed for a umber N of coverters as I R = I R = = I R (4a od vir od vir... odn virn oq vir oq vir... oqn virn I R = I R = = I R (4b I od Note that output d q axis output currets of paralleled iverters are iversely proportioal to their virtual resistaces. It ca be easily observed that curret sharig performace is just iflueced by the output impedace ratio istead of the output impedace value of the two iverter modules. Thus, the cotroller is very suitable for the low voltage microgrid applicatios. IV. PROPOSED CONTROL STRATEGY Based o the above aalysis, the proposed cotrol strategy is show i Fig. 7. The power stage cosists of a three-leg three-phase iverter coected to a DC lik, loaded by a L f - C f filter, coected to the ac bus by meas of a power lie ( lie. The cotroller icludes a sychroous referece framebased phase locked loop (SRF-PLL which substitutes the two loops droop cotrol, a virtual resistace loop (R v, a DC lik voltage feed-forward loop, the covetioal PR ier curret voltage loops (G i G v that geerates a PWM sigal to drive the IGBTs the iverter. Capacitor currets voltages are trasformed to the statioary referece frame ( i cαβ v cαβ. The voltage referece V ref is geerated by usig the amplitude referece ( V ref the phase geerated by the PLL. A detailed block diagram of the SRF-PLL is show i Fig. 8. Eve though the PLL is tryig to sychroize the iverter with the commo AC bus, i case of supplyig reactive loads, the quadrature curret flowig through the virtual resistace will create uavoidable quadrature voltage drop that will cause a icrease of frequecy i the PLL. This way the mechaism iheretly edows a I oq f droop characteristic i each iverter. INVERTER v dc DC lik AC BUS v ref v Gv i Gi αβ abc abc αβ i c PWM L i i f l o lie v i c C o f S R vir abc αβ i o abc αβ Virtual Resistace abc αβ v o Vref siθ V ref s ω ref PI v q dq abc θ SFR PLL Load INVERTER lie S Fig. 7. Block diagram of the proposed cotrol method.

6 V. EXPERIMENTAL RESULTS AND PERFORMANCE COMPARISON I order to compare evaluate the performace of the proposed cotrol scheme with the covetioal droop cotrol, a scale-dow laboratory prototype is built accordig to Fig.7. The time-domai model of the proposed cotrol scheme is evaluated i Matlab/Simulik eviromet. The TMS3F8 DSP based platform has bee chose for the real-time digital experimetal tests. The system parameters are give i Table I II. TABLE I SYSTEM PARAMETERS OF PROPOSED CONTROLLER Parameters Values Parameters Values U dc 5 V C f 9.9 µf k pi.63 k i 8.47 R load Ω f c 4 khz L f 3 mh ω c 3 rad/s k p.53 R vir 3 Ω f s khz L lie 7/3.5/ mh TABLE III SYSTEM PARAMETERS OF CONVENTIONAL DROOP CONTROLLER Parameters Values Parameters Values U dc 5 V C f 9.9 µf k pi.63 k i 8.47 k qv. f c 4 khz R load Ω P 75 W L f 3 mh ω c 3 rd/s k p.53 k pω 4 3 f s khz L lie 7/3.5/ mh R start Ω Q 75 var Fig. 9 shows the simulatio results of the paralleled iverter system by usig the proposed cotrol scheme. We ca see that the active reactive powers ca be precisely cotrolled accordig to the ratio of the virtual resistace (:. I order to verify the feasibility of the proposed cotroller, differet operatig coditios have bee cosidered i the experimetal tests. A. Experimetal tests compariso for large lie impedace (L lie = 7mH Fig. shows the output voltages currets trasiet respose for both the covetioal droop cotrol the proposed cotroller whe sharig a pure resistive load. Firstly, iverter # works staloe the iverter # is plugged to the poit of commo couplig (PCC to share the load with iverter #. I order to damp the iitial trasiet curret achieve the hot-swappable performace, a Ω virtual resistace Rstart used by iverter #, lastig for s whe employig covetioal droop cotrol. It ca be observed that the proposed cotroller ca provide higher speed, better dampig precisio performace power cotrol tha those i covetioal droop cotrol. Active power (W Reactive Power (Var Output voltage & Output Curret P P Time (s (a Output active power Time (s (b Output reactive power Time (s (c Output voltage curret. Fig. 9. Simulatio results of the paralleled iverters whe sharig a RL load. (a Covetioal droop cotrol. (b Proposed cotrol method. (X-axis: time (a 5 ms/div, (b 5 ms/div, Y-axis: U 5V/div, i 5A/div Fig.. Compared experimetal results of trasiet resposes for parallel iverters. Fig. shows the steady output voltage waveform of iverter #, output currets of both iverters the circulatig curret based for both covetioal droop proposed cotroller. From Fig., it ca be observed that the Q Q I Io U Uo

7 covetioal droop cotrol strategy ca achieve load-sharig capability betwee the parallel iverters, but the circulatig curret is still large. The peak value of circulatig curret is early A, which represets almost half of the iverter rated output curret. The reaso leadig to this pheomeo is the presece of high-frequecy harmoics i the capacitor curret. This curret is used as feed-forward of the iteral curret loop to improve the dyamic respose its harmoics result i waveform quality deterioratio icrease of the circulatig curret. However the curret sharig performace is quite good whe employig the proposed cotroller i compariso with the droop cotrol. The maximum value of circulatig curret is just.4 A. Fig. shows the cut-off resposes whe iverter# discoects from the PCC for the case of usig covetioal droop cotroller the proposed oe. It ca be observed that whe the iverter # is discoected from the PCC, the output curret of iverter # icreases immediately to supply the load. (b Proposed cotrol method. (X-axis: time 5 ms/div, Y-axis: U 5V/div, i 5A/div Fig.. Experimetal results compariso betwee trasiet resposes. B. Experimetal tests compariso for small lie impedace (L lie = 3.5 mh L lie = mh The paralleled iverter system becomes ustable whe usig droop cotrol with same parameters whe the lie impedace is reduced to 3.5 mh. The large trasiet over curret results i activatig the protectio system whe both iverters were coected. I cotrast, the proposed cotroller ca maitai the load sharig capability with L lie = 3.5 mh eve mh, as show i Fig. 3, while the droop cotrol was ot able to edow a stable operatio i such coditios. (a Covetioal droop cotrol. (a L lie = 3.5 mh. (b Proposed cotrol method. (X-axis: time 5 ms/div, Y-axis: U 5V/div, i 5A/div Fig.. Experimetal results compariso of the steady state waveforms. (b L lie = mh. (X-axis: time 5 ms/div, Y-axis: U 5V/div, i 5A/div Fig. 3. Steady waveforms of the parallel iverters usig the proposed cotroller uder small lie impedace. (a Covetioal droop cotrol. C. Experimetal tests with asymmetrical lie impedace (L lie = 7 mh, L lie = 3.5 mh Fig. 4 shows the curret-sharig performace uder asymmetrical lie impedace whe usig the proposed cotroller. It ca be observed that the proposed cotroller ca

8 elarge system stability margi, while obtaiig a good loadsharig capability eve uder asymmetrical lie impedace as show i Fig. 4, eve whe the droop cotroller was ot able to provide system stability. (X-axis: time 5 ms/div, Y-axis: U 5V/div, i 5A/div Fig. 4. Steady waveforms of the parallel iverters with the U-I droop cotroller uder differet Lie impedace. The performace comparisos betwee both cotrollers are summarized i Table I. The proposed cotroller is faster tha droop method sice it does ot require P/Q calculatios, which limit the bwidth of the system. Further, the use of filters, especially fiite impulse respose (FIR requires icrease the computatioal burde. Note that the covetioal droop cotrol requires for additioal virtual impedace if we wat to improve the aforemetioed problems. I additio, covetioal droop cotrol is more complex to desig sice we eed to adjust two droop coefficiets plus the virtual impedace value. So that two terms (R v Q V droop gai value has to be cosidered at the same time to respect both maximum voltage deviatio proper trasiet respose. The proposed cotroller solves the trade-off by oly usig the parameter R v. There is a tradeoff betwee the power sharig accuracy the voltage amplitude. VI. CONCLUSION This paper proposed a ovel cotrol strategy which based o a virtual impedace phase locked loop, which substitutes the covetioal two droop cotrol loops, for a parallel three-phase iverters. The load sharig performace of this cotroller just depeds o output impedace ratio istead of the output impedace value of the two iverter modules which makes it quiet suitable applied i low-voltage microgrids with small lie impedace values. I compariso to the traditioal droop cotroller, the proposed cotroller could obtai faster dyamic respose, exteded stability margi, simple cotrol parameters desig. TABLE III PERFORMANCE COMPARISON Performaces P-V/Q-V droop Proposed cotrol Trasiet respose Slow Fast Cotrol desig Complex Simple Computatioal load High Low Cotrol parameters m,, R v R v REFERENCES [] Guerrero, J.M.; Chorkar, M.; Lee, T.; Loh, P.C., "Advaced Cotrol Architectures for Itelliget Microgrids Part I: Decetralized Hierarchical Cotrol," Idustrial Electroics, IEEE Trasactios o, vol.6, o.4, pp.54,6, April 3 [] Chorkar, M.C.; Diva, D.M.; Adapa, R., "Cotrol of parallel coected iverters i staloe AC supply systems," Idustry Applicatios, IEEE Trasactios o, vol.9, o., pp.36,43, Ja/Feb 993 [3] Lasseter, R.H., "MicroGrids," Power Egieerig Society Witer Meetig,. IEEE, vol., o., pp.35,38 vol., [4] Cooper K,Dasgupta A, Keedy K, et al, "New Grid Schedulig Reschedulig Methods i the GrADS Project," Proceedigs of 8th Iteratioal Parallel Distributed Processig Symposium, vol.8, pp , 4. [5] J. Guerrero, L. de Vicua, J. Matas, M. Castilla, J. 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