Low Jitter Audio Range PLL with ultra-low Power Dissipation

Transcription

1 Low Jitter Audio Rage PLL with ultra-low Power Dissipatio Fu Luo Departmet of Electrical, Computer & Biomedical Egieerig Uiversity of Rhode Islad igsto, RI, 0288 USA Godi Fischer Departmet of Electrical, Computer & Biomedical Egieerig Uiversity of Rhode Islad igsto, RI, 0288 USA ABSTRACT This paper presets the desig of a ultra-low power Phase- Locked Loop (PLL) iteded for applicatios i the exteded audio rage. The PLL is well suited for battery operated systems, where small size ad low power operatio are crucially importat. The preseted implemetatio is based o a curret cotrolled relaxatio oscillator, which creates a sawtooth put with a frequecy rage of approximately 300 khz. The frequecy is cotrolled by a curret that ca vary from 2 to 74 A. Usig a referece frequecy of ¼ of the typical watch crystal frequecy, the user ca select ay iteger multiple of 8.92 khz up to the maximum of khz. The PLL circuit operates from a sigle 3 V supply ad, depedig o the actual put frequecy, dissipates betwee μw of power. Categories ad Subject Descriptors B 7. [Types ad Desig Styles]: VLSI (very large scale itegratio) Geeral Terms Desig, Measuremet, Performace, Experimetatio. eywords Low power CMOS desig, PLLs, Phase Jitter To achieve the iteded ultra-low power dissipatio, all MOS devices i the aalog sectio of the PLL are operated i the subthreshold or weak iversio regio while all digital uits are based o static CMOS desig techiques. If we adopt the commo 3V termial stadard of may butto cell batteries, the total supply curret of the PLL has to be limited to approximately 0.5 μa to meet the stated power requiremet. The aalog MOS devices must therefore be biased with currets ot exceedig 00 A. As stated above, this requires operatig the trasistors i the sub-threshold regio, which reders them more susceptible to geometry mismatches ad various sources of oise ad other disturbaces. It is therefore a particularly challegig task for circuit desigers to maitai high quality performace. 2. LOOP ARCHITECTURE Figure depicts the basic buildig blocks of a PLL: a phase detector (PD), a loop filter, a voltage cotrolled oscillator (VCO) ad a (digital) frequecy divider. The VCO ad the loop filter are arguably the most critical blocks, sice they decide ab the frequecy rage ad exert the strogest ifluece o settlig behavior as well as frequecy ad phase stability.. INTRODUCTION PLLs are versatile buildig blocks used i may commuicatio systems ad itegrated circuits, where they serve as local oscillators, carrier geerators or detectors, clock recovery uits, frequecy multipliers, etc. This paper addresses the desig of a PLL iteded for the exteded audio rage (0-50 khz) with a power cosumptio of ot more tha -2μW. The circuit is therefore well suited for battery operated systems as foud i may remote sesig applicatios or portable miiature biomedical devices. Permissio to make digital or hard copies of all or part of this work for persoal or classroom use is grated with fee provided that copies are ot made or distributed for profit or commercial advatage ad that copies bear this otice ad the full citatio o the first page. To copy otherwise, or republish, to post o servers or to redistribute to lists, requires prior specific permissio ad/or a fee. GLSVLSI, May 2 4, 20, Lausae, Switzerlad. Copyright 20 ACM //05...$0.00. Figure. Basic PLL Block Diagram. The loop filter is typically a simple first or secod order passive RC circuit. I cases where it is ecessary to reduce clock misaligmet, active filters ca be used as well. While they ca yield more effective filter characteristics, they add sigificatly more complexity to the cotrol of the settlig behavior ad the lockig characteristics. If the PLL put frequecy is expected to be a iteger multiple of the referece, the feedback path has to icorporate a digital frequecy divider or modulo cer. If the frequecy divisio is programmable, the PLL ca serve as a frequecy sythesizer.

2 3. PLL BUILDING BLOCS 3. Phase Detector To be able to icremet, maitai or decremet the VCO put frequecy, desigers prefers a phase detector (PD) with a terary put. Figure 2 presets a efficiet implemetatio of such a 3- way PD circuit based o static CMOS techiques. The 3 digital puts created by this circuit are up (icremet), dw, (decremet) ad Nup, Ndw (maitai). The 2 iput voltages of the depicted circuit, i.e. V ref ad V fb, are square waves with arbitrary duty cycles. Figure 2. Terary PD i CMOS Techology. 3.2 Loop Filter The loop filter i a all-digital PLL is typically realized by a charge pump [6], essetially a capacitor that is charged or discharged by a costat referece curret as illustrated i Figure 3. obtai best trackig ad acquisitio properties, the loop badwidth should be made as wide as possible. The desiger thus has to carefully weigh the pros ad cos of selectig various sets of filter parameters. Based o the iteded put frequecy rage of 0-50 khz, we have decided o the followig desig compromise: C =25 pf, C 2 =2.5 pf ad R=8 M. The selected resistor ad capacitor values are rather large for a area effective o-chip implemetatio. Some desigers might therefore decide to keep them off chip to be able to readily adjust the tuig rage ad gai more cotrol over the PLL lockig characteristics. Coversely, exteral compoets are rather costly ad reder the implemetatio more susceptible to oise ijectios ad other parasitic effects. We have opted to realize the charge pump with o-chip compoets. To miimize circuit area, we have realized the large dampig resistor of 8 M by a very log -chael device operated i the ohmic or triode regio. While this implemetatio requires approximately 50 times less area tha a passive resistor formed by the high resistive layer offered by the available 0.5 m CMOS process, it is ot perfectly liear ad acts more like a distributed RC lie tha a simple resistor. However, as will be show i sectio 5, it does ot severely alter the loop settlig behavior. To prevet additioal distortio, we have realized the filter capacitor C as a passive elemet usig the poly-poly2 capacitor optio offered by the chose CMOS process. The charge-discharge curret I ch of the charge pump has bee selected to be slightly smaller tha 00 A. 3.3 Voltage Cotrolled Oscillator Most high-frequecy VCOs are based o some form of curret cotrolled or curret starved rig oscillator. Sice our target put frequecies lie i the exteded audio rage, the propagatio delay of such a rig oscillator elemet would have to be o the order of multiple microsecods. This umber is more tha 3 orders of magitude larger tha a typical gate delay o a state-of-the-art CMOS chip ad thus would reder the idividual elemets rather uwieldy. Istead, we have opted for a curret cotrolled relaxatio oscillator. This solutio allows to miimized size ad power idepedetly. Figure 4 depicts the proposed VCO circuit. Figure 3. Charge pump with terary cotrol. The serial RC sectio forms a first-order lowpass filter, which (partially) removes the higher frequecy compoets i the (digital) phase detector put V ctl. Capacitor C 2 has bee added to prevet vertical steps i the cotrol voltage of the VCO, which would cause udesired glitches ad sudde frequecy chages i the VCO put [7]. C 2 is typically selected to be ab oe-teth the value of the filter capacitor C. To miimize phase jitter iduced by exteral oise, the loop badwidth should be made as arrow as possible. O the other had, to miimize the trasiet error due to sigal modulatio, or to miimize the put jitter due to iteral oscillator oise, or to Figure 4. Curret cotrolled relaxatio oscillator. To achieve the desired low frequecy operatio, the capacitor C g of the VCO is charged by a very small (voltage cotrolled) curret ragig from approximately 2-74 A. This creates a egative ramp (V g ), which cotiues to decrease util V g matches the referece voltage V ref. As soo as V g drops below V ref, the comparator, realized by devices m-m7, creates a short egative pulse, which resets V g to V dd by activatig the switchig device

3 mg. To speed up the relatively slow comparator recovery time from its put low state to the (typical) put high state, we have added a servo loop cosistig of a log-chael iverter (to miimize power) ad a additioal p-chael pull-up device (mp6) actig i parallel to the curret mirror device m6. If we deote the very short reset phase of V g by T rst, we ca compute the period of the resultig sawtooth waveform as follows [8]: T saw Cg Vdd Vref ) T I ref ( () rst Sice T rst will be o the order of a few s while T saw will be i the μs rage, the slope of V g ca be approximated by the ratio I ref /C g =(V dd -V ref )/T saw. To maximize the sawtooth swig ad with it the oise immuity, the commo source iput pair of the comparator has bee realized by p-chael devices. This exteds the commo-mode iput rage dow to groud. V ref could therefore be as small as the saturatio voltage of the -chael curret mirror device (approximately 00 mv). I this work, we have coveietly utilized the commo gate voltage of the 2 -chael curret source elemets mb3 & mb4 as the referece voltage. V ref is therefore almost idetical to the threshold voltage of these 2 trasistors. Combiig the 3 V supply with the omial -chael threshold voltage of the chose 0.5 μm CMOS process yields a sawtooth swig of ab 2.4 V. Selectig a p-chael rather tha a -chael comparator iput pair is also beeficial with regard to flicker oise, sice p-chael devices ted to suffer iheretly less from these radom charge carrier combiatios tha their -chael cerparts. Furthermore, it provides for a higher egative slew rate ad thus miimizes the comparator latecy [5], [9]. A toggle flip-flop coverts the short egative voltage spike produced by the comparator, i.e., V o, ito a square wave with a 50% duty cycle. The VCO put frequecy is therefore: f (2) 2T saw As illustrated i Figure 4, the VCO is biased by a supply isesitive curret source formed by trasistors mb, mb2, mb3, mb4 ad resistor R b. To obtai a sufficietly short comparator respose time, we have selected the omial tail curret of the differetial iput pair to be 80 A. 3.4 V-I coverter Sice the depicted relaxatio oscillator is cotrolled by a curret, the charge pump put voltage eeds to be coverted to a proportioal curret. Ufortuately, the V-I relatioship of a MOS device is ot liear. To obtai a quasi-liear relatioship, we have created a voltage depedet weighted sum of 2 oliear, very log chael MOS currets (the drai currets of mr ad mr2 i Figure 5). To avoid a dead-lock situatio i case V ctl accidetly approaches V dd, we have added a arrow start-up device mst, which prevets the cotrol curret I ctl from reachig zero. Figure 6 shows a simulatio of the resultig quasi-liear V-I curve realized by the depicted circuit. Figure 5. Voltage-to-curret coverter circuit. Figure 6. Resultig V-I Coverter Characteristics. 3.5 Frequecy Divider Circuit The utilizatio of a divide-by-n or modulo N cer reders the PLL more versatile. By combiig the divider circuit with a digital comparator, oe effectively has a frequecy sythesizer govered by the simple relatioship. f N (3) f i If it becomes ecessary to create fractioal multiples of a referece frequecy, oe ca add a secod divide-by-m circuit i frot of the PD. The put versus iput frequecy relatioship the becomes: f N (4) M f i We have applied this techique to sythesize put frequecies of iteger multiples of ¼ of the typical watch crystal frequecy of khz. Figure 7 depicts our 4-bit versio of a divide-by-n cer paired with the ecessary digital comparator circuit. This circuit eables testig the PLL for ay iteger umber of N betwee ad 5. The divider ad comparator circuits have bee implemeted usig static CMOS techiques. Sice this cer/comparator circuit is operated at frequecies below 25 khz, its cotributio to the total power budget is deemed egligible.

4 Figure 7. Modulo-N cer with digital comparator circuit. 4. STABILITY AND JITTER ANALYSIS 4. Loop Stability The trasfer fuctio of a PLL employig a charge pump as loop filter ca be approximated by: H where ad CP ( s) pd vco (5) s 2 s N pd ( sc R) vco pd R NC Ich pd (6) 2 vco V pd ad vco are the scalig factors of the charge pump ad the VCO, respectively, while the scalar N characterizes the frequecy divider. The PLL s atural frequecy, its dampig factor ad the lock-i rage are give by: I ctl vco (7) ch (8) Vctl 2NC RC (9) 2 4 (0) L Although the above expressios pertai to a oversimplified versio of the PLL ad do ot acc for the additioal elemet C 2, they provide useful isight ito the rather complex dyamics of the PLL. Based o the actual value of N, the atural frequecy of our PLL will vary betwee khz, while the dampig factor is expected to lie betwee This yields a lock-i frequecy of 5-20 times the atural frequecy, which provides sufficiet protectio agaist jitter preset o the referece iput. 4.2 Jitter Aalysis The evet-to-evet variatios of the comparator trasitios i the VCO are caused by udesired voltage variatios of its two iputs, i.e., V g ad V ref. If all parasitic sigal compoets affectig these two voltages are represeted by a equivalet differetial iput oise voltage V, we ca approximate the variace of subsequet comparator trasitios by V t T () saw V V dd ref A complete cycle of the square wave put of the VCO cosists of two sawtooth periods. If we assume the disturbig sigals preset durig two cosecutive trasitios to be statistically idepedet, the PLL s cycle-to-cycle jitter T Jcc becomes: TJcc 2 (2) t A practically more relevat umber may be the relative jitter, i.e. the jitter divided by the put period T. Combiig equatios () ad (2) yields T T Jcc (3) V 2( Vdd Vref ) This result is ot surprisig, sice maximizig the swig of the sawtooth voltage V g, i.e., (V dd -V ref ), miimizes the impact of the disturbig sigal compoets. For example, the relative jitter will be less tha 0.% i our circuit as log as V ca be kept below 3.4 mv. As table I reveals, the self-oise produced by the MOS trasistors will therefore be rather icosequetial. The disturbig equivalet voltage V icludes power supply oise, substrate oise as well as thermal ad flicker oise stemmig from the MOS trasistors. Our VCO circuit yields a very high positive power supply rejectio (> 40 db), but suffers from a rather poor groud oise protectio (0.5 db). Substrate ijected oise is therefore deemed to be the most critical parameter with regard to jitter performace. Table lists the critical performace parameters of the comparator circuit depicted i Figure 4. Table. Comparator performace parameters Differetial Mode 0 khz Commo Mode 0 khz Propagatio Delay (T saw =3.5 s) Propagatio Delay (T saw =35 s) 75 db -9.5 db 86 s 435 s Iput referred thermal Noise V th 62 V/Hz /2 Power Dissipatio (V dd =3 V) 700 W 5. SIMULATIONS RESULTS To demostrate the proper fuctioality of the proposed PLL, we have realized the physical lay of the etire PLL. Figure 8 displays a picture of the fial lay. As ca be see, the VCO ad the programmable digital frequecy divider rather pale i compariso to the filter capacitor C, which fills ab 60% of the etire PLL footprit. The charge pump capacitor C 2 is realized by the bottom plate parasitic of C ad ams to approximately

5 0% of the filter capacitor. To provide some extra protectio agaist groud oise ijectio, the aalog portio of the PLL is protected by a guard rig. All circuit simulatios have bee performed o a lay extracted etlist. The simulatios have bee carried by HSpice usig Bsim3v3. model parameters of the available 0.5μm CMOS process. We have assumed a square wave referece iput voltage of 8.92 khz with 3 V swig. Figure 9. VCO frequecy versus cotrol voltage. Figure 8. Lay of proposed PLL (Size: 0.2 x 0.23 mm). Our first ivestigatio was cocered with the performace of the VCO. As depicted i Figure 9, the circuit yields a almost liear characteristic with a frequecy rage from 0 khz 50 khz while the cotrol voltage varies from V. Figure 0 reveals the dyamic respose of the PLL due to a chage of the digital feedback frequecy divider from N=5 to N=3. The three depicted traces represet the put voltage of the charge pump (V ctl ), the feedback sigal after the voltage divisio (V fb ) ad the VCO referece voltage V ref. The simulatio results demostrate that the PLL is stable ad locks relatively quickly while N chages from 5 to 3. As expected (cf. equatio (8) & (9)), the case N=5 requires visibly more settlig time tha N=3 (see top trace i Figure 0). The total power cosumptio of the PLL depeds o the actual put frequecy. Table 2 lists the recorded power of the PLL as a fuctio of the put frequecy. The above listed values reveal that the power dissipatio of the PLL is ot strogly tied to the put frequecy. I fact, the power icreases by ot more tha 40% while the frequecy quituples from khz to khz. Figure 0. Dyamic respose of the proposed PLL to a chage of the feedback frequecy divider from 5 to 3. Table 2. PLL power dissipatio versus put frequecy N f ref [khz] f [khz] P [μw]

6 Sice the actual phase jitter of the PLL will tightly be liked to its physical operatig coditios such as substrate oise ijectio or cross talk betwee aalog ad digital sigals, it is ot possible to properly assess this parameter via simulatio. We expect to obtai some idisputable umbers for this parameter from the physical implemetatio of the PLL i 0.5 m CMOS. Table 3 summarizes the critical performace parameters of some recet low power PLL or oscillator implemetatios. Provided the simulated performace parameters of the preseted PLL ca be cofirmed o silico, it represets a iterestig alterative for very low power applicatios. Table 3. Characteristics of some recet low power oscillators Refereces Techol. Supply [V] Frequecy [khz] Power [μw] This work 0.5μm * Ada et al [4] De Vita et al [] Lasae et al [2] Sebastiao et al [3] * Complete PLL 0.6μm * 0.35μm μm m CONCLUSIONS We have itroduced a iterestig alterative for a ultra-low power PLL. The core of the circuit cosists of a curret cotrolled relaxatio oscillator, which geerates a sawtooth put with a frequecy rage of approximately khz. Jitter resultig from radom fluctuatios of the 2 comparator iput voltages is kept small by maximizig the sawtooth swig ad substrate oise ijectio is reduced by a guard rig, which ecircles all sesitive PLL compoets. The curret implemetatio realizes a sawtooth swig of ab 80% of the supply rail, but the comparator is equipped to hadle a rail-to-rail sigal rage. The expected referece iput of the PLL is a square wave of ¼ of the typical wrist watch crystal frequecy, i.e., 8.92 khz. A 4-bit digital comparator allows the user to pick the put as a iteger multiple of the referece frequecy up to a maximum of khz. The circuit operates from a sigle 3 V supply ad is expected to dissipate less tha 2 μw of power. 7. REFERENCES [] G. De Vita, F. Marraccii, ad G. Iaaccoe, Low-voltage low-power CMOS oscillator with low temperature ad process sesitivity, i Proc. IEEE It. Symp. Circuit Syst., pp May 27-30, [2]. Lasae ad J. ostamovaara, A.2-V CMOS RC oscillator for capacitive ad resistive sesor applicatios, IEEE Tras. Istrum. Meas., Vol. 57, No. 2, pp , December, [3] F. Sebastiao, L. Breems,. Makiwa, S. Drago, D. Leeaerts, ad B. Nauta, A low-voltage mobility-based frequecy referece for crystal-less ULP radios, IEEE. J. Solid-State Circuits, Vol. 44, No. 7, pp , July, [4] Gudel, A., Carr, W.N., Ultra low power CMOS PLL Clock Sythesizer for Wireless Sesor Nodes, IEEE Iteratioal Symposium o Circuit ad Systems, pp May 27-30, [5] Marti,., Johs D.A., Aalog Itegrated Circuit Desig, Joh Wiley ad Sos, Ic, 997. [6] Narayaa, H., Fischer, G., Ultra low-power phase-locked loops, IEEE 48th Midwest Symposium o Circuits ad Systems, Vol.2, pp , February, [7] I. A. Youg, J.. Greaso, ad. L. Wog, A PLL Clock Geerator with 5 to 0 MHz of Lock Rage for Microprocessors, IEEE J. Solid-State Circuits, Vol.27, No., pp , November, 992. [8] M. P. Fly ad S. Lidholm, A.2 um CMOS curret cotrolled oscillator, IEEE J. of Solid-State Circuits, Vol. 27, No. 7, pp , July, 992. [9] C.-M. Hug ad.. O, A fully itegrated.5-v 5.5-GHz CMOS phase-locked loop, IEEE J. Solid-State Circuits, Vol. 37, No. 4, pp , April, 2002.