Novel Matrix Converter Topologies with Reduced Transistor Count

Transcription

1 Novel Matrix Coverter Topologies with Reduced Trasistor Cout. M. ajjad Hossai Rafi Electroic ystems Egieerig Hayag Uiversity Asa, outh Korea Thomas A. Lipo Electrical & Computer Egieerig Uiversity of Wiscosi-Madiso Madiso WI, UA Byug-il Kwo Electroic ystems Egieerig Hayag Uiversity Asa, outh Korea Abstract This paper proposes several alterative ovel matrix coverter topologies based o the structure of a dual bridge matrix coverter with certai advatages over the covetioal matrix coverter topologies. It is demostrated that, by utilizig -trasistor iverter at the load side of ay idirect matrix coverter family could lead to a major reductio i the high performace but expesive trasistor cout. Oe matrix coverter topology is realized by employig oly 12 trasistors as opposed to 18 trasistors as i the covetioal or dual bridge or 15 trasistors i the sparse matrix coverter. Despite the reduced umber of trasistors, this topology esures four-quadrat operatio, uity power factor, o dc-lik eergy storage, ad high quality voltagecurret waveform. This paper also shows a realizatio which could reduce the trasistor cout further to oly 6, which fulfills all the desirable features of a matrix coverter except that it has uidirectioal power flow capability which is still attractive for suitable applicatios. Thus, these circuits could prove to be attractive i applicatios requirig high cost switchig compoets such as ew silico carbide or gallium itride based devices. Proposed topologies are aalyzed theoretically to verify the characteristics of this coverter family. imulatio results of a 6-trasistor topology are provided to validate the performace ad feasibility of the ovel topologies. I. INTRODUCTION Traditioal AC-AC frequecy coverters covert AC electrical power of oe frequecy ito AC electrical power of aother frequecy. Additioally, these coverters, covetioally kow as DC liked rectifier-iverter type power frequecy coverter. They have the capability to cotrol the load voltage amplitude, the load displacemet agle relative to source voltage, the displacemet agle betwee source currets ad voltages ad the capability to cotrol bi-directioal or uidirectioal power flow through the coverter. Thus, the most desirable features of a AC-AC coverter are as follows, 1. imple ad compact circuit arragemet 2. Geeratio of output voltage with chageable amplitude ad frequecy. High quality iput ad output curret 4. Operatios with uity power factor for ay load 5. Regeeratio capability The matrix coverter, show i Fig. 1, ca also fulfil these ideal characteristics. Moreover it assures siusoidal iput ad output waveforms, with miimal higher order harmoics ad o sub-harmoics. Last but ot least, it has a miimal eergy storage requiremet, which allows oe to elimiate bulky ad lifetime- limited DC-lik eergy-storig capacitors [1]-[4]. I 1980, eturii itroduced the first actual sigle-stage matrix coverter (MC cosistig of a array of bidirectioal switches [1], ad i a followig ladmark work [2] the required algorithms were preseted. However, idustrial acceptace of the covetioal matrix coverter (CMC had bee limited due to its 18 power switches, complex commutatio, bipolar subbers, ad limited voltage trasfer ratio (up to 87% [2]. However, sice its itroductio, itesive research has bee coducted for the developmet of differet modulatio ad cotrol strategies [5]-[11]. As a alterative structure [12]-[16] propose a comparable idirect topology based o dual bridge cocept. I [12] this arragemet is treated as a rectifier/iverter, where lie (rectifier ad load (iverter side switches are cotrolled separately. I additio, [1]-[16] start to label this arragemet as a idirect CMC approach also kow as a idirect matrix coverter (IMC. Moreover, i [14] [15], the complicated commutatio scheme of this coverter was reduced uder the ame of Dual Bridge Matrix Coverter (DBMC. I additio, i [15], bulky clamp protectio circuit was greatly simplified ad i [15][16] the large umber of power switches (trasistors were reduced gradually uder certai costraits. e.g. from 18 to 15 is etitled as parse Matrix Coverter (MC, from 15 to 12 is termed as ery parse Matrix Coverter (MC ad Iversig Lik Matrix Coverter (ILMC, ad fially from 12 to 9 is called as Ultra parse Matrix Coverter (UMC /14/$ IEEE 1078

2 This paper itroduces several additioal MC topologies with reduced umber of trasistors. They are developed based o the structure of a IMC or DBMC (cf. Fig. 2. With the proposed structure as show i Fig., DBMCs could be realized with less trasistors tha their covetioal structure. A literature survey o the MC suggests [1]-[16] that i case of ay BDMC family, the trasistors reductio techiques are utilized mostly o the lie side coverter topology, i.e. the rectifier circuit. However, this paper discusses a major trasistor reductio techique which could be realized by utilizig a -trasistor iverter circuit formig the load side coverter of ay covetioal DBMC family. This type of iverter topology (Load side coverter of Fig. was first proposed i [19] describig the topology, operatioal priciple, ad its commutatio techique. Moreover, covetioal PWM methods ca be utilized o both the rectifier ad iverter circuits, therefore, the cotrol scheme is simplified. Furthermore, a simple clamp circuit is used i betwee to coect the rectifier ad iverter circuit. Moreover, the derivatio ad the basic operatio alogside the switchig sequece ad PWM techiques for both rectifier ad iverter circuits are discussed i this paper. Fially, system level simulatio results of 6-trasistor MC are provided to verify the characteristics of the ovel MC topologies usig MATLAB/ IMULINK. II. DERIATION OF THE NOEL MC TOPOLOGY Covetioally, if a coverter has m iputs ad outputs, the umber of power switches required for eergy Figure 1. Commo emitter based bidirectioal trasistor CMC topology Figure 2. Dual bridge matrix coverter topology coversio are mx[1]. I accordace to that, to coect a m-phase voltage source to a -phase load, a CMC requires a array of mx bidirectioal power switches. The matrix coverter of switches show i Fig. 1, has the highest practical iterest because it coects a three-phase voltage source with a three-phase load, typically a motor. If the switchig fuctio of a switch, jk i Fig. 1 is 1, jk = 0, where, j switch jk closed switch jk opeedd { a,b,c}, ad k { u,v,w} The the restrictio of the CMCC topology ca be writte as, ak + bk + ck = 0 The iput ad output voltagess of such CMC ca be expressed as vectors, sa i = sb sc su o = sv sw The relatio betwee these two voltages v ca be expressed as follows, su au sv = av sw aw bu bv bw cu sa cv. sb cw sc Thus, equatio 4 ca be rewritte as, o = T. i where, T is the istataeous trasfer matrix. I the same maer the relatioship betwee the iput ad output currets ca be obtaied as follows, i T i = T. i o isa ii = isb i sc isu io = i sw where, T T is the traspose matrix of T. I cotrast, the DBMC topology (cf. Fig. 2 cosists of series coected lie ad load side coverter with a fictitious DC lik i-betwee. Here, a covetioal voltage source iverter (I is fed by bidirectioal curret source rectifier (CR []. This structure decouples the cotrol of the iput curret ad output voltage. Agai, for a balaced phase system lie voltages are, sa + sb + sc = 0 (1 (2 ( (4 (5 (6 (7 (8 1079

3 p idc sa sb ap bp cp a b tup t twp u v w isw sc Rf Lf Cf a b c c tu tv tw isu Rl Ll Figure. chematic of the ovel matrix coverter topology El Thus, the istataeous trasfer matrix T is essetially the product of lie ad load side coverter trasfer fuctio. For the DBMC topology show i Fig. 2, two additioal poits (p, are itroduced ad the T becomes as follows, au av aw bu bv bw cu up cv = cw wp u ap v. a w bp b Thus, the output voltage of DBMC ca be foud as, su up sv = sw wp u ap v. a w bp b sa cp. sb c sc cp (9 c (10 Fig. illustrates a ovel topology based o the basic structure of a DBMC show i Fig. 2. From the figure. it ca be see that this topology has less umber of trasistors ad that the switch reductio strategy is applied o the load side coverter. As may be observed, this topology is equipped with both trasistors ( u, v, ad w ad thyristors ( tup, tu, t, tv, twp, ad tw. I cotrast with the covetioal I, ew ad evolvig but expesive silico carbide or gallium itride based switches are reduced from 6 to i umbers by usig 6 iexpesive thyristors istead. Here, two thyristors ( tup, btu for phase u per phase provide positive to egative curret commutatio to the circuit. Ulike utilizig complex ad expesive forced commutatio techiques [17], these thyristors are aturally commutated by meas of trasistor s switchig capability. As for a covetioal I, diodes are also coected atiparallel with all the switches for bidirectioal curret flow. Thus, the iverter circuit trasfer fuctio ca be rewritte for of the proposed topology as follows, up wp u ( + tup up v = ( t + w ( + twp wp ( tu + u ( tv + v ( + tw w (11 Fially, the output voltage of the ovel MC topology could be obtaied as, su ( + tup up sv = ( t + sw ( + twp wp Here, p = ap a bp b ( tu + u ( + p tv v. ( + tw w sa cp. sb c sc (12 (1 It should be oted that switches u, v, ad w are operated both o the positive ad egative cycle of the curret flow. Thus, i equatio (12 ad (1 for the positive sequece trasistors u, v, ad w become up,, ad wp respectively. For the egative sequece they become a, b, c, u, v, ad w respectively. III. PROPOED TOPOLOGIE A. Topologies with Regeerative Capability I order to obtai a siusoidal iput curret supply a covetioal CR is utilized with commo-emitter bidirectioal power trasistors which is capable of operatig with positive ad egative DC curret for the uipolar DC voltage as required by the I. With this arragemet PWM cotrol is possible for both lie ad load side coverter. Aother versio of the DBMC is proposed show i Fig. 4, by replacig of the classical I with the -trasistor I. I [19] authors have show that it is a iexpesive alterative to the classical 6-trasistor I ad they have verified the performace ad feasibility of this ew I topology. Thus, the ovel MC topology requires 15 uidirectioal trasistors to be the replacemet to the 18-trasistor topology. The trasistor switch cout could be reduced furthermore uder the same coditio ( p > at the lie side bridge. Fig. 5 illustrates the switch reductio techique i step by step maer [5][15][16]. Oe ca see that trasistors app ad ap ca be replaced with sigle switch ad the topology 1080

4 idc possesses the same performace as CM. This type of MC was deoted as MC i [15] ad it requires 15 uidirectioal power trasistors. However, Fig. 6 illustrates aother ovel MC topology usig the switch reductio techique ad the - trasistor I discussed above. This ovel topology cosists of oly 12 uidirectioal trasistors havig the same characteristics as the 15-trasistor MC or CM. Furthermore, the DBMC topology could reduce its power trasistor cout by employig zero DC lik curret commutatio techique at the lie side coverter as show i Fig. 7. This strategy of switch reductio is proposed i [15][16] ad deoted as MC or 12-trasistor MC. Nevertheless, this MC topology could be replaced by the ovel 9-trasistor MC topology show i Fig. 7 which resembles the same characteristics as the 12-trasistor MC. B. Topologies with No-regeerative Capability With the coditio i DC 0, further switch reductio could be achieved by coectig a covetioal 6-trasistor CR ad I i series, as a result of a 12-trasistor MC [15][16] (Fig. 8. By usig the same strategy described above, this topology could be substituted by the ovel 9-trasistor MC topology show i Fig. 8. Here, the bidirectioal power flow ca be realized by two power trasistor ad two diodes placed betwee the CR ad I as show i Fig. 9. Fially, by utilizig a two-quadrat buck-type PWM rectifier suggested i [15][16] ad the -trasistor I, oe could realize the DBMC with further reduced umber of trasistors. Where, o curret flows through trasistors jp ad j ( j { a,b,c}. Thus, a ew 6-trasistor MC could be obtaied as show i Fig. 10. This circuit structure of the 6-trasistor MC ad 9- trasitor MC topologies are such that, they restrict the a b c p isu isw u w v sa sb sc ap bp cp app bpp cpp a b p idc tup t twp dc u v w c Figure 7. Novel 9-trasistor MC topology Rf Lf ap bp cp p idc Cf a b c tu tv tw isu isw Rl Ll a b c isu isw u w Figure 4. Novel 15-trasistor MC topology El v ap p idc p idc p idc bp ap Figure 8. Novel 9-trasistor ILMC topology p idc app bpp isu u a a b c isw w ap bp v a b bp Figure trasistor ILMC topology Figure 5. Trasistor reductio stretegy P idc tup t twp ap bp cp P idc sa tup tup twp sb Cc a b c u v w sa sc Rc sb a b c u v w Rf Lf Cc sc Rf Lf Cf tu tv tw isu isw Cf a b c tu tv tw Rl Rl Ll Ll El El Figure 6. chemetic of the ovel 12-trasistor MC topology Figure 10. chemetic of the ovel 6-trasistor MC topology 1081

5 operatio to uidirectioal power flow. Ad they ca oly be used whe the value of the DC lik curret is positive or equal to 0 (i DC 0. Due to this, the phase displacemet of the iput voltage ad curret fudametal is limited to ± π/6. As a result of that, the power factor o the load side should be always greater tha Nevertheless, because of the low umber of power trasistors, this 6-trasistor MC should be of iterest ad i the future this ovel topology will be reported i detail with experimetal results. C. Clamp Circuit Uder ormal or fault coditios the clamp circuit is a essetial compoet for both CMC ad DBMC. It provides a path for the commutatio eergy stored i the load s leakage reactace. However, i faulty coditio it serves to deof the switchig eergize the load curret for the protectio devices. The covetioal clamp circuit of a CMC requires dual six-pack diode rectifiers ad oe capacitor [6]. However, IMC topologies require a much simpler clamp circuit. Moreover, i [15] the clamp circuit for the covetioal 9-trasistor MC or the UMC, is greatly simplified with oly oe diode ad oe capacitor. Likewise, a sigle diode (D c ad sigle capacitor (C c clamp circuit is used for the ovel 6-trasistor MC as show i Fig. 10. At startig poit with all the lie side switches are o, the clamp capacitor voltage is charged up to the maximum peak lie voltage. Normally, the C c shows higher voltage tha the dc lik voltage DC. However, to avoid high voltage spikess uder a fault coditio, with all the trasistors off, the stored eergy i the iductive load flows i to the C c. Also, the size of the capacitor value depeds o the load curret, load iductace, ad the highest allowable capacitor voltage [6]. I. COMMUTATION AND PWM CONTROL CHEME For the purpose of simplified aalysis, values of filter compoets R f, L f, ad C f are cosidered to be zero. witchig frequecy of the rectifier side is cosidered much higher tha the iput ad output frequecy. Iput curret ad positive DC voltage is maitaied by the rectifier circuit, its switchig fuctios, ad the iput voltage. However, the DC curret ad output voltage are determiedd by the iverter switchig fuctios ad output curret. Nevertheless, i the clamp circuit a additioal dampig resistor (R c is used parallel with the clamp capacitor (C c ad diode (D c i order to miimize the fluctuatios of the output waveform. This R c ca be cosidered as the coductio losses switchig compoet. I additio, the iput source voltages ca be assumed as follows, Ad the iput curret equatios are writte bellow, iu = I o cos( ωθ oi t + ϕ o (15 iv = I o cos( ωθ oi t + ϕ o iw = I o cos( ωθ oi t + ϕ o + The quatities m ad I are the maximum peak iput voltage ad output curret, ω i ad ω are the iput ad output agular frequecy, fially φ is the iitial agle of the phase output curret. A. witchig Priciple of the Lie ide Coverter The switchig sequece of the rectifier circuit is based o six itervals of the iput voltage sychroizatio agle. It ca be observed from the Fig. 11 that, oly oe of the three phase iput voltage has the highest absolute value durig each iterval. For example, i iterval oe sa has the highest absolute value. Furthermore, i oe iterval the switchig sequece is split ito two portios to maitai the DC lik voltage. I additio, i each portio the switchig sequece Figure 11. ix itervals of a switchig cycle of the rectifier circuit sa sb sc = m cos ω i t = m cos( ω i t = m cos( ω i t + (14 Figure 12. (a Positive (b egative switchig techique of the iverter 1082

6 of lie side trasistor is fixed ad the DC is equal to oe of the two highest positive lie voltages. Correspodig to sc, the highest absolute voltage, the largest positive lie voltages are sa - sb ad sa - sc. Fially, the rectifier switchig state i each portio ca be determied by followig sequece. I portio 1, for the first 0 o coductio period a ad b remai tured o with c is tured off. Thus the DC side voltage is sa - sb. The dc lik curret i DC is equal to i sab ad i sc, ad i sa is zero. Agai for the ext 0 o coductio period a ad c are tured o with b is tured off, that makes the DC side voltage is equal to sa - sc. The basic strategy cotiues accordig to the phase order as show i Table I. The detailed switchig ad PWM scheme for the load side coverter ca be foud i [15]. TABLE I. Iterval LINE IDE WITCH AND DC OLTAGE IN EACH INTERAL Portio 1 Portio 2 O witch DC O witch DC 1 b, a sa sb c, a sa - sc 2 b, c sb - sc a, c sa - sc c, b sb - sc a, b sb - sa 4 c, a sc - sa b, a sb - sa 5 a, c sc sa b, c sc sb 6 a, b sa - sb c, b sc - sb B. Commutatio of the Load ide Coverter The commutatio techique for the load side coverter is described i this sectio. For positive i u curret, thyristor tup is first tured o with tu off. Trasistor u is the switched o ad off usig a appropriate PWM techique. Withi this period, positive curret flows through tup, u, D 2, ad D t2 (cf. Fig. 12(a. At the ed of this positive half cycle; whe curret reaches zero, tup is tured off by removig the gate sigal from u. After the recovery period of tup, tu is tured o with tup remaiig off. Agai, for this egative half cycle u is tured o ad off usig pulse width modulatio. Also, i this period, egative curret flows through D 1, D t1, u, ad tu (cf. Fig. 12(b. The basic strategy cotiues for the rest of the legs accordig to their phase order. imilar to the classical I, this coverter also has six active ad two zero switchig states. Eight switchig states are give i Table II, where state 1 ad 8 provide zero ad the reamig states provide o-zero. C. ie-tragle PWM cotrol scheme I this sectio the PWM scheme of the iverter circuit will be described. Here, aturally sampled sie-triagle PWM (T-PWM method was selected to aalyze the 6- trasistor MC topology. The T-PWM method uses a sigle triagular carrier sigal to compare agaist three siusoidal referece waveforms displaced i time by 120 o [18]. This type of modulatio is geerally termed double-edge aturally sampled modulatio. The equatios for phase voltages usig T-PWM are give below, suz = m cos ω o t = M DC cos ω o t (16 svz = m cos( ω o t = M DC cos( ω o t swz = m cos( ω o t + = M DC cos( ω o t + The fudametal target three-phase lie-lie output voltages are, π suv = suz svz = M DC cos( ω o t + 6 π (17 svw = svz swz = M DC cos( ω o t + 6 π swu = swz suz = M DC cos( ω o t + 6 where, m = output voltage peak magitude, M = modulatio idex = m / DC, ad the referece waveforms are defied by cosiderig z as a fictitious DC bus ceter poit. For simplificatio, it is cosidered that o delay is give betwee the coductio periods of the per phase thyristors. That implies, the PWM switchig of the trasistors will also have o delay betwee the positive ad egative curret flow. I additio, the PWM pulses for ay leg trasistor (i.e. u are idetical for both positive ad egative curret. Evetually the combiatio of these devices per phase esures a typical phase PWM cotrol scheme. TABLE II. WICHING TATE OF THE NOEL TOPOLOGY witchig Devices Output lie voltages state tup+ up tup+ up tup+ wp ab bc ca Figure 1. (a Naturally sampled sie-triagle PWM; (b ad (d thyristor firig pulses ad their coductio periods; (c ad (e trasistors switchig pulses 108

7 Fig. 1(a illustrates the T-PWM geeratio methodology by comparig triagular carrier sigal to a siusoidal referece waveforms for phase a. The resultig switchig pulses by T-PWM method per phase trasistors are show accordigly i Fig. 1(c ad 1(e. Moreover, thyristor firig pulses ad their coductio periods are give pictorially i Fig. 1(b ad 1(d. It is to be oted that i those Fig.s, small blocks represet the firig pulses but the bigger rectagular blocks deote the coductio period of the thyristors.. IMULATION REULT Proposed 6-trasistor MC topology has bee extesively ivestigated utilizig system level simulatio with MATLAB/IMULINK to observe its performace ad feasibility. The simulatio software represets all the switches ad the compoets as ideal. imulatio results of the ovel MC topology are illustrated i Fig. 14 ad 15. ystem level simulatio has bee performed extesively utilizig ope loop cotrol arragemet to verify its performace. imulatio parameters take for aalysis are show i Table III. TABLE III. IMULATION PARAMETER Parameter alue Parameterr alue Iput lie voltage (p-p 220 Rectifier switchig 5400 Hz frequecy Iput filter capacitace 250 μf Iverter switchig 4500 Hz frequecy Iput filter iductace 220 μh Modulatio (M idex 0.8 Iput filter resistace 0.02 Ω Load iductace (L l 20 μh Iput-output frequecy 60 Hz Load resistace (R l 1 Ω Clamp capacitace (C c 1 μf Back EMF (E l 100 (p-p Figure 14. imulatio results: (a Output DC voltage, ad (b curret of the rectifier circuit idc, (c three phase output curret, (d output lie voltage, (e Iput curret ad voltage Fig. 14(a shows the output DC voltage from the rectifier circuit of the coverter. From the Fig. it ca be see that by six itervals switchig techique of the rectifier esures stable DC output voltage. Agai i Fig. 14(b oe ca observe the DC curret waveform with the coditio i DC 0. It is to be oted that the switchig frequecy of the T-PWM algorithm used for the rectifier circuit is 5400 Hz. However, with improved cotrol scheme, better waveforms ca be achieved. Fig. 14(c depicts phase output curret of the iverter utilizig T-PWM with switchig frequecy of 4500 Hz. The waveforms foud through simulatio are ot pure siusoidal, however better performace ca be achieved through improved or developed cotrol scheme. I Fig. 14(d output lie to lie voltage is show. Although the waveforms are slightly distorted but it ca also be improved by developig or utilizig better switchig techique, ad cotrol scheme. It is to be oted that the T- DC bus voltage PWM techique caot utilize the maximumm to produce maximum peak fudametal output lie voltage to the load, whereas the third harmoic ijected T-PWM or space vector PWM (PWM gives 15% ehaced fudametal output with better quality [15]. Fig. 14(e Figure 15. THD of the output curret at 4.5 khz switchig frequecy of the displays the waveforms of the iput phase voltage ( sa = 220 ad phase curret (i a = 5 Amp ad they are foud to be i phase regardless the load type. Therefore, regardless the load type this coverter will provide uity power factor. However, because of the lie side filter, the phase curret leads the phase voltage i this figure. Fially Fig. 15 depicts the THD of the output curret for a 4500 khz switchig frequecy. Because of the slight zero curret itervals eeded to allow the thyristors recover 1084

8 blockig ability a slight icrease i the curret THD was obtaied compared to the covetioal iverter. I. CONCLUION The focal poit of this paper is developig several attractive yet iexpesive alterative topologies at the mid to high power level system. The performace ad feasibility has bee substatiated with system level simulatio with utilizig ope loop cotrol scheme. Performace wise it resembles covetioal topologies but with certai advatages. Thus, these variatios of previous topologies could be a useful alterative solutio cosiderig the attractive features provided by these topologies. They are, Reductio i expesive power trasistor cout High quality iput ad output curret Operatios with uity power factor with ay load type imple clamp circuit with oe diode ad oe capacitor is required Practical implemetatio of the load side coverter could provide greater DC lik voltage utilizatio because it requires sigificatly less dead time. Ulike the covetioal I this I requires dead times oly at zero crossig istace of the output curret sice it cosists of oly oe trasistors per phase. The 6-trasistor ad the 9-trasistor MC allows uidirectioal power flow due their rectifier circuit arragemet. However, its low trasistor cout makes the 6-trasistor MC a very attractive alterative i suitable applicatios, such as permaet maget motor load. Nevertheless, rest of the topologies proposed here, are capable of work i bidirectioal power flow. The compariso table i terms of trasistor switches of covetioal DBMC ad the ovel topology are summarized i Table I TABLE I. REALIZATION EFFORT OF DIFFERENT MC TOPOLOGIE Coverter Type Trasistors Novel Topology Trasistors IMC trasistor IMC 15 MC trasistor MC 12 MC 12 9-trasistor MC 9 ILMC 12 9-trasistor ILMC 9 B-ILMC trasistor B-ILMC 11 UMC 9 6-trasistor UMC 6 Furthermore, future topics of research will cocer, improvemet of the switchig techique to improve the output ad iput voltage waveforms, ad their trasfer ratio, reductio of the harmoic cotets of output waveforms. witchig losses miimizatio of the topologies. Moreover, utilizatio of a closed loop cotrol scheme could improve the performace of the topology i all aspects. These coverters ad the exteded multi-level topologies based o these coverters ca be ivestigated for a umber of future power system applicatios i both medium ad high power systems. REFERENCE [1] M. eturii, A ew sie wave i sie wave out coversio techique which elimiates reactive elemets, Proceedigs of POWERCON , pp. E_1-E_15. [2] A. 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