High performance of cubic AlxGa1-xN/GaN Double Gate MOS-HEMTs

Transcription

1 High performace of cubic AlxGa1-xN/GaN Double Gate MOS-HEMTs Driss BOUGUENNA 1, Nawel KERMAS 2, Bouaza DJELLOULI 2 1 Departmet of Sciece ad Techical (ST), Faculty of Sciece ad Techology, Uiversity of Mascara, 29000, Mascara, Algeria. 2 Laboratory of Modelizatio ad Calculatio Methods, Departmet of Electroic, Uiversity of Saida, Saida, Algeria *** Abstract I this paper, we have compared the performace of cubic Al xga 1-xN/GaN ad IP/I yga 1- yas DG MOS-HEMTs, by aalyzig the impact of gate legth (L G) usig 2D extao 3 software. Driftdiffusio model was take for simulatig the proposed device. The gate legth was varied from (12 to 18) m i a step of 3 m. As gate legth is reduced for scalig, higher drai curret is observed, agai as Idium cotet y of chael layer I yga 1-yAs is icreased, there is a icrease i drai curret desity, while threshold voltage is decrease comparable to IP/I yga 1-yAs DG MOS-HEMT. Except drai curret desity ad threshold voltage all other parameters are acceptable, a eedful to improve the two parameters. However, the proposed model of cubic Al xga 1-xN/GaN DG MOS-HEMT is the ultimate to replace IP/I yga 1-yAs DG MOS-HEMT ad MOSFET for ext-geeratio microwave ad power switchig applicatio fields i the future. Keywords: cubic Al xga 1-xN/GaN, IP/I yga 1-yAs, device simulatio, DG MOSFET, DG MOS-HEMT, extao INTRODUCTION For switchig devices ad digital electroics field-effect trasistors (FETs) with ormally-off characteristics are desirable. Therefore, cubic Al xga 1-xN/GaN without udesirable parasitic piezoelectric ad spotaeous polarizatio fields ad with equal electrical properties for all gate orietatios [1] ad has a sigificat trasport advatages, ad is beig used extesively i research as chael materials for upcomig highly scaly devices [2]. Further the cubic itrides would allow usig the same techology for ormally-o ad ormally-off devices [1]. But, majority of III-V materials have cosiderably smaller bad gap as compared to silico, leadig to excessive bad-to-bad tuelig leakage currets, which evetually limits their scalability beyod 22 m techology ode gate legth (L G) [3]. I HEMT devices, the gate leakage curret ad buffer leakage are importat factors limitig its performace ad reliability. Therefore, the use of a gate oxide helps to improve gate cotact formig a MOS-HEMT, reduce the gate leakage ad icrease drai curret, however, it partly reduces the trascoductace because of a larger gate-to-chael separatio [4]. I this work, we have aalyzed the impact of the gate legth o devices performace of IP/I yga 1-yAs ad cubic Al xga 1-xN/GaN aostructures based DG MOS- HEMT devices. Key devices performace such as drai curret desity ad threshold voltage. Followig by the descriptio of the device structures i Sectio 2, we will discuss the devices simulatio results ad compariso study of a symmetrical uderlap DG MOSFET devices, cubic Al xga 1-xN/GaN ad IP/I yga 1-yAs aostructures based DG MOS-HEMTs switchig devices usig extao 3 software [5]. Moreover, to validate our simulatio results of proposed models we have compared with both results which were obtaied by H. Pardeshi et al [6] ad obtaied by F. Djeffal et al [7]. 2. DEVICE SIMULATION RESULTS I this work, we have simulated the I-V characteristics of three differet device structures such as: silico symmetrical uderlap DG MOSFET, cubic Al xga 1-xN/GaN ad IP/I yga 1-yAs DG MOS-HEMT. However, we have aalyzed the impact of LG o performace gate based cubic Al xga 1-xN/GaN DG MOS-HEMT usig 2D extao 3 software. 2015, IRJET ISO 9001:2008 Certified Joural Page 2072

2 2.1 Device descriptio structures The simulated of a symmetrical uderlap DG MOSFET ad III-V heterostructures devices have the same geometry ad dopig cocetratios, but differet chael materials ad gate legths. We have cosidered three structures: the first structure cosists of a symmetrical uderlap DG MOSFET used i our simulatio is show i Fig.1, where L G = 10 m is the gate legth, L u = 5 m is the uderlap symmetrical legths o both the source ad drai sides, t bd = t Si= 3 m is the udoped ultrathi body (UTB) thickess ad t Ox = 1 m is the gate oxide thickess. The secod structure cosists of the cubic Al xga 1-xN/GaN DG MOS-HEMT is show i Fig.2, where the gate legth L G variable from (12 to 18) m, i steps of 3 m ad Al cotet x i the barrier layer Al xga 1-xN (x = 30 %), with ultrathi t bd = 6 m. The body cosists of cubic GaN chael t Ch ad Al xga 1-xN barrier tb, where tbd = t Ch + 2.tb. For aalyzig the ifluece of L G, t Ch is kept costat at 2 m ad t b = 2 m. The source/drai legths are kept fixed L u = 5 m, the upper ad lower gate oxide thickess t Ox = 1.2 m with SiO 2 dielectric to miimize the gate leakage. The source ad drai regios are also assumed to be heavily doped with -type dopig cocetratio N D = cm-3 ad uses abrupt dopig profile at source/drai eds. Furthermore, we have assumed also a symmetric uderlap from source-to-gate ad gate-to-drai sides. While the third structure cosists of IP/I yga 1-yAs DG MOS-HEMT devices is show i Fig.3, where Idium cotet y i the chael layer I yga 1-yAs is variable (53 % ad 75 %), the gate legth L G = 18 m, ad tbd = 6 m is the ultrathi body thickess. The body cosists of t Ch is the I yga 1-yAs chael ad tb is the IP barrier thickess, where tbd = t Ch + 2.tb are assumed i this work. For aalyzig the impact of Idium cotet y, keepig barrier ad chael thickess costat (t b = 2 m ad t Ch = 2 m). ad is lattice matched cubic Al xga 1-xN. A arrow bad gap cubic GaN layer is sadwiched betwee the two wide bad gap cubic Al xga 1-xN barrier layers ad the chael is cofied at the heterostructure iterfaces. The barrier layer used has the coductio bad edge offset with the chael ad is early the lattice matched with the arrow bad layer to miimize the traps at its iterface with the chael [8]. Fig. 1: Schematic structure of a symmetrical uderlap DG MOSFET. Fig. 2: Schematic structure of cubic Al xga 1-xN/GaN aostructures based DG MOS-HEMT. Moreover, the device chael cosists of III-V heterostructure cosistig of arrow bad I yga 1-yAs t Ch layer ad two layers of wide bad IP (t b). I yga 1-yAs has high electro mobility ad is lattice matched IP [7]. While, the chael of secod device cosists of arrow bad cubic GaN (t Ch) layer ad two layers of wide bad cubic Al xga 1-xN (t b). Cubic GaN has high electro mobility 2015, IRJET ISO 9001:2008 Certified Joural Page 2073

3 (1) E 1 1 E 0 Simulatio at differet voltages Fig. 3: Schematic structure of IP/I yga 1-yAs aostructures based DG MOS-HEMT. Fig.4 shows the electrical output characteristics of a symmetrical uderlap DG MOSFET are calculated usig 2D extao3 at gate voltage VG is varied from 0.05 V to 0.5 V with a step of 0.05 V ad at room temperature. For low drai bias the liear drive curret is directly proportioal to the coductivity ad for high drai bias the saturated drive curret is proportioal to the carrier desity. I order to validate the simulatio results ad calibratio of our proposed model parameters we have compared with the results obtaied by F. Djeffal et al [7]. 2.2 Results ad discussio The desity gradiet model used i the umerical simulatio, solves the quatum potetial equatios self cosistetly with the Poisso s equatio ad carrier cotiuity equatios. The quatum potetial is itroduced to iclude quatizatio effects i a classical devices simulatio. Desity gradiet trasport model is used maily i simulatig aoscale devices, such as sigle gate MOSFETs, ad DG MOSFETs, FiFETs ad uderlap structures. A quatizatio effect is used to aalyze the carrier trasport i the iterface betwee the two dissimilar bad-gap semicoductor materials [8]. Moreover, the two-dimesioal drift-diffusio model umerical simulatio has bee carried out usig 2D extao3 software. This model of drift-diffusio uses to solve the Poisso s equatio self-cosistetly with carrier cotiuity equatio. We have assumed the mobility-model-simba-2 [5], if the expoets kappa,p (k,p) are temperature depedet the this equatio is called Caali model (with µ,p as the low field mobility) with suitable modificatios to precisely capture the oequilibrium carrier trasport [9] with suitable modificatios to precisely capture the o-equilibrium carrier trasport. Fig. 4: The output characteristics of a symmetrical uderlap DG MOSFET are calculated usig extao 3 at differet gate voltages where L G = 10 m, t Si = 3 m ad t Ox = 1 m. The I D-V GS trasfer characteristics of a symmetrical uderlap DG MOSFET at differet drai voltages V D are show i Fig.5 are calculated usig 2D extao 3. By varyig of the gate-to-source potetial, the curret icreases due to icrease of carrier desity i.e. 2DEG i chael. For validatig the simulatio results ad calibratio of the model parameters are compared with umerical simulatio results ad experimetal values [10]. 2015, IRJET ISO 9001:2008 Certified Joural Page 2074

4 2 m). Reductio of curret was observed as gate legth icreases because of icrease of chael resistace. The peak value of drai curret obtaied A/m at L G = 12 m, t b = 2 m, ad V D = 0.5 V. Variatio i Idium cotet y withi the I yga 1-yAs chael layer Fig. 5: I D-V GS trasfer characteristics of a symmetrical uderlap DG MOSFET are calculated usig extao 3 at differet drai voltages where L G = 10 m, t Si = 3 m ad t Ox = 1 m. Fig.7 shows the curret-voltage characteristics of IP/I yga 1-yAs DG MOS-HEMT at differet Idium cotet y i the I yga 1-yAs chael layer. Our simulatio results are showed that at y = 75 %, IP/I yga 1-yAs DG MOS-HEMT reaches the peak value of drai curret obtaied is A/m at L G = 18 m, t b = 2 m, ad V D = 0.5 V usig drift diffusio model. Variatio i gate legth of cubic Al xga 1- xn/gan DG MOS-HEMT The I D-V GS trasfer characteristics of cubic Al xga 1-xN/GaN DG MOS-HEMT at V D = 0.05 V ad 0.5 V are show i Fig.6. With varyig of the gate-to-source potetial, the curret icreases due to icrease of carrier desity i.e. 2DEG i chael. Fig. 7: I D-V GS characteristics of IP/I yga 1-yAs DG MOS- HEMT where t bd = 6 m ad L u= 5 m. The applied drai voltage is V D = 0.05 V ad VD = 0.5 V at differet Idium cotet y. Comparative study o I-V characteristics of cubic Al xga 1-xN/GaN ad IP/I yga 1-yAs DG MOS-HEMTs Fig. 6: ID-VGS trasfer characteristics of cubic Al 0.3Ga 0.7N/GaN DG MOS-HEMT at V D = 0.05 V ad 0.5 V ad for L G-depedet at room temperature usig extao 3. The gate legth is varied from (12 to 18) m i a step of 3 m, keepig barrier ad chael thickess costat (barrier thickess, t b = 2 m ad chael thickess, t Ch = Fig.8 shows simulated curret-voltage characteristics of both devices, by varyig the gate-to-source potetial, the drai curret icreases due to icrease of carrier desity. Keepig gate ad uderlap legths costat (gate legth, L G = 12 m ad uderlap legth, L u = 5 m). We could be obtaied excellet characteristics clearly depictig higher drai level for cubic Al 0.3Ga 0.7N/GaN DG MOS-HEMT devices, arisig from high mobility ad coductivity tha IP/I 0.75Ga 0.25As DG MOS-HEMT devices. We have observed a good drai 2015, IRJET ISO 9001:2008 Certified Joural Page 2075

5 curret saturatio arisig from cosiderably lower, with double gate providig much better chael cotrol [11]. High mobility ad coductivity leads to higher drive curret at both (low ad high) drai biases, which have great sigificace for high speed logic applicatios. For low drai bias the liear drive curret is directly proportioal to the coductivity ad for high drai bias the saturated drive curret is proportioal to the carrier desity, as well as the carrier ijectio velocity. The carrier ijectio velocity i tur depeds o the low field carrier mobility ad effective mass m* [12]. The trasfer characteristics of both devices are compared i Fig.9 at V D = 0.5 V by varyig the gate-tosource potetial curret. The gate legth is varied from (12 to 18) m i a step of 3 m, keepig barrier ad chael thickess costat (t b = t Ch = 2 m). As devices are scaled for ehacig the performace, short chael effects start to domiate. The curret-voltage characteristics of the DG MOS- HEMTs are aalyzed. Thus exploitatio of high mobility/wide bad gap characteristics ca be doe usig ew structure of devices, such as cubic Al xga 1- xn/gan DG MOS-HEMT. Furthermore, with high-κ dielectric provides higher ON-curret. Fig. 9: I D versus V G characteristics of both devices where applied drai voltage is V D = 0.5 V, t bd = 6 m, L u = 5 m, ad gate legth L G is varied from (12 to 18) m with a steps of 3 m for both devices. O the other had, the simulatio results of the device characteristics of cubic Al xga 1-xN/GaN DG MOS-HEMT are compared with IP/I yga 1-yAs DG MOS-HEMT for various gate legths at drai bias of 0.5 V. The maximum source-to-drai curret of these devices is i the order of some hudred A/m. Therefore IP/I yga 1-yAs based DG MOS-HEMT is applicable for high speed applicatios ca be viewed as replacemet of MOSFET compared to cubic Al xga 1-xN/GaN DG MOS-HEMT is applicable for ultrahighspeed logic amplificatios, high power switchig, ad high temperature applicatio fields. Thereby, the drai curret of cubic Al xga 1-xN/GaN DG MOS-HEMT is a factor 40% higher tha the same curret of IP/I yga 1-yAs based DG MOS-HEMT at V GS = 0.8 V ad L G = 12 m. 3. CONCLUSION AND OUTLOOK Our simulatio results idicate that, the cubic Al xga 1- Fig. 8: I D versus V GS characteristics of both devices, where L G = 12 m, t bd = 6 m, ad L u = 5 m are kept fixed costats. The applied drai voltage is V D = 0.05 V ad V D = 0.5 V for both devices. xn/gan DG MOS-HEMT provide higher ON-curret at L G = 12 m ad V D = 0.5 V compared with IP/I 0.75Ga 0.25As is lower which is acceptable for the devices performace, eedful improvemets are required. However, ultrashort cubic Al xga 1-xN/GaN MOS-HEMTs eed DG structures to overcome the weakess of short chael effect caused by their arrow bad gap ad small electro effective mass. From the futuristic poit of view, our simulatio results showed that the device desigs of cubic Al xga 1-xN/GaN DG MOS-HEMT could be proposed as replacemet of IP/I yga 1-yAs DG MOS-HEMT ad MOSFET i the future. We therefore clearly establish the potetial of usig cubic Al xga 1-xN/GaN DG MOS-HEMT is 2015, IRJET ISO 9001:2008 Certified Joural Page 2076

6 useful for ultrahigh-speed logic amplificatios of extgeeratio, high power switchig, ad high temperature applicatio fields. Double Gate techologies with proper desig parameters are attractive for couteracts the effect of carrier ijectio ito the device buffer (sice o buffer is used i the device structures). [10] Sudhasu Kumar Pati, Hemat Pardeshi, Godwi Raj, N. Moha Kumar, Chada Kumar Sarkar, "Impact of gate legth ad barrier thickess o performace of IP/IGaAs based Double Gate Metal Oxide-Semicoductor Heterostructure Field-Effect Trasistor (DG MOS-HFET", Superlattices ad Microstructures vol. 55, pp. 8-15, Mar REFERENCES [1] S. Raja, P. Waltereit, C. Poblez, S. J. Heikma, D. S. Gree, J. S. Speck ad U. K. Mishra, "Power performace of AlGaN/GaN HEMTs grow o SiC by plasma-assisted MBE", IEEE, Electro Device Letters, vol. 25, pp , May [2] S. Haffouz, H. Tag, J. A. Bardwell, E. M. Hsu, J. B. Webb, ad S. Rolfe, "AlGaN/GaN field effect trasistors with C-doped GaN buffer layer as a electrical isolatio template grow by molecular beam epitaxy", Solid-State Electro, vol. 49,.5, pp , May [3] J. Schörma, S. Potthast, D. J. As, K. Lischka, "Near UV Emissio from No-polar Cubic AlxGa1-xN/GaN Quatum Wells", Appl. Phys. Lett, vol. 89,.13, pp , Sep [4] E. Tschumak, R. Grazer, J. K. N. Lider F. Schwierz, K. Lischka, H. Nagasawa, M. Abe, ad D. J. As, "Nopolar cubic AlxGa1-xN/GaN heterojuctio fieldeffect trasistor o Ar+ implated 3C SiC (001)", Appl. Phys. Lett, vol. 96,.25, pp , Jue [5] Wu Lu, Almaz Kuliev, Steve J. Koester, Xie-We Wag, Jack O. Chu, Tso-Pig Ma, Ilesami Adesida, "High Performace 0.1 µm gate-legth P-Type SiGe MODFET s ad MOS-MODFET s", IEEE Trasactios o Electro Devices, vol. 47,.8, pp , Aug [6] H. Pardeshi, S. K. Pati, G. Raj, N. Mohakumar, ad C. K. Sarkar, "Effect of uderlap ad gate legth o device performace of a AlIN/GaN uderlap MOSFET", Joural of Semicoductors, vol. 33, No. 12, pp , Dec [7] Olie Available ad [8] H. Pardeshi, G. Raj, S. K. Pati, N. Mohakumar, C.K. Sarkar, "Comparative assessmet of III-V heterostructure ad silico uderlap double gate MOSFETs", Semicoductors, vol. 46,.10, pp , Oct [9] F. Djeffal, Z. Dibi, M. L. Hafiae, D. Arar, "Desig ad simulatio of a aoelectroic DG MOSFET curret source usig artificial eural etworks", Materials Scieces ad Egieerig C, vol. 27,.5-8, pp , Sep BIOGRAPHIES Driss BOUGUENNA received the Ph.D degree i electroics from the Uiversity of Sciece ad Tcchology of Ora, Ora, Algeria i Sice 2007, he is a titular Professor with Departmet of Sciece ad Techology, Faculty of Sciece ad Techology, Mascara Uiversity, Mascara, Algeria. His curret research iterests iclude the modellig ad simulatio of III-V trasistors HEMTs. Nawel KERMAS is curretly pursuig the Ph.D. degree from Uiversity of Saida, Saida, Algeria. Here curret research iterests iclude the modellig of III-V trasistors HEMTs. 2015, IRJET ISO 9001:2008 Certified Joural Page 2077