VARIATIONS in process parameter values and on-chip

Transcription

1 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 1 Comact Curret Source Models for Timig Aalysis uder Temerature ad Body Bias Variatios Saket Guta, ad Sachi S. Saatekar, Fellow, IEEE, Abstract State-of-the-art timig tools are built aroud the use of curret source models CSMs, which have rove to be fast ad accurate i eablig the aalysis of large circuits. As circuits become icreasigly exosed to rocess ad temerature variatios, there is a strog eed to augmet these models to accout for thermal effects ad for the imact of adative body biasig, a comesatory techique that is used to overcome ochi variatios. However, a straightforward extesio of CSMs to icororate timig aalysis at multile body biases ad temeratures results i ureasoably large characterizatio tables for each cell. We roose a ew aroach to comactly cature body bias ad temerature effects withi a maistream CSM framework. Our aroach features a table reductio method for comactio of tables ad a fast ad ovel waveform sesitivity method for timig evaluatio uder ay body bias ad temerature coditio. O a 45m techology, we demostrate high accuracy, with mea errors of uder 4% i both slew ad delay as comared to HSPICE. We show a seedu of over five orders of magitude over HSPICE ad a seedu of about 92 over covetioal CSMs. I. INTRODUCTION VARIATIONS i rocess arameter values ad o-chi temeratures have grow larger with shrikig feature sizes. Process variatios occur due to heomea such as roximity effects i hotolithograhy, o-uiform coditios durig deositio, ad radom doat fluctuatios, ad lead to fluctuatios i arameters such as trasistor dimesios, oxide thickesses, ad doat cocetratios [1] [3]. Ochi temerature variatios occur due to ower dissiatio i the form of heat. Such thermal variatios have a sigificat bearig o the mobilities of electros ad holes, as well as the threshold voltage of the devices. These effects have led to icreased shifts i circuit erformace, due to which a sigificat fractio of the total umber of accetable dies may fail to achieve the rescribed erformace goals. To overcome this roblem, desigers must build resiliet circuits that meet their erformace goals i site of these variatios. A key eabler for variatio-tolerat desig is the ability to simulate the timig behavior of a circuit durig the desig rocess usig static timig aalysis STA. Traditioal stadard cell modelig aroaches rereset the delay ad outut slew as oliear fuctios of the iut slew ad outut Mauscrit received October 18, 21; revised August 1, 211. This work was suorted i art by the SRC uder cotract 27-TJ-1572 ad by the NSF uder award CCF The authors are with the Deartmet of Electrical ad Comuter Egieerig, Uiversity of Miesota, Mieaolis MN, 55455, USA saket@um.edu load caacitace [4]. Whe itercoect resistace became sigificat, these methods were relaced by the otio of effective caacitace [5]. However, this aroach models the iut as a saturated ram with iecewise costat sloe, ad was further ehaced by the develomet of CSMs, which rereset a cell as a voltage cotrolled curret source ad rovide fast ad accurate timig estimates. A CSM aroach termed as Blade [6] reresets the cell as a voltage-cotrolled curret source VCCS with a iteral caacitace ad a time-shifted iut waveform drivig a arbitrary load. A looku table, idexed by the iut voltage, V i, ad the outut voltage, V out, models the VCCS curret, I out. These ideas were further refied i [7] [12]. The work i [7], [8] removed the assumtios of liearity, ad [9] [12] addressed multile iut switchig ad stack effects. Further, a curret source model based o orthogoal fuctios was roosed i [13], ad a aroach based o the small-sigal model of a trasistor was built i [14]. Withi the CSM framework, rocess variatios are commoly catured through the use of rocess corers. Traditioally, temerature variatios were also hadled usig corerbased methods, but this is o loger viable. Corer-based aroaches are redicated o the idea that the timig varies mootoically over the temerature rage, but this is o loger the case with thermally-drive variatios [15]. I aometerscale techologies, elevated temeratures cause reductios i device mobilities which ted to icrease the delay as well as reductios i threshold voltages which ted to decrease the delay. The iterlay betwee these effects may cause the circuit delay to icrease mootoically egative temerature deedece, decrease mootoically ositive temerature deedece, or vary omootoically mixed temerature deedece with temerature. I the last case, the worst case may occur i the iterior of the temerature rage, rather tha at its edges. As a result, a set of temerature corers is o loger adequate, ad circuit delays must be simulated as fuctios of temerature. Therefore, a first ecessary ehacemet of CSMs ivolves extedig them to determie the cell delay as a fuctio of temerature. This caability is useful ot oly for circuit aalysis but also for buildig otimizatio techiques that comesate for temerature variatios [3], [16] [19]. A secod way i which CSMs require augmetatio is i buildig a ability to simulate cell timig i the resece of body biases. The alicatio of adative body biases ABBs allows circuits to be made resiliet ad variatio-tolerat by

2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 2 alyig a deliberate bias to the body termials of trasistors i a circuit. Realistically, ABB is alied at coarse levels of graularity, e.g., by biasig idividual -wells ad/or -wells, each of which cotais a umber of trasistors. Forward body bias FBB effectively reduces the trasistor threshold voltage ad seeds u the device, at the cost of icreased leakage, while reverse body bias RBB achieves the oosite effect o seed ad leakage. ABB ivolves the use of FBB or RBB to hel dies recover from variatios, ad may be alied dyamically to tighte the distributio of the dies with maximum oeratioal frequecy, while simultaeously meetig the leakage ower costraits [1] [3], [17], [2]. Traditioal CSMs simulate the circuit at fixed values of the body bias v b = v b = ad at fixed values of the temerature. The obvious extesios to existig CSMs that eable them to cature body biases ad temerature effects are rather iefficiet. I ricile, the body termial of a device ca be cosidered to be aother ort, ad the cell ca be accordigly characterized by creatig a look-u table for various combiatios of body biases, v b,v b. Further, such looku tables would have to be costructed for various temerature values. However, this icreases the amout of memory used as well as the characterizatio time sigificatly over the zero body bias ad the omial temerature case. For istace, for 1 values each of v b ad v b, ad for 1 values of temerature, the table for each library cell becomes 1 larger. The eed to access a larger looku table may also result i a sigificat cocomitat icrease i the simulatio rutime of CSM macromodels. This aer develos efficiet timig characterizatio methods for buildig CSMs that icororate chages i the body bias ad the temerature. Sice ABB is alied at the graularity of a well, we assume that all PMOS trasistors i a cell have the same body bias value, v b, ad all NMOS devices are biased at v b. Further we assume that all trasistors i the cell exeriece a uiform temerature: this is reasoable, sice the rate of decay of temerature with resect to the distace from the cell has a time costat that is sigificatly larger tha the size of a cell. Our framework for icororatig effects of body bias ad temerature ito the CSM has a very small memory ad rutime overhead, while maitaiig high levels of accuracy. Our mathematical framework cosists of two key stes. First, we itelligetly adat a existig scheme to eable the comactio of look-u tables for the sesitivities of CSM comoets to body bias ad temerature, over the rage of allowable values of both the alied body bias ad ochi temerature. Our secod key cotributio is to develo a ovel waveform sesitivity model for evaluatig the imact of the alied body bias ad variatios i temerature, which rovides accurate waveforms at the outut of the cell uder ay body bias or temerature coditio, with miimal comutatio. The essetial idea of this aroach is that sice body bias or temerature variatio costitutes a small erturbatio to the omial waveform, it should be ossible to determie the erturbed waveform chealy by determiig ad savig the arameters that comute its shift from the omial waveform. We develo a scheme for characterizig this erturbatio ad comutig it efficietly. Secifically, mathematical models for such arameters are develoed ad further aalyzed for their ideedece over body bias ad temerature variatios for a efficiet comutatio of such arameters. The remaider of the aer is orgaized as follows. Sectio II resets the develomet of sesitivity models for CSM comoets to hadle variatios i body bias ad temerature. Sectio III resets our algorithms for comactig the CSM sesitivity tables. The we reset the covetioal macromodel solvers used i state-of-the-art CSMs i Sectio IV, ad is followed by a descritio of our method for fast outut waveform evaluatio i Sectio V. Sectio VI resets exerimetal results o a set of library cells i a 45m techology. We the reset the coclusio of our work i Sectio VII. II. CSM SENSITIVITY MODEL DEVELOPMENT Fig. 1: Examle of a CSM: the outut ort is modeled as a oliear VCCS deedet o all iut ort voltages, i arallel with a oliear caacitace. The CSM is a gate-level black-box abstractio of a cell i a library, with the same iut ad outut orts as the origial cell. Our CSM structure, show i Figure 1, is of the tye roosed i [6], ad is augmeted to model oliearities as i [9]. Secifically, outut ort is relaced by a oliear voltagecotrolled-curret-source VCCS, I, i arallel with a oliear caacitace, C. The VCCS model eables the CSM to be load-ideedet, ad ermits it to hadle a arbitrary electrical waveform at its iuts. The CSM is characterized i terms of the value of I ad the charge, Q, stored o the caacitor, C. The variables, I ad Q, are fuctios of all iut ad outut ort voltages ad temerature, ad are determied by characterizig the cell at various ort voltages, body bias combiatios ad temeratures as follows: I = FV i,v o,v b,v b, T 1 Q = GV i,v o,v b,v b, T 2 The arameters I ad Q are modeled usig the fuctios F ad G, resectively, ad V i ad V o are, resectively, the voltages at the trasitioig iut ad outut orts of the cell. We use the term T to rereset the temerature offset from a baselie temerature value, take here to be room temerature 25 C. I the temerature rage of [ 25 C, 125 C] that we work i, the rage for the values of T is [ 5 C, 1 C]. For a cell, I characterizatio ivolves DC simulatios over multile combiatios of DC values of V i,v o, while Q is characterized through a set of trasiet simulatios [9]. The

3 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 3 resetatio of our model is targeted to the more widelyused sceario of sigle-iut switchig for gates with a sigle outut, though the idea ca easily be exteded to multile iut switchig MIS ad multioutut gates, leveragig curret work o CSMs o these toics [9], [11], [12]. As metioed earlier, i order to cature the sesitivity of CSM arameters to the alied body bias ad temerature offset, i ricile, the circuit could be characterized over a set S of all ossible v b,v b, T oits, treatig body termials as iut orts, ad temerature offset as the ideedet variable. Sice the allowable values of the alied body biases ad temerature offset chage i discrete stes, the cardiality of this set is large, ad the corresodig characterizatio would be comutatioally itesive, eve as a recharacterizatio ste that is to be erformed oce for a techology. Moreover, memory requiremets of the table multily sigificatly over the curret characterizatio rocedure at zero body bias ad zero temerature offset. We observe through simulatios that the fuctios F ad G deed much more weakly ov b,v b, ad T as comared to V i or V o. Hece, a simler model ca be utilized to save o this comutatio. We thus develo sesitivity models of CSM with resect to v b, v b ad T as we will soo show, the models with resect to body bias ad temerature are ideedet, ad the reset a scheme to icororate the effects of the two. A. Ideedece of Body Bias ad Temerature Effects Next, we exlai the ratioale for aalyzig the effects of body bias ad temerature ideedetly. Body bias a chage i the substrate bias voltage, V BS chages the threshold voltage, V th. The sesitivity of V th with resect to V BS ca be catured from followig equatio [21]: V th V BS = C de C ox 3 where C de is the deletio caacitace of the MOS trasistor ad C ox is the oxide caacitace. C de is a very weak fuctio of temerature, beig roortioal to the iverse square root of the built-i otetial. Similarly, it is observed that the exressio for V th sesitivity with resect to temerature is ideedet ofv BS [21]. Hece, the effects of chages i body bias ad temerature o MOS trasistors ca be treated as ideedet. SiceI adq essetially abstract the iteral cell behavior, the effects of body bias ad chages i temerature o I ad Q ca also be assumed to be ideedet. This is further verified by the model formulatios ad accuracy results as reseted i the subsequet subsectios ad sectios. B. CSM Body Bias Sesitivity Model We first reset the body bias sesitivity model, which is ideedet of the chages i temerature ad costructed at T = C i.e., at room temerature. We costruct a olyomial aroximatio for the variatios of I ad Q with resect to v b,v b. Our simulatios show that a liear aroximatio yields a average of 2.% relative error with resect to HSPICE, evaluated over all v b,v b oits, for all V i,v o oits. The CSM is ow modified by usig the equatios: I V i,v o,v b,v b, Q V i,v o,v b,v b, = I Z 1+a I V i,v o v b +b I V i,v o v b 4 = Q Z 1+a Q V i,v o v b +b Q V i,v o v b 5 where I Z = FV i,v o,,,, Q Z = GV i,v o,,,, ad {a I, b I, a Q, b Q } corresod to the sesitivity of the fuctio to the corresodig body bias. These arameters are characterized at a discrete set of V i,v o values ad are saved i a looku table. The characterizatio of I ad Q usig equatios 4 ad 5 ca ow be carried out usig a miimum of three simulatios at eachv i,v o, sice it is a liear model; however, additioal redudacy is referable to accout for the small oliearities, ad a liear least squares fit ca be used istead. For otatioal simlicity, we will defie the followig fuctios: L I v b,v b = 1+a I V i,v o v b +b I V i,v o v b 6 L Q v b,v b = 1+a Q V i,v o v b +b Q V i,v o v b 7 Clearly, I V i,v o,v b,v b, = I Z L I v b,v b 8 Q V i,v o,v b,v b, = Q Z L Q v b,v b 9 C. CSM Temerature Sesitivity Model We ow costruct the temerature sesitivity model at zero body bias. We observe that the variatios of I ad Q with T are oliear, ulike the body bias case where a liear aroximatio was adequate. We emloy a secodorder olyomial aroximatio, ad fid that the fit has a average relative error of 1.6% relative error i comariso with HSPICE simulatios. The CSM for the temerature sesitivity model with the first ad secod order sesitivities i temerature offset is ow rereseted by the followig modified equatios: I V i,v o,,, T = I Z 1+c I V i,v o T +r I V i,v o T 2 1 Q V i,v o,,, T = Q Z 1+c Q V i,v o T +r Q V i,v o T 2 11 where I Z,Q Z are as defied above, ad {c I,c q,r I, r Q } corresod to the sesitivity of the fuctio to the corresodig owers of the temerature offset, T. As i the case of {a I, b I, a Q, b Q }, these arameters are characterized at a discrete set of V i,v o values ad saved i a looku table. Sice the temerature sesitivity model is a secod order model, we eed at least three oits to determie the values of{c I,r I,c Q,r Q }. As before, for otatioal simlicity, we will defie the followig fuctios: S I T = 1+c I V i,v o T +r I V i,v o T 2 12 S Q T = 1+c Q V i,v o T +r Q V i,v o T 2 13

4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 4 Clearly, I V i,v o,,, T = I Z S I T 14 Q V i,v o,,, T = Q Z S Q T 15 a iitial 2 2 table corresodig to the oits at the four corers of the table. Next, this table is exaded to iclude additioal etries usig the idea of h-hos. D. CSM Comlete Sesitivity Model The comlete body bias ad temerature sesitivity model ca ow be formulated by itegratig the models of I ad Q with body bias from equatios 8, 9, ad with temerature offset from equatios 14, 15. The comlete model is costructed as follows: I V i,v o,v b,v b, T = I Z L I v b,v b S I T 16 Q V i,v o,v b,v b, T = Q Z L Q v b,v b S Q T 17 Simulatios show that the above model yields aroximatios with a average of 2.9% relative error with resect to HSPICE. This also justifies our assumtio that the effects of body bias ad chages i temerature o CSM comoets ca be aalyzed ideedetly. III. COMPACT CSM FORMULATION As described i Sectios I ad II, the looku tables obtaied for {a I,b I,a Q,b Q } ad {c I,r I,c Q,r Q } reduce the excessive memory requiremets described i Sectio I. However, we still eed a searate looku table idexed by V i,v o for each arameter of every cell i the library. If we ca further reduce the size of these tables by suitably comactig them, we ca gai more i terms of memory overheads iduced. We thus reset the develomet of a comact looku table scheme used for reducig the size of such looku tables. A. Table Size Reductio for Covetioal CSMs As a relimiary ste, we attemt to aly the method i [22] to create comact looku tables for I ad Q for the zero body bias ad omial temerature case, i.e., I Z ad Q Z, with cotrolled loss of accuracy. For geeral values of the body bias ad temerature, we must also create looku tables for {a I, b I, a Q, b Q } ad {c I, r I, c Q, r Q } at each value of V i,v o : as we will see, for these arameters, a direct extesio of the method i [22] does ot yield satisfactory results. We first overview the rocedure i [22]. This method begis with a table of characterized oits, idexed by variables x ad y i the horizotal ad vertical directios, resectively. The idea behid table size reductio is to kee a subset of all these oits ad to iterolate the rest. For istace, cosider the rectagle bouded by oits x 1,y 1,x 2,y 1,x 2,y 2, ad x 1,y 2 : a oit x,y withi this rectagle ca be droed if the iterolatio error i its value, usig these oits lies withi a secified boud. Istead of a exesive eumeratio, the work i [22] resets a dyamic rogrammig method for reducig a twodimesioal table. The objective of the algorithm is to create a smaller m m table, where m is resecified, while miimizig the total error corresodig to the oits that are droed from the table. The rocedure begis by costructig Fig. 2: The iitial ste, cosiderig all rectagles from ay oiti,j, extedig to ay oitk,l at the ortheast corer. a Fig. 3: a A 1-ho solutio from i,j to,, through a itermediate oit, k,l. b A 2-ho solutio from 1,1 to, through a itermediate oit, k, l uses a reviously comuted otimal 1-ho solutio from k,l to,. I the iitial ste, we cosider all rectagles origiatig at a oit i,j at the southwest corer, extedig to ay oit k,l at the ortheast corer, as show i Figure 2. We comute the error metric over the rectagle, corresodig to the case where oly the oits at the four corers of the rectagle are ket i the looku table, ad all iteral oits are droed. The error metric is the sum of the iterolatio errors for all oits withi ad o the erimeter of the rectagle. Each such rectagle corresods to a otimal substructure for dyamic rogrammig: the otimal solutio will be comosed from some but ot all such substructures. Next, we defie a 1-ho oeratio. We otimize the regio bouded by oit i,j to the southwest ad, to the ortheast by fidig a otimal oit k, l withi this regio. Here, otimality is defied as follows: the oit k, l divides the regio ito four subregios, as show i Figure 3a, ad over all cadidate k, l oits, the otimal oit miimizes the total error summed u over these four subregios. Sice the error over each rectagle was calculated i the iitial ste, this ste ivolves eumeratig all cadidate k, l oits, ad summig u the reviously calculated error over the rectagles i costat time for each such oit. We refer to this as a 1- ho, idicatig that for each i,j, the table hos over a sigle oit, corresodig to the otimal k,l, o the way to,. The associated otimal error ecoutered is the 1-ho error for i,j. I geeral, a h-ho from i,j to, fids a oit k,l such that the error from i,j to k,l, lus the h 1-ho error from k,l to,, is miimized over all cadidate b

5 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 5 oits k,l. To obtai a m m table, the rocedure stos after m 1 hos, ad the otimal m-ho from 1,1 to, rovides the comact table. Figure 3b shows a examle of a 2-ho solutio from P1,1 to P,; if the algorithm were to sto here, it would result i a 4 4 comacted table. The comutatioal comlexity of this algorithm is Om 4, but as is tyically small = 3 i our simulatios, this remais tractable, as we will show i Sectio VI-A that the rutimes for this scheme are reasoable. It should be oted that although this method roceeds alog the mai diagoal of the table i the orth-east directio, the iterolatio error is comuted by cosiderig all the four ed oits of a rectagle i Figure 3a for istace. Thus, it also cosiders the iterolatio error iduced alog the other diagoal, ad the rows ad colums of the table as well. While this method is ot exact for examle, for a h-ho, it does ot etertai the ossibility of a h 1 ho to k,l ad the a 1-ho to,, i ractice it is see to work well. A faster versio of the algorithm, which trades off accuracy for seed, is also roosed i [22]. B. Modificatios for Sesitivity Tables As stated earlier, the above aroach works well for characterizig I ad Q, where eighborig etries have similar magitudes. However, i case of the sesitivity arameters, {a I, b I, a Q,b Q } ad {c I, r I, c Q,r Q }, there ca be large differeces i the values of eighborig arameters. This is illustrated i Figure 4a ad b, which show, resectively, the values of a Q = Q / v b ad c I = I / T for a iverter cell 1. Large outliers i.e., values of large magitude are clearly visible o the lot. The resece of these outliers is attributed to the ature of variatio of the values ofi Z adq Z withv i,v o, ad the way these values are derived i the CSM. At a articular V i,v o bias oit, it is quite ossible that oly a small curret flows iside the iut ad outut termials of the cell. Sice the magitudes of these iflowig currets decide the values of I Z ad Q Z, the values of resultat I Z ad Q Z are also small. Hece, ay chage relative to this small value becomes large ad is reflected as a large sesitivity value. I ricile, sice these I Z ad Q Z values are small, we may cosider settig the corresodig sesitivities to zero. This, however, has bee observed to create iaccuracies i waveform evaluatios the waveform evaluatio techiques are described i Sectios IV ad V for whe such chages are multilied by other quatities with relatively higher magitudes temerature offset for istace, the et cotributio from these small chages, to the comuted values of V o t or of the waveform sesitivities, becomes sigificat, ad hece caot be eglected. For such data, it ca easily be show that the aroach i [22], which deeds o griddig the table i the coordiate directios, is oorly comacted, i.e., the iterolatio errors i the reduced table are large. Such errors are demostrated to be easily visible i the outut resose, where they aear as 1 Similar behavior is see for a I, b I, b Q, r I, c Q, ad r Q. kiks i the CSM-based waveform that do ot exist i the corresodig HSPICE waveform. This haes due to the fact that a iterolatio error caused by the resece of these outliers causes a error i I ad Q values, which causes the solver described i the ext sectio to geerate errors i outut waveforms. A samle waveform with the use of comacted I ad Q tables, as geerated by the solver for a risig iut ram is show i Figure 5. As is see, due to oor comactio, kiks aear i the evaluated waveform. The icorrect waveform also icurs slew ad delay errors. Sesitivity Body Bias Sesitivity Distributio 1 V i idex 2 a V idex o c Sesitivity Temerature Sesitivity Distributio V idex o 3 b V i idex Fig. 4: The CSM sesitivity arameter distributio for a a Q ad b c I as fuctios of V i,v o. c The resultat looku table for a Q, whe all the outliers have bee removed ad saved searately i a table. We roose a simle method for avoidig these roblems, based o the observatio that for these sesitivity arameters, such outliers are few i umber ad have relatively large magitudes. We therefore tabulate ad save the outliers searately. As ca be observed from Figure 4a ad b, the umber of outliers is quite small comared to the total umber of data oits. Thus, a searate tabulatio of outliers would icur egligible overhead. I order to tabulate the outliers searately, give the set of all oits, we fid the mea ad variace over all etries. Ay etry that is over k variaces from the mea is foud to be a outlier; i ractice, we fid k = 2 to be a adequate value. The removed etry at table locatio x,y is the relaced by a dummy oit, the error cotributio to the total error from which is zero. The modified table is the comacted usig the algorithm i Sectio III-A. Whe a table etry is requested, we first determie whether the accessed oit is a outlier: if so, we fetch it from the outliers list; else, we fid it usig the comacted look-u table. With the outliers searated, the variatios i remaiig looku table become more uiform. Table I shows the list of

6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 6 tables at zero body bias ad zero temerature offset, ad the comressed CSM sesitivity arameter tables for the body bias coefficiets {a I,b I,a Q,b Q } ad the temerature offset coefficiets {c I,r I,c Q,r Q }. Fig. 5: The resece of outliers yields oor comactio of the looku tables whe the origial scheme from [22] is used. This results i icorrectly evaluated outut waveforms with kiks at some time oits. Our aroach however, with a mechaism for searatio of outliers, results i the correctly evaluated outut waveform with miimal errors. A. Usig the Macromodel i a Solver To solve the case of a gate drivig a itercoect, icludig cases that ivolve couled lies ad crosstalk, it is eough to cosider the situatio where a gate drives a load described by a RCπ-model as show i Figure 6. Stadard techiques such as the O Brie-Savario aroach [23] are used i our work to reduce a arbitrary itercoect load to a π-model at the drivig oit. We first obtai the waveform at the drivig oit ode V o, ad the we evaluate the waveform at ay sik ode i the RC etwork by solvig a liear system usig stadard model order reductio methods. searately tabulated outliers for a looku table for a Q. Further, Figure 4c shows the remaiig etries for a Q i the 2-D looku table idexed by V i,v o. As is clearly see, the removal of outliers make the variatio i the looku table more uiform, allowig for a high comactio usig the origial algorithm. TABLE I: The outlier table for a Q V i idex V o idex a Q This method of searatig the outliers removes the kiks reset i the V o t waveforms. As show i Figure 5, the smooth waveform obtaied from the solver usig our aroach is o loger characterized by kiks, as comared to the waveform which had kiks due to the errors caused by origial comactio scheme. The waveform usig our aroach further has egligible slew ad delay errors. A otetial alterative for dealig with such outliers is to decrease the size of V i,v o voltages stes at which I Z ad Q Z are characterized, makig the variatio of sesitivities more uiform. We observe that this requires us to icrease the value of by about 6-9 for differet tables, resultig i a large icrease i the storage sace required. For a small umber of outliers, this osed as a sigificat icrease i the memory requiremets for a library with differet cells. It also rohibitively icreases the comutatioal time of the comressio algorithm 4. Therefore, a itermediate aroach of savig outliers searately kees both the storage sace ad the comressio time tractable. IV. THE MACROMODEL SOLVER Usig the aroaches described so far, the cell library is characterized to determie the I ad Q characterizatio Fig. 6: A CSM for a gate, uder zero body bias ad zero temerature offset, drivig a π load. We aalyze the case of a gate outut drivig a π-load i the absece of body bias ad at zero temerature offset, as show i Figure 6. Fidig the outut voltage waveform ivolves solvig the equatio: I Z +I Z Q = I C1 +I C2 18 where I Z Q = dqz dt I C1 = C 1 dv o dt I C2 = C 2 dv C2 dt I Z = FV i,v o,,, Q Z = GV i,v o,,, Equatio 18 is a oliear differetial equatio i V o t, ad the iut voltage, V i t, is kow. This equatio ca be solved usig routie circuit simulatio methods. We aly the Backward Euler formula to Q,V o ad V C2 with a time ste h, goig from time to time +1 the suerscrit +1 is droed for otatioal simlicity to get: Q = Q +hi Q 19 C 1 V o = C 1 Vo +hi C1 2 C 2 V C2 = C 2 VC 2 +hi C2 21 Moreover, usig Ohm s Law, we have V C2 = V o RI C2. Substitutig V C2 from this i equatio 21, we have: I C2 = C 2V o V C 2 h+rc 2 22

7 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 7 We the obtai the values of I Q from equatio 19, of I C1 from equatio 2 ad of I C2 from equatio 22, ad substitute them i equatio 18 to obtai: I + Q Q h = C 1V o Vo + C 2V o VC 2 h h+rc 2 Solvig this for V o, we arrive at the followig exressios: V o = 1 [ hc2 VC A 2 +BC 1 Vo +hi +Q Q ] 23 where A = hc 1 +hc 2 +RC 1 C 2 24 B = h+rc 2 25 Obtaiig V o, we substitute I C2 from equatio 22 i equatio 21 to solve for V C2 : V C2 = 1 [ hvo +RC 2 V ] C B 2 26 Thus we have obtaied the exressios for both the ukow ort voltages i terms of kow quatities. However, such exressios are still imlicit, ad hece must be solved iteratively. B. Newto-Rahso Solver The aroach covetioally emloyed i CSM solvers is to solve the oliear equatio 23, through iterative Newto- Rahso liearizatio. This aroach is hereby termed as the Newto-Rahso Solver, ad referred as such i the rest of the sectios. I the k+1 th iteratio, we use the k th iteratio value, show by the additioal subscrit k, to obtai: AV o = BC 1 Vo +hc 2 VC 2 +hb I,k + I V o V o,k k +B Q,k + Q V o V o,k Q k V o = V o,k AV o,k hc 2 V C 2 BC 1 V o +hi,k +Q,k Q A Bh I / k + Q / k 27 This comutatio is carried out by refereces to the look-u tables for I ad Q, with the aroriate use of iterolatio as ecessary, ad the use of fiite differeces to comute derivatives. V. FORMULATION OF WAVEFORM SENSITIVITY MODEL The Newto-Rahso solver i Sectio IV-B forms the basis for a rocedure for comutig the waveform uder ay body bias ad temerature coditio usig covetioal CSM solvers. However, evaluatio of the delays ad slews of the gates uder umerous body bias ad temerature offset coditios etails multile simulatios of the etire outut voltage waveform at each combiatio of body bias ad temerature value. Alicatios that require timig aalysis at multile body biases ad at multile temerature values iclude [1] [3], [17], [19]. Ituitively, the reeated comutatio of full waveforms from scratch seems uecessarily excessive, for several reasos. First, the alicatio of body bias or a variatio i temerature corresods to a erturbatio to a base case, such as the zero body bias ad zero temerature offset case, ad it should be ossible to comute the waveform at ozero body bias ad temerature offset based o the zero body bias ad zero temerature offset case, with some cosideratio of body bias ad temerature sesitivities, much more chealy tha the above rocedure. Secod, as discussed ad show before i Sectio II, the effects of chages i body bias ad temerature o CSM ca be decouled. Thus it should be ossible to decoule ad ideedetly comute the effects of body bias ad temerature chages o the outut waveforms too. Third, i most cases, desigers are iterested ot i the etire waveform, but secific roerties of the gate outut, such as its delay ad outut trasitio time. I this sectio, we demostrate the efficiet comutatio of such metrics uder chagig body bias ad temerature without the eed for umerous table look-u oeratios. A. Waveform Sesitivity Models Cosider the case whe we have the cell maitaied at zero temerature offset T = C, but with a ozero alied body bias v b,v b. For various values of v b,v b, the solutio of the waveform uder the framework of equatio 27 etails multile accesses to the look-u tables for I ad Q. The etries that are accessed i these tables chage accordig to the alied body bias. However, sice body bias is a small erturbatio, i ractice, the accessed etries i each table at each ste of the algorithm are relatively close to each other, ad ca be viewed as erturbatios to a omial case. Therefore, we roose to cature the outut waveform at zero temerature offset for ozero body bias case as a erturbatio to the waveform with zero body bias ad zero temerature offset as follows: V o t = V Z o t+αv b,v b,t v b +βv b,v b,t v b 28 where V Z o t reresets the outut waveform, V o t, with zero body bias ad zero temerature offset, ad αv b,v b,t ad βv b,v b,t are time-varyig body bias erturbatio arameters that are recisely defied as: αv b,v b,t = t v b βv b,v b,t = t v b 29 Similarly, if we cosider the variatio i temerature of the cell, the cell beig maitaied at zero body bias, we ca formulate a liear model as above for caturig the outut waveform at ay temerature with a ozero temerature offset, T as erturbatio to the outut waveform at omial temerature with zero temerature offset T : V o t = V Z o t+σ T,t T 3 where Vo Z t is as as described above, ad σ T,t is timevaryig temerature erturbatio arameter that is recisely defied as: σ T,t = t 31 T

8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 8 The followig two results rovide a recise formula for αv b,v b,t, βv b,v b,t ad σ T,t. We first reset the results roved i the Aedix, ad the discuss how the comutatioal cost of evaluatig these quatities ca be sigificatly reduced. Theorem 1 The waveform sesitivity arameters from equatio 28, αv b,v b,t ad βv b,v b,t, are give by: αv b,v b,t = N α/d α,β 32 βv b,v b,t = N β /D α,β 33 [ N α = B α C 1 +ha I I Z +a Q Q Z a Q QZ, Q Z, a Q α v b Q Z, N β = B [ Q Z, D α,β = B +Q Z b Q ] α v b QZ, L Q v v VC b,v b +hc 2 2, b v b β C 1 +hb I I Z +b Q Q Z b Q QZ, b Q [ hi Z β v b QZ, v b L Q v b,v b Q Z, ] a Q β v b +hc 2 V C 2 v b, ai v b + b I v b +h IZ L I v b,v b ] aq v b + b Q v b + QZ v b L Q v b,v b +A where terms usig the suerscrit are uderstood to corresod to their values at the revious th time ste, ad the suerscrit Z refers to the case where v b = v b = V, ad T = C. Theorem 2 The waveform temerature sesitivity arameter from equatio 3,σ T,t, is give by: σ T,t = N σ/d σ 34 [ N σ = B σ C 1 +hc I +2r I TI Z +c Q +2r Q TQ Z c Q +2r Q TQZ, Q Z, c Q [ D σ = A B hi Z + hi Z r I +Q Z σ T Q Z, c I +Q Z r Q QZ, T S Q T rq ] σ T 2 +hc 2 V C 2 T, T +h IZ T S I T ] c Q T 2 + QZ T S Q T where the terms have the otatios as described above. Theorems 1 ad 2 eable the efficiet comutatio V o t at ay body bias value ad temerature offset usig a closed form exressio, deedet oly o the values ofv o at revious time stes ad the values i the waveform at zero body bias ad omial temerature. As a result, the waveform at arbitrary body bias ad temerature values ca be reroduced if the values of αt, βt ad σt are comuted. B. Simlified Waveform Sesitivity Models Further simlificatios are ossible with both the models discussed above. Cosider first the body bias model. O ivestigatig deedecy of the outut waveform o v b,v b ad o αv b,v b,t,βv b,v b,t, we observe that: 1 The variatio i V o t over v b,v b is early liear at each time oit of the waveform. Emirically, this ca be see i Figure 7, which shows tyical cases for the variatio of V o t over v b,v b for various time oits of simulatio. This behavior is observed for multile test cases, ad idicates that αv b,v b,t,βv b,v b,t are actually ideedet of the alied body bias, ad are oly deedet o t. 2 Figure 8 shows the variatios i αv b,v b,t ad βv b,v b,t with v b,v b. The magitude of these variatios were observed to be a maximum of.1 for all test cases. Sice these arameters are further multilied by v b or v b [.3V,.3V] i equatio 28, their effects o V o t are exected to be egligible. This is further validated i Sectio VI. V o V o variatio with body bias at selected time oits v.2.2 v.2 b b Fig. 7: Tyical surface lots for V o showig the liear ature of V o variatios with v b,v b, with each surface corresodig to a radomly selected time oit durig the simulatio. Variatio of α,β with body bias for fallig iut Times a α β.1.1 V o Variatio of α,β with body bias for arbitrary iut.2 α β Times Fig. 8: Simulatios showig the variatio of αt ad βt at a rage of body biases from the miimum to the maximum, icludig zero. Two such test cases are show i Figure a ad b. This leads to the followig aroximatio, which rovides accurate waveforms with very low errors, as demostrated i Sectio VI: αv b,v b,t α t = αv b =,v b =,t βv b,v b,t β t = βv b =,v b =,t 35 b

9 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 9 The simlified body bias waveform sesitivity model is thus give as follows: V o t = V Z o t+α t v b +β t v b 36 Note that this dramatically reduces the storage requiremets for the looku table. At each time oit, this method requires just two additioal arameters, α ad β. I order to develo a simlified model with chages i temerature as was doe i the body bias case, we ivestigated the ossibility of beig able to geerate a simlified temerature waveform sesitivity model too. We however fid that ulike the body bias case, the followig aroximatio: σ T,t σ t = σ T =,t 37 does ot work very well with the temerature waveform sesitivity model. The iaccuracies i the resultat delays ad slews, as comared to HSPICE, reach uto 2%. This ca be attributed to the oliear effects of temerature o the circuit resoses, which lead to reduced accuracy whe a liear model is used. Therefore, we aly a more accurate iecewise liear model to address the above iaccuracies. We observe that icreasig the value of T icreases the iaccuracies i waveform evaluatio, ad that the magitude of such errors are ot large for smaller values of T. Thus, istead of the very simlistic liear aroximatio as i equatio 37, we roose a more accurate ad less aroximate liear simlified temerature sesitivity model as follows: σ T,t σ T,t TR = σ T = T 1,t, T MIN T < T MIN + 3 TR 2 TR = σ T = T 2,t, T MIN + T < T MIN TR = σ T = T 3,t, T MIN + T T MAX 38 3 where, T MIN = Miimum value of temerature offset i the rage of T T MAX = Maximum value of temerature offset i the rage of T T R = T MAX T MIN TR T 1 = T MIN TR T 2 = T MIN TR T 3 = T MIN + 6 As stated i Sectio II, the values of T MAX ad T MIN are take to be -5 C ad 1 C, resectively. The above formulatio i equatio 38 states that this temerature rage is divided ito three rages of early equal size. The waveforms of σ T,t, with T chose as the cetral value i each of these itervals, are the evaluated ad saved. Although i ricile, a waveform corresodig to each of the 13 T values ca be saved givig us the lowest error i the model, a desiger would like to save ad work with miimal umber of waveforms, without losig much i accuracy. We have foud through simulatios that a choice of 3 differet waveform described through equatio 38 serves this urose. As we will show i Sectio VI, such a choice still reserves the high accuracy. The gai i storage ad waveform evaluatio seedu o the other had, is sigificat. I other words, istead of comutig ad savig σ T, t at just oe temerature oit as i the liear case i equatio 37, we ow save the values of σ T, t at three distict values of temerature to rovide a better aroximatio that catures thermal oliearities. The simlified temerature waveform sesitivity model is thus give as follows: V o t = V Z o t+σ T,t T 39 where σ T,t is give by equatio 38. As will be show i Sectio VI, the above model yields accurate waveforms for all temerature oits. C. Comlete Waveform Sesitivity Model We ow roose the comlete body bias ad temerature waveform sesitivity model as follows: V o t = V Z o t +α t v b +β t v b +σ T,t T 4 This model is a liear combiatio of the simlified waveform sesitivity models as give i equatios 36 ad 39. Note that such a liear combiatio is ossible sice the effects of body bias ad temerature are ideedet of each other, as has bee discussed i Sectio II. Equatio 4 redicts that the effects of erturbatios iside a cell caused due to chages i body bias ad temerature, ca be catured through a simle liear model of the outut voltage i terms of the chages i the body bias ad temerature. To summarize, evaluatig the outut at b body bias oits each for v b ad v b, ad at τ temerature offset oits, usig a eumerative aroach would solve for b 2 τ waveforms, ivolvig the extesive use of looku tables. I cotrast, our aroach reduces the solutio to fidig just six waveforms: oe for the zero body bias, Vo Z t, ad oe each for α t ad β t, ad three for σ T,t. The et result is a large savigs i the storage ad comutatio. Thus, the stes ivolved i comutig the waveform at ay v b,v b ad T are summarized below: 1 Aly equatio 27 to geerate the waveform Vo Z t at zero-body bias ad zero temerature offset. 2 Comute ad save α t, β t at every timeste from equatios 32, 33, ad Comute ad save σ T,t at every timeste from equatios 34 ad Use the comuted α t, β t ad σ T,t i equatio 4 to directly geerate the waveform for ay value of v b,v b ad T. VI. EXPERIMENTAL RESULTS Our results are based o stadard library cells usig the 45m PTM [24], ad our accuracy is measured through comarisos with the results of HSPICE [25] simulatios.

10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 1 A. Reductio i CSM Sesitivity Table Size We aly our table reductio algorithm for the sesitivity arameters, {a I, b I, a Q, b Q } ad {c I, r I, c Q, r Q } for a set of stadard cells characterized usig 45m PTM [24], ad demostrate our results i Table II for a tyical table, for a I. Colums 2 through 4 show the umber of etries i the reduced table usig the origial comressio aroach Sectio III-A, ad Colums 5 through 7 list the size of the reduced tables usig our aroach Sectio III-B. These comarisos are show for various bouds 2%, 5%, 1% o the allowable error, ad i each case, the otimal table size corresods to the smallest m m table, idexed by V i,v o, that meets the error boud. I each case, m = 3 for the origial table size, i.e., it has 9 etries. As is see from the table, i each case, our aroach yields much smaller tables tha the rior aroach. TABLE II: Results for sesitivity arameter table reductio for tables with origial size = 9 Cell Reduced Table Size with Error Bouds Ru Tye Origial aroach Our aroach Time 2% 5% 1% 2% 5% 1% INV s NAND s NOR s NAND s NOR s AOI s AOI s The last colum of Table II shows the rutime of the algorithm for achievig reduced table sizes for the most comutatioally-itesive solutio, where the 2% error boud must be satisfied. The rutimes are measured o a 3GHz Itel Core2Duo CPU, ad corresod to the average for the {a I,a Q,b I,b Q } ad {c I,c Q,r I,r Q } sesitivity tables, ad are very reasoable, esecially cosiderig that this characterizatio comutatio must be erformed oly oce for a give library i a give techology. It is easy to exlai why the origial algorithm of Sectio III-A does ot lead to sufficiet reductio i the table size. This ca rimarily be related to outliers: igorig these oits causes substatial errors at these oits whe iterolatio is used to redict the values of missig etries. O the other had, if these are icluded, the large jums at these oits ca result i iterolatio errors at earby oits that do ot corresod to outliers. These errors ca oly be dimiished by usig reduced tables of larger sizes. B. Seedu Due to Waveform Sesitivity Models We ow reset the seedu obtaied usig our various simlified body bias, temerature ad the comlete waveform sesitivity WS models, as roosed i Sectios V-B, ad V-C, resectively. We evaluate the seedu of our models over HSPICE ad over the Newto-Rahso solver see Sectio IV-B that would be used i a simle extesio of existig CSMs. To calculate the above seedu, we erform our tests with each circuit examle uder multile combiatios of the followig arameters: multile rise/fall waveforms 1s 1s iut rams, i stes of 5-1s, various RC itercoects from the ChiA-1K, ChiB-1K ad the ChiB-5K family [26] as load bechmarks reduced to π-models, multile body bias oits 169 oits with v b,v b [-.3V,.3V], i stes of.5v for each arameter, ad multile temerature oits 13 oits with T [-5 C, 1 C], i stes of 12.5 C. First, we reset the seedus with simlified body bias waveform sesitivity model ad those of simlified temerature waveform sesitivity model ideedetly. The we reset the seedus of the comlete waveform sesitivity model. I each case, we calculate the rutimes usig HSPICE, Newto- Rahso solver ad our simlified waveform sesitivity models, ad average these rutimes over all the test cases to arrive at fial seedu results. For the test cases, we erform trasiet simulatios ad reort the seedus of our algorithm over HSPICE ad over the Newto-Rahso solver. Exectedly, the seedu over HSPICE is large, ad is foud to be about five orders of magitude. More iterestigly, our comlete waveform sesitivity model achieves a average seedu of 91.81, ad a maximum seedu of 99.55, over the Newto- Rahso solver. 1 Body Bias Waveform Sesitivity Model: We evaluate the seedu achieved usig the stadaloe body bias model as reseted i Sectio V-B. We erform evaluatios at 169 body bias oits withi the rage v b,v b [-.3V,.3V]. All evaluatios are carried at the zero temerature offset of T = C. Table III lists the seedus that are obtaied by our waveform sesitivity model over HSPICE ad over the Newto-Rahso Solver, for stadard library cells. As ca be see from the table, the body bias waveform sesitivity model achieves a average seedu of aroud five orders of magitude over HSPICE ad a average seedu of 67.9 over the Newto-Rahso Solver. TABLE III: Seedus obtaied by the Comlete Waveform Sesitivity WS Model over HSPICE ad Newto-Rahso NR solver Cell WS Model Seedus Body Bias Temerature Combied Over Over NR Over Over NR Over Over NR HSPICE Solver HSPICE Solver HSPICE Solver INV 8.9e e e NAND2 9.6e e e NOR2 9.2e e e NAND3 9.6e e e NOR3 8.9e e e AOI21 1.8e e e AOI22 1.e e e Temerature Waveform Sesitivity Model: Next, we evaluate the seedu achieved usig the stadaloe simlified temerature waveform sesitivity model as reseted i Sectio V-B. We erform evaluatios at 13 temerature oits withi the rage T [-5 C, 1 C] with zero body biasig. Table III resets the average seedu attaied over HSPICE ad the Newto-Rahso solver. Comared to body bias case, these seedus are lower sice we are evaluatig at a much lesser umber of temerature oits 13 as comared to 169 i the body bias case.

11 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 11 Volts Volts v b = 1. v b =. v b = 1.3 v b =.3 V i V sik HSPICE V sik WS MODEL Time s 1 v b =.8 v b =.3 a v b = 1.3 v b =.1 V i V sik HSPICE V sik WS MODEL Time s b Fig. 9: The result of our simlified body bias waveform sesitivity WS method as comared with HSPICE, for several body bias values: a outut waveform from a Iverter, loaded with a 2l bechmark RC itercoect, evaluated at sik ode 52, ad b outut waveform from a NAND2, loaded with a 45l bechmark RC itercoect, evaluated at sik ode Comlete Waveform Sesitivity Model: We ow reset the seedu obtaied with our comlete body bias ad temerature waveform sesitivity model as reseted i Sectio V-C. I this case, we erform evaluatios at all combiatios of the 169 body bias ad 13 temerature oits withi the rage v b,v b [-.3V,.3V], ad T [-5 C, 1 C] thus a total of evaluatios. Table III resets the average seedu attaied by our comlete model over HSPICE ad the Newto-Rahso solver. Note that with the comlete model, we are able to achieve a order of five magitudes seedu over HSPICE. Our comlete model is much faster as comared to the Newto-Rahso solver, over which we are able to achieve a average seedu of 91.81, cosiderig all temerature ad body bias oits. C. Accuracy of the Waveform Sesitivity Models I this subsectio, we reset the accuracy achieved by our body bias ad temerature models i both waveform geeratio ad comutatio of slews ad delays over multile combiatios of body bias ad temerature values. Through the accuracy of these waveforms ad low errors i slews ad delays, we also show that our assumtios of makig waveform sesitivity models simlified are justified. We reset accurate waveform geeratio both at the outut ode of the cell as well as the sik odes of the RC itercoect loads, which are coected to the outut ode of the cell. Volts Volts v b = 1. v b =. V i V o HSPICE V o WS MODEL v b = 1.3 v b = Times v b =.8 v b =.3 v b = 1.2 v b =.2 a V i V o HSPICE V o WS MODEL Times b Fig. 1: Similar results of outut waveform at the outut ode of a gate a for a NAND2, modelig a iut glitch, ad b for a NAND3, with a omootoe iut. 1 Body Bias Waveform Sesitivity Model: The temerature offset i this art of evaluatio is set to zero. Figures 9 ad 1 comare reresetative waveforms as geerated through HSPICE [25] ad the simlified body bias waveform sesitivity model, whe the iut waveform takes ay arbitrary shae either due to glitches, oise or crosstalk. We evaluate accuracies both at the outut ode of the cell, ad the sik odes of the itercoects which load the cell outut ode. Figure 9 shows the tyical resose of the cell at the sik odes of the RC tree itercoect loads. The waveform is first obtaied at the outut ode of the cell, ad the evaluated at sik ode usig Padé-aroximatio of the RC itercoect circuit, ad model order reductio techiques [23]. Figure 1 shows the outut waveforms at the outut ode of the cells, with arbitrary iuts. The waveforms i some cases are coicidet to the aked eye, as our algorithm yields high accuracy. This also validates the idea that α,β ca be assumed to be ideedet of v b,v b, as roosed i Sectio V-B. Note that the iitial rigig error i these waveforms is due to the use of Padé-aroximatio, ad ot due to the waveform sesitivity model. 2 Temerature Waveform Sesitivity Model: As with the body bias waveform sesitivity model, the simlified temerature sesitivity model as described i Sectio V-B yields accurate waveforms for ay temerature offset value. Note that the body bias is ket at zero i all such evaluatios. Figure 11 shows a set of waveforms obtaied from a NOR3 cell, loaded with 33l RC itercoect etwork. The waveform is first obtaied at the outut ode of the NOR3 cell, ad the waveform show is the evaluated at sik ode 55. As show i

12 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 12 a a b Fig. 11: The result of our simlified temerature waveform sesitivity WS method as comared with HSPICE, for various temerature values. Show above are outut waveforms from a NOR3, loaded with 33l bechmark RC itercoect, evaluated at sik ode 55: a for a fallig ste iut, ad b for a slower risig iut. b Fig. 12: The result of our comlete waveform sesitivity WS model as comared with HSPICE, for various temerature ad body bias values. Show above are waveforms at the outut ode of a Iverter with a 45l as the itercoect load ad a iut glitch due to crosstalk, ad b 25m as the itercoect load ad a arbitrary iut. the figure, the temerature waveform sesitivity model yields very accurate waveforms. This also validates the simlificatio of σ T,t values, as roosed i Sectio V-B. 3 Comlete Waveform Sesitivity Model: For resetig the results i this sectio, we geerate waveforms for multile combiatios of body bias or temerature offset values ad comare the result with the corresodig waveforms obtaied from HSPICE. We fid that the comlete model as reseted i Sectio V-C, geerates very accurate waveforms. As before, we evaluate accuracies both at the outut ode of the cell, ad the sik odes of the itercoects which load the cell outut ode. Figure 12 shows the accuracy obtaied at the outut ode of a iverter loaded with 45l RC itercoect, with iuts havig glitches ad arbitrary shaes. Figure 13 shows the waveform evaluated at sik ode 52 of 2l RC load itercoect for NAND2 ad NOR2 cells. Our results show that a liear model for V o t i both body bias ad temerature with simlificatios as i equatios 35 ad 38, suffices for geeratio of waveforms at ay combiatio of body bias ad temerature, with sufficietly desired accuracy. 4 Slew ad Delay Errors: We ow reset some more descritive tables for the errors i delays ad slews that are icurred i formulatio of the comlete waveform sesitivity model. For this tabulatio, we work with the test cases that were metioed at the begiig of Sectio VI-B, ad save the delay ad slew values as obtaied from our comlete waveform a Fig. 13: Similar outut waveforms from cells loaded with 2l bechmark RC itercoect, evaluated at farthest sik ode 52: a the outut from a NAND2 for a risig iut, ad b the outut from a NOR2 for a fallig iut. sesitivity model ad from HSPICE. We the obtai the relative ercetage error betwee delays ad slews corresodig to the comlete simlified waveform sesitivity model ad of HSPICE. All such errors are tabulated. Table IV shows the mea ad stadard deviatio of these relative errors for a NAND2 cell, over all v b,v b, T oits, reseted for each combiatio of iuts slews ad outut load itercoects. It is see that both the mea ad stadard deviatios are small for all test cases. A more detailed view of these rise ad fall delay/slew errors is reseted i Table V, for a articular test case: with a NAND2 cell loaded with 2l as the RC itercoect, waveforms beig evaluated at sik ode 52. This table shows b

13 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 13 TABLE IV: Mea ad stadard deviatio St. Dev. of the ercetage errors over all v b,v b, T oits, icurred by our comlete waveform sesitivity model i the outut rise delay ad slew values for NAND2 cell, as comared to HSPICE for differet iut slews ad outut RC itercoect loads RC Itercoect Loads Iut 25m 33l 45l Slews Percet Delay Error Percet Slew Error Percet Delay Error Percet Slew Error Percet Delay Error Percet Slew Error Mea St. Dev. Mea St. Dev. Mea St. Dev. Mea St. Dev. Mea St. Dev. Mea St. Dev. 5s s s s s TABLE V: Percet delay ad slew errors for a NAND2 cell at various temerature offsets, over all v b,v b oits T Percet Delay Errors Percet Slew Errors C Max. Mi. Mea Max. Mi. Mea the distributio of the delay/slew errors over all v b, v b oits, but at differet T values. Colum 1 of the table lists the temerature offsets from the omial temerature of 25 C at which the waveforms are evaluated. Colums 2 to 4 reset, for the value of T listed i colum 1, the maximum, the miimum ad the mea of the ercetage delay errors obtaied over all v b,v b oits. Similarly, colums 5 to 7 reset the maximum, the miimum ad the mea ercetage slew errors obtaied over all v b,v b oits at that temerature offset. Clearly, at all temerature offsets, both the mea delay ad slew errors over all v b,v b oits are cotaied withi 4%. We thus observe from Tables IV ad V that oly a small error is icurred i both delays ad slews over all combiatios of v b,v b, ad T oits, validatig the use of our waveform sesitivity model i redictig the delay ad slews over the etire rage of body bias ad temerature. Very similar observatios were made for other stadard cells i the library. VII. CONCLUSION A simle extesio of existig CSMs to icororate the effects of body bias ad temerature i the CSM framework results i excessive icrease i library memory ad solver rutime. We reset a ovel aroach to icororate body bias ad temerature effects ito curret source models. We develo sesitivity model for caturig variatios i CSM comoets with body bias ad temerature, with comactio of the resultig tables of these model arameters. We icororate this sesitivity model ito the maistream CSM solver framework, ad develo a ew model for caturig waveform sesitivity with body bias ad temerature, which allows us to comute waveforms at multile combiatios of body bias ad temerature oits with massive savigs i comutatio. The results demostrate the effectiveess of our comactio scheme ad the waveform sesitivity model i achievig HSPICE level accuracy with high seedus both over HSPICE ad covetioal CSM solvers. REFERENCES [1] T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sao, M. Norishima, M. Murota, M. Kako, M. Kiugawa, M. Kakumu, ad T. Sakurai, A.9-V, 15 MHz, 1-mW, 4 mm 2, 2-D discrete cosie trasform core rocessor with variable threshold-voltage VT scheme, i Proceedigs of the IEEE Iteratioal Solid-State Circuits Coferece, , [2] J. W. Tschaz, J. Kao, S. G. Naredra, R. Nair, D. Atoiadis, A. Chadrakasa, ad V. De, Adative body bias for reducig imacts of die-todie ad withi-die arameter variatios o microrocessor frequecy ad leakage, IEEE Joural of Solid-State Circuits, vol. 37, , November 22. [3] J. Tschaz, N. Kim, S. Dighe, J. Howard, G. Ruhl, S. Vaga, S. Naredra, Y. Hoskote, H. Wilso, C. Lam, M. Shuma, C. Tokuaga, D. Somasekhar, S. Tag, D. Fia, T. Karik, N. Borkar, N. Kurd, ad V. De, Adative frequecy ad biasig techiques for tolerace to dyamic temerature-voltage variatios ad agig, i Proceedigs of the IEEE Iteratioal Solid-State Circuits Coferece, , 27. [4] S. S. Saatekar, Timig. Bosto, MA: Sriger, 24. [5] F. Dartu, N. Meezes, ad L. Pileggi, Performace comutatio for recharacterized CMOS gates with RC loads, IEEE Trasactios o Comuter Aided Desig of Itegrated Circuits ad Systems, vol. 15, , May [6] J. F. Croix ad D. F. Wog, Blade ad Razor: Cell ad itercoect delay aalysis usig curret-based models, i Proceedigs of the Desig Automatio Coferece, , 23. [7] I. Keller, K. Tseg, ad N. Verghese, A robust cell-level crosstalk delay chage aalysis, i Proceedigs of the Iteratioal Coferece o Comuter-Aided Desig, , 24. [8] P. Li ad E. Acar, A waveform ideedet gate model for accurate timig aalysis, i Proceedigs of the Iteratioal Coferece o Comuter Desig, , 25. [9] C. Ami, C. Kashya, N. Meezes, K. Killack, ad E. Chirout, A multi-ort curret source model for multile-iut switchig effects i CMOS library cells, i Proceedigs of the Desig Automatio Coferece, , 26. [1] C. Kashya, C. Ami, N. Meezes, ad E. Chirout, A oliear cell macromodel for digital alicatios, i Proceedigs of the Iteratioal Coferece o Comuter-Aided Desig, , 27. [11] N. Meezes, C. Kashya, ad C. Ami, A true electrical cell model for timig, oise, ad ower grid verificatio, i Proceedigs of the Desig Automatio Coferece, , 28. [12] B. Amelifard, S. Hatami, H. Fatemi, ad M. Pedram, A curret source model for CMOS logic cells cosiderig multile iut switchig ad stack effect, i Proceedigs of the Coferece o Desig, Automatio ad Test i Euroe, , 28. [13] A. Goel ad S. Vrudhula, Curret source based stadard cell model for accurate sigal itegrity ad timig aalysis, i Proceedigs of the Coferece o Desig, Automatio ad Test i Euroe, , 28.

14 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION VLSI SYSTEMS 14 [14] S. Raja, F. Varadi, M. Becer, ad J. Geada, Trasistor level gate modelig for accurate ad fast timig, oise, ad ower aalysis, i Proceedigs of the Desig Automatio Coferece, , 28. [15] V. Gerousis, Desig ad modelig challeges for 9 m ad 5 m, i Proceedigs of the IEEE Custom Itegrated Circuits Coferece, , 23. [16] G. Oo, M. Miyazaki, M. Taaka, N. Ohkubo, ad T. Kuwahara, Temerature refereced suly voltage ad forward-body-bias cotrol TSFC architecture for miimum ower cosumtio, i Proceedigs of the Euroea Solid State Circuits Coferece, , 24. [17] S. V. Kumar, C. H. Kim, ad S. S. Saatekar, Body bias voltage comutatios for rocess ad temerature comesatio, IEEE Trasactios o Very Large Scale Itegratio Systems, vol. 16, , March 28. [18] Y. Zha, S. V. Kumar, ad S. S. Saatekar, Thermally aware desig, Foudatios ad Treds i Electroic Desig Automatio, vol. 2, o. 3, , 28. [19] K. Bowma, J. Tschaz, C. Wilkerso, S. Lu, T. Karik, V. De, ad S. Borkar, Circuit techiques for dyamic variatio tolerace, i Proceedigs of the Desig Automatio Coferece,. 4 7, 29. [2] J. Tschaz, S. Naredra, A. Keshavarzi, ad V. De, Adative circuit techiques to miimize variatio imacts o microrocessor erformace ad ower, i Proceedigs of the IEEE Iteratioal Symosium o Circuits ad Systems,. 9 12, 25. [21] Y. Taur ad T. H. Nig, Fudametals of moder VLSI devices. Cambridge, UK: Cambridge Uiversity Press, Secod Editio, 29. [22] J. F. Croix ad D. F. Wog, A fast ad accurate techique to otimize characterizatio tables for logic sythesis, i Proceedigs of the Desig Automatio Coferece, , [23] P. R. O Brie ad T. L. Savario, Modelig the drivig oit characteristic of resistive itercoect for accurate delay estimatio, i Proceedigs of the Iteratioal Coferece o Comuter-Aided Desig, , [24] Predictive Techology Model. htt:// tm. [25] htt:// [26] Z. Li, C. N. Sze, C. J. Alert, J. Hu, ad W. Shi, Makig fast buffer isertio eve faster via aroximatio techiques, i Proceedigs of the Asia ad South Pacific Desig Automatio Coferece, , 25. [27] G. A. Baker ad P. G. Morris, Padé Aroximats. Cambridge, MA: Cambridge Uiversity Press, Secod Editio, that {a I,a Q,b I,b Q} are ideedet of body bias, beig fuctios of V i,v o oly, but aear as fuctios of v b,v b sice V o dyamically chages with body bias durig simulatio. Proof of Theorem 2 The derivatio of σ follows alog the same lies as for α ad β. At each time ste, combiig the oliear equatio 23 with 31, ad A,B give by 24, 25, we ca write σt as: σt = BC1 A T + hc2 VC 2 A T + B A h I T + Q T Q T 42 Writig I,Q as secod order fuctios of T from 1, 11, we get σt = BC1 A hi Z Q Z Q Z, [ T + hc2 VC 2 A T + B h IZ A T SI T+ Q Z T SQ T QZ, V o c I +2r I T + ci ri T + T c Q +2r Q T + cq T c Q +2rQ T + c Q T S Q T+ T T2 + ] rq T + T T2 T T + r Q T T2 where S I ad S Q are defied as i equatios 12 ad 13, resectively, ad SQ corresods to the evaluatio of S Q at time ste. Further, V C2 / T ca be calculated usig equatio 26. Sice = σ, ad at time ste, T σ =, collectig all T terms multilied by σ o left had side, the result of equatio 34 follows immediately. Note that {c I,c Q,r I,r Q} are agai ideedet of temerature, beig fuctios of V i,v o oly. APPENDIX Proof of Theorem 1 At each time ste, combiig the oliear equatio 23 with 29, ad A,B give by 24, 25, we ca write αt as: αt = BC1 + hc2 VC 2 + B h I + Q Q A v b A v b A v b v b v b 41 Writig I,Q as liear fuctios of v b,v b from 4, 5, we get [ αt = BC1 + hc2 VC 2 + B h IZ L Iv b,v b + A v b A v b A v b Q Z L Qv b,v b QZ, v b V hi Z Q Z Q Z, V o L Qv b,v b + o v b a I + ai v b + bi v b + v b v b a Q + aq v b + bq v b v b v b ] a Q + a Q v b + b Q v v b b v b where L I ad L Q are defied as i equatios 6 ad 7, resectively, ad L Q corresods to the evaluatio of L Q at time ste. Further, V C2 / v b ca be calculated usig equatio 26. V Recogizig that o v b = α, ad at time ste, α = v b, collectig all terms multilied byα, the result of equatio 32 follows immediately. The derivatio of equatio 33 is aalogous. Note Saket Guta Saket Guta received the B.Tech. degree i electroics ad comuter egieerig from Idia Istitute of Techology, Roorkee, Idia, i 28, ad the M.S. degree i electrical egieerig from the Uiversity of Miesota, Mieaolis, i 211. He is curretly ursuig his PhD degree i electrical egieerig from the Uiversity of Miesota, Mieaolis. His research iterests iclude develomet ad imlemetatios of CAD-related timig tools, ad high-erformace circuits ad architectures that are varitios ad agig resiliet. His other iterests iclude umerical modelig ad simulatio, ad arallel rogrammig o multicores ad GPUs. Sachi S. Saatekar Sachi S. Saatekar F3 received the Ph.D.degree from the Uiversity of Illiois at Urbaa-Chamaig i He is curretly with the Uiversity of Miesota, where he holds the Distiguished McKight Uiversity Professorshi ad the Robert ad Marjorie Hele Chair i Electrical ad Comuter Egieerig. His research iterests are i the aalysis ad otimizatio of aometer-scale VLSI circuits. He has held ositios o the editorial boards of various jourals ad is curretly the Editor-i-Chief of the Trasactios o CAD. He has served as Techical Program Chair ad Geeral Chair for the Desig Automatio Coferece, the Iteratioal Symosium o Physical Desig, ad the Tau worksho. He is a reciiet of the NSF Career Award, six coferece Best Paer Awards, ad the SRC Techical Excellece Award.