Analysis and Software Implementation of a Robust Synchronizing PLL Circuit

Transcription

1 Analysis and Software Implementation of a Robust Synchronizing PLL Circuit Luís Guilherme B. ROLIM, Member, IEEE, Diogo R. COSTA, Jr., and Maurício AREDES, Member, IEEE Federal University of Rio de Janeiro (UFRJ), Electrical Engineering (COPPE and POLI) P.O.Box 6854, Rio de Janeiro Brazil [rolim diogo aredes]@coe.ufrj.br Abstract This paper presents the analysis and software implementation of a robust synchronizing circuit PLL circuit designed for using in the controller of active power line conditioners. The basic problem consists in designing a PLL circuit that can track accurately and continuously the positive-sequence component at the fundamental frequency and its phase angle, even when the system voltage of the bus, to which the active power line conditioner is connected, is distorted and/or unbalanced. The fundaments of the PLL circuit are discussed. It is shown that the PLL can fail in tracking the system voltage during the startup, under some adverse conditions. Moreover, it is shown that oscillations caused by the presence of subharmonics can be very critical and can pull the stable point of operation synchronized to that sub-harmonic frequency. Oscillations at the reference input are also discussed, and the solution of this problem is presented. Finally, experimental and simulation results are shown and compared. Index Terms Phase locked loops (PLL), Phase synchronization, Power systems.

2 I. INTRODUCTION Most applications of static converters connected to the utility power grid require synchronization between the grid voltage and the voltage or current synthesized by the converter. As examples of such applications can be pointed out: converters that inject energy coming from alternative supplies into the grid; Active Power Line Conditioners, FACTS and Custom Power devices (e.g. DVR, STATCOM, active filters []-[3]). In many cases, the reference signal obtained from the grid voltage is contaminated by harmonics, which may have been produced by the power converter itself or generated elsewhere. Additionally, the voltages in a three-phase system may contain unbalances from negativeand/or zero-sequence components, which could cause improper synchronization between converter and grid. The most widely accepted solution to provide synchronization between time-varying signals is the use of a phase-locked-loop (PLL) system [4] that can be described by the basic structure shown in block diagram form in Fig.. This simplified PLL structure comprises a phase detector (PD), a loop filter (LF) and a controlled oscillator (VCO), each of which can be implemented in several different forms. If the signal to be tracked (reference input) is an analog signal, then the most suitable type of PD to be used is the product-type one. The use of a product-type PD plus a linear LF causes the PLL to behave linearly for small variations on input, reference input u (t) phase detector (PD) phase error u d (t) loop filter (LF) VCO output u 2 (t) controlled oscillator (VCO) VCO input u f (t) Fig. Block diagram of basic PLL structure

3 yielding a linear PLL. II. FUNDAMENTALS OF THE THREE-PHASE PLL CIRCUIT In the case of three-phase input signals, traditional (single input) PLL system analysis [4] can still be applied if small modifications are introduced in the simplified structure of Fig.. In view of that, in this work, the reference input is represented by a space vector, as well as the VCO output: ( w t+φ ) j u ( t) = Ue and ( w t+φ ) j 2 2 u 2 ( t) = U 2e () In stationary (αβ) reference frame, both signals can be written in the form u(t) = u α + ju β, where the α and β components are u α (t)=ucos(ωt+φ) and u β (t)=usin(ωt+φ). Three-phase input signals can be easily converted to this form through the Clarke Transformation. Alternatively, these signals can be represented in a synchronously rotating reference frame (through the Park Transformation) as shown in [5], with similar results. The angular frequency ω 2 of the VCO output signal is related to its input u f (t) by: where ω is called the center frequency. ω 2 = ω + u f (t), (2) The phase detector s operation is based on the product of both space vectors u (t) and u 2 (t). For this reason it is often called a vector-product phase detector (VP-PD). Its output can be obtained from the operation: u d (t) = u (t). u 2 (t)* = U U 2 e j(ω-ω2)t e j(φ-φ2), (3) where the asterisk denotes the complex conjugate. Alternatively, the phase error signal can be expressed in rectangular form as u d (t) = (u α u 2α + u β u 2β ) + j(u β u 2α - u α u 2β ). (4)

4 It is evident from (4) that the real and imaginary components of u d (t) have, respectively, the same form as the p and q power components from Akagi s instantaneous power theory [7],[8]. Hereafter, two different approaches can be adopted: if the real part of u d (t) is used as feedback error signal, then we have the so-called p-type PLL system, or p-pll for short. Using the imaginary part of u d (t) yields the so-called q-pll [9]. The latter approach will be used in the analysis presented next, but the results are applicable to p-pll systems as well. Now, considering that ω = ω 2 = ω (i.e. the PLL is nearly locked at the center frequency), then the phase error signal given by (3) can be further simplified to u d (t) = Im{U U 2 e j(φ-φ2) }, which yields: u d (t) = U U 2.sin(φ - φ 2 ), (5) For small phase deviations, this relationship can be approximated linearly by: u d (t) K d.φ e (t), (6) where K d = U U 2 and φ e (t) = φ (t) φ 2 (t). If the amplitudes U and U 2 are both normalized to unity, then (6) further simplifies to u d (t) φ e (t). As a result, the linearized behavior of the PLL can be described by the simplified block diagram shown in Fig. 2. In the block diagram shown in Fig. 2, the center frequency appears as a term added to the output of the PI loop filter. This produces the same effect as a non-zero initial condition at the integrator s output. For a proportional plus integral (PI-type) loop filter, as the one shown in Fig. 2, the linearized loop transfer function between φ (t) and φ 2 (t) is given by:

5 φ (t) φ 2 (t) K s ω s φ e (t) i + KP + u f φ 2 (t) - + loop filter VCO H Φ ( s) Fig. 2 Small-signal block diagram. K s + K 2 P i ( s) = =. 2 (7) Φ( s) s + K Ps + K i H(s) can be rewritten in the form: H ( s) = s 2ξω s + ω 2 n n 2 n + 2ξω s + ω 2 n (8) where ω n = K i K P and ξ =. 2 K i Well-designed PLL systems should meet the following design criteria: ξ.7 for optimum transient response (ITAE sense); narrow bandwith (low ω n ) for improved noise rejection, in order to produce a purely sinusoidal output signal even in the presence of input harmonics. The PLL lock range is defined as the maximum initial frequency deviation between reference f(hz) 8 7 f(hz) Fig. 3 results for sub-harmonic disturbances at Hz: 7% in magnitude and % in magnitude

6 input and VCO output, which will still cause the PLL to get locked in a single beat. It can be shown to be approximately equal to the natural frequency ω n : ω L ω n. (9) Thus, a narrow-bandwith PLL may fail to lock at some desired frequency during the start-up transient, if following conditions are met: the input signal contains harmonic components; the initial PI output is more distant from the desired frequency than the lock range; the initial PI output (or the center frequency) is close to some harmonic. It is however very difficult to predict the behavior of the PLL under the above conditions, because it depends on the relative amplitude of the harmonic components. Sub-harmonic oscillations at the reference input can cause the PLL to lock at the lower sub-harmonic frequency, even if the relative magnitude is very low. This fact is illustrated by the simulation results presented in Fig. 3a and Fig. 3b. For both simulations, the frequency of interest is 6Hz (with normalized amplitude of p.u.) and a disturbance at Hz has been added. The initial condition at the PI loop filter output is zero, what means that the VCO starts from zero frequency or DC conditions. If the disturbance is slightly increased beyond 7% of the main component, the PLL fails to lock at the desired center frequency of 6Hz. Fig. 3a shows a critical situation where 7% of disturbance at Hz is introduced and the PLL still locks at the center frequency (6Hz). However, it locks at Hz instead, as shown in Fig. 3b, if the disturbance is increased to % at Hz. As the frequency of interest for grid-connected applications is essentially constant (5Hz or 6Hz), an obvious solution to the above problem would be tuning the PLL by adjusting its center frequency to the nominal grid frequency. However, an even safer solution is the introduction of limits to the PI output, so that the VCO frequency variation is confined to the center

7 frequency (chosen equal to the grid frequency) plus or minus the lock range. A potential risk introduced by this approach is the chance of occurring so-called reset windup problems in the controller [6], which can lead to undesired oscillations, numerical overflow problems and even to instability. To avoid these difficulties, some anti windup strategy should be used for implementation of the control algorithms. This solution has been implemented by software in a TMS32LF247 DSP. Some implementation details are given in the next section. III. IMPLEMENTATION DETAILS The proposed PLL system was implemented with fixed-point arithmetic in the TMS32LF247 DSP, using a khz sampling frequency. The algorithm is executed as an interrupt service routine (ISR), which is triggered by one of the general-purpose timer circuits available on-chip. The same timer also triggers the acquisition of input signals, simultaneously with the interrupts. As the on-chip A/D converters are fast (approximately 5ns conversion time), input data is made available at the beginning of the ISR with negligible time delay. A simplified block-diagram representation of the implemented algorithm is shown in Fig. 4 (compare to the block diagram of Fig. ). The line voltages v ab and v bc are converted to the αβ reference frame through the Clarke Transformation, immediately after A/D conversion. The feedback signals corresponding to VCO output (labeled i α and i β in Fig. 4) are generated in i α sin(ωt) v ab v bc a-b Transf. v α v β X X Σ p 3φ PI Controller ω ωt s i β cos(ωt) Fig. 4 Block-diagram representation of the implemented algorithm

8 real time by table interpolations, which give the sine and the cosine of the output angle ωt. The vector product between the reference input signals and VCO outputs (v α + j v β and i α + j i β respectively) is calculated as the sum of products of the individual components. The resulting quantity can be also interpreted as the real power, according to Akagi s pq theory ([7],[8]) and it is the input error signal for the PI-Controller. Hence, in this case a p-type PLL has been implemented. The output signal produced by its phase detector (VP-PD) is called p 3φ and can be written as: p 3φ = 3.V.I.cos(φ - φ 2 ), () for the PLL in the locked state at the center frequency. In steady state, the VCO outputs (i α + j i β) lead the reference input signals (v α + jv β) by 9. This fundamental characteristic should be reminded when the PLL circuit is applied. IV. EXPERIMENTAL RESULTS The experimental results obtained by the PLL algorithm, which has been implemented with fixed point arithmetic in the TMS32LF247 DSP, were compared with simulations carried out in MATLAB. The input signals used in the simulations were the same ones acquired during the experimental tests. The sampling frequency used in the simulations was also khz. The chosen LF parameters were k P = 5 and k I = 5, yielding a lock range of approximately ω n = 7rad/s (Hz) and a damping coeficient of nearly ξ =.35. A. Unbalanced input signals In this case, in all experimental tests, as well as in the simulations, the PI output values were limited to a minimum of.5 (corresponding to 3Hz) and a maximum of.5 (corresponding to 9Hz), since the center frequency (6Hz) was normalized to p.u.

9 Six test cases have been carried out, with different initial conditions at the PI s output and different input signals (balanced and with negative-sequence unbalance). In the first test case, balanced input signals were applied and the initial value for the PI s output was set equal to one (i.e. the resulting initial frequency deviation is inside the lock range). In the second test case, unbalanced input signals were applied, containing 2.5% of negative-sequence component at the fundamental frequency, and the initial value for the PI s output was also equal to one. The results of these cases are shown in Fig. 5 and Fig. 6 respectively, where the dynamic response of the PLL circuit can be observed. In both cases, where the PI s output was initial- f(pu) error Fig. 5 and simulation results for signal balanced and the initial value for the PI s output equal to : error PI output error.5 f(pu) Fig. 6 and simulation results for signal unbalanced and the initial value for the PI s output equal to : error PI output

10 ized with., the PLL circuit locks to the desired frequency in approximately 7ms. The expected settling time would lie between approximately four to five units divided by the product ξ ω n (i.e. 6 2ms). In the second test, the output frequency presents ripples smaller than two percent. The third test case comprises balanced input signals and the PI initial value is equal to.5 (i.e. outside the lock range). The results are shown in Fig. 7. In the fourth test case, input signals with 2.5% negative-sequence imbalance at the fundamental frequency were used, and the initial value for the PI s output was set to.5. The results of this test case are shown in Fig. 8. f(pu) error Fig. 7 and simulation results for signal balanced and the initial value for the PI s output equal to.5: error PI output f(pu) error Fig. 8 and simulation results for signal unbalanced and the initial value for the PI s output equal to.5: error PI output

11 In these cases, where the PI s output is initialized to.5, the PLL takes more time to lock in the desired frequency (~25ms for balanced signals and ~43ms for unbalanced signals) than the previous ones. This occurs because the initial frequency deviation is well outside the lock range. The ripple presents in the output frequency in the fourth test is smaller than three percent. The fifth test case has balanced input signals and the initial value for the PI s output is equal to.5 (also outside the lock range). The results are shown in Fig. 9. The sixth test uses input signals unbalanced by 2.5% of negative-sequence component at the fundamental frequency f(pu) error Fig. 9 and simulation results for signal balanced and the initial value for the PI s output equal to.5: error PI output f(pu) error Fig. and simulation results for signal unbalanced and the initial value for the PI s output equal to.5: error PI output

12 and the initial value for the PI s output is equal to.5. The results are shown in Fig.. For the PI s output initialized to.5, the time the PLL takes to lock to the desired frequency is approximated the same one as when the PI s output is initialized to.5. The frequency ripple present in the sixth test is smaller than two percent. In all of the above tests, the PLL algorithm has successfully locked to the desired frequency, even in the presence of strong negative-sequence unbalances in the input voltages. With more than % of negative-sequence unbalance, the frequency jitter caused by this same unbalance remains around %. Based on the results obtained from the tests presented above, it can be error f(pu) Fig. and simulation results for 7% of sub-harmonic disturbance at Hz and the initial value for the PI s output equal to zero: error PI output. error f(pu) Fig. 2 and simulation results for 7% of sub-harmonic disturbance at Hz and the PI s output is limited: error PI output

13 said that the implemented PLL algorithm is very robust against negative-sequence unbalances coming from the three-phase input signals, up to an amount of 2.5% at least. The resulting VCO output signal will then always lock to the positive-sequence component of the input signals, thus indicating that this very algorithm can be used as a positive-sequence voltage or current detector. error f(pu) Fig. 3 and simulation results for % of subharmonic disturbance at Hz and the initial value for the PI s output equal to zero: error PI output error f(pu) Fig. 4 and simulation results for % of subharmonic disturbance at Hz and the PI s output is limited: error PI output

14 B. Sub-harmonics Four tests have been carried out to verify the performance of the PLL control software in the presence of sub-harmonic oscillations at very low frequency (Hz), under different initial conditions and limiting or not the PI controller s output. The results of these tests are shown from Fig. to Fig. 4. Fig. and Fig. 2 show the results of the tests, which have used 7% of sub-harmonic disturbance at Hz. In Fig., the system starts from zero initial condition and the PI s output is not limited. In Fig. 2, the PI s output is limited and the initial value is within the limits. and experiments show that the PLL locks to the desired frequency in both cases. For the test results presented in Fig. 3 and Fig. 4, the sub-harmonic disturbance was % at Hz. In Fig. 3 the initial value for PI s output is zero and the output is not limited. In this case, the PLL fails to lock. This problem can be corrected if limits are introduced to the PI s output, as shown in Fig. 4. The PLL output frequency then locks to the desired frequency, with only a few percent of frequency ripple. f(pu) error Fig. 5 and simulation results for harmonic disturbance and the PI s output is limited: error PI output

15 C. Harmonics This test was accomplished to verify the performance of the PLL circuit in the presence of harmonic distortion. In this case, the line voltage signals were acquired from a common bus, to which a three-phase, full-bridge rectifier is also connected. These signals were contaminated by a fifth-order harmonic component of approximately % and an eleventh-order harmonic component of nearly 5%. The THD is approximately of 5% and the waveform of this voltage v ab,ref v ab,gen can be seen in Fig. 6 with the label of v ab,ref. Fig. 5 shows the simulation and the experimental results obtained from the present test. In this case, the PI s output is limited and the initial value for its output is equal to.. The experimental results agree very well to the simulation results. The application of this PLL circuit in the control of a power electronics device was also demonstrated in this test, with the correct switching of a PWM inverter supplying a resistive load.

16 v ab,ref v ab,gen In Fig. 6, the distorted signal labeled v ab,ref is the reference signal for the PLL circuit and the voltage labeled v ab,gen is the (filtered) voltage generated by PWM switching of the inverter. The PLL circuit has successfully locked, and the inverter is synchronized with the fundamental component of the line voltage. V. CONCLUSIONS This paper describes a robust synchronizing PLL circuit, which has been analyzed and implement by software. The experimental results obtained from several tests have been comv ab,ref v ab,gen Fig. 6 results for harmonic disturbance of the switching of an inverter PWM

17 pared to MATLAB simulations, showing good agreement. Some aspects related to the system s ability to maintain synchronism in the presence of sub-harmonics, harmonics and negative-sequence unbalances have been investigated, and the implemented algorithm revealed to be robust even under such circumstances. When the input signals are contaminated with negative-sequence components, the implemented PLL is able to produce output signals locked to the positive sequence components only. This makes this PLL circuit suitable for positivesequence detection of voltages and/or currents in power electronics equipment. VI. ACKNOWLEDGEMENTS The authors are grateful to Brazilian Research Council (CNPq) for the financial support. VII. REFERENCES [] L.N. Arruda, S.M. Silva and B.J.C. Filho, PLL structure for utility connected systems, Conference Record of the Thirty-Sixth IEEE-IAS Annual Meeting (2), Volume 4, Page(s): [2] C. Zhan, C. Fitzer, V.K. Ramachandaramurthy, A. Arulampalam, M. Barnes and N. Jenkins, Software phase-locked loop applied to dynamic voltage restore (DVR), IEEE Power Engineering Society Winter Meeting, 2, Volume 3, Page(s): [3] S. Chung, A phase tracking system for three phase utility interface inverters, IEEE Transactions on Power Electronics, Volume 5 Issue 3, May 2 Page(s): [4] R.E. Best, Phase Locked Loops Theory, Design and Applications, ISBN , McGraw-Hill, 984. [5] V. Kaura and V. Blasko, Operation of a phase locked loop system under distorted utility conditions, IEEE Transactions on Industry Applications, Volume 33 Issue, Jan.-Feb. 997 Page(s):

18 [6] K.J. Åström and B. Wittenmark, Computer-Controlled Systems Theory and Design, 3 rd Edition, ISBN , Prentice-Hall, 984 [7] H. Akagi, Y. Kanagawa e A. Nabae, Instantaneous Reactive Power Compensator Comprising Switching Devices Without Energy Storage Components, IEEE Trans. Industry Applications, vol. IA-2, May-June, 984. [8] E.H. Watanabe, R.M. Stephan e M. Aredes, New Concepts of Instantaneous Active and Reactive Powers in Electrical Systems with Generic Loads, IEEE Trans. Power Delivery, vol. 8, No. 2, April 993, pp [9] E.M. Sasso, G.G. Sotelo, A.A. Ferreira, E.H. Watanabe, M. Aredes, P.G. Barbosa, Investigação dos Modelos de Circuitos de Sincronismo Trifásicos Baseados na Teoria das Potências Real e Imaginária Instantâneas (p-pll e q-pll), Proceedings of the XV CBA, Natal-RN, Brazil, September 22, pp (in portuguese). BIOGRAPHIES Diogo Rodrigues da Costa Junior was born in Rio de Janeiro State, Brazil, on June 2, 98. He received the B.Sc. degree from Federal University of Rio de Janeiro, in 23. He is involved in research projects of the Power Electronic Laboratory from the COPPE/UFRJ, since 2. He is enrolled in M.Sc. at COPPE/UFRJ in Power Electronics and, with Dr. Rolim and Dr. Aredes, is developing the digital control of a prototype of a Dynamic Voltage Restorer. Luís Guilherme Barbosa Rolim was born in Niterói, Brazil, in 966. He received the B.S. and M.S. degrees from the Federal University of Rio de Janeiro (UFRJ), Rio de Janeiro, Brazil, and the Dr.-Ing. degree from the Technical University Berlin, Berlin, Germany, in 989, 993, and 997, respectively, all in electrical engineering. Since 99, he has been a Faculty Member of the Electrical Engineering Department, Escola Politécnica, UFRJ, where he teaches and conducts research on power electronics, drives, and microprocessor control. He is a member of the Power Electronics Research Group at COPPE/UFRJ and has authored more than 2 papers published in brazilian and international conference proceedings and technical journals. Maurício Aredes (S 94, M 97) was born in São Paulo State, Brazil, on August 4, 96. He received the B.Sc. degree from Fluminense Federal University, Rio de Janeiro State in 984, the M.Sc. degree in Electrical Engineering from Federal University of Rio de Janeiro in 99, and the Dr.-Ing. Degree (magna cum laude) from Technische Universität Berlin in 996. From 985 to 988 he worked at the Itaipu HVDC Transmission System and from 988 to 99 in the SCADA Project of Itaipu Power Plant. From 996 to 997 he worked within CEPEL Centro de Pesquisas de Energia Elétrica, Rio de Janeiro, as R&D Engineer. In 997, he became an Associate Professor at the Federal University of Rio de Janeiro, where he teaches Power Electronics. His main research area includes HVDC and FACTS systems, active filters, Custom Power and Power Quality Issues. Dr. Aredes is a member of the Brazilian Society for Automatic Control and the Brazilian Power Electronics Society.

19 List of Figure Captions Fig. Block diagram of basic PLL structure Fig. 2 Small-signal block diagram. Fig. 3 results for sub-harmonic disturbances at Hz: Fig. 4 Block-diagram representation of the implemented algorithm Fig. 5 and simulation results for signal balanced and the initial value for the PI s output equal to : error PI output Fig. 6 and simulation results for signal unbalanced and the initial value for the PI s output equal to : error PI output Fig. 7 and simulation results for signal balanced and the initial value for the PI s output equal to.5: error PI output Fig. 8 and simulation results for signal unbalanced and the initial value for the PI s output equal to.5: error PI output Fig. 9 and simulation results for signal balanced and the initial value for the PI s output equal to.5: error PI output Fig. and simulation results for signal unbalanced and the initial value for the PI s output equal to.5: error PI output Fig. and simulation results for 7% of sub-harmonic disturbance at Hz and the initial value for the PI s output equal to zero: error PI output. Fig. 2 and simulation results for 7% of sub-harmonic disturbance at Hz and the PI s output is limited: error PI output Fig. 3 and simulation results for % of sub-harmonic disturbance at Hz and the initial value for the PI s output equal to zero: error PI output Fig. 4 and simulation results for % of sub-harmonic disturbance at Hz and the PI s output is limited: error PI output Fig. 5 and simulation results for harmonic disturbance and the PI s output is limited: error PI output Fig. 6 results for harmonic disturbance of the switching of an inverter PWM