A 40fJ/c-s 1 V 10 bit SAR ADC with Dual Sampling Capacitive DAC Topology

Transcription

1 JOURNAL OF SEMICONUCTOR TECHNOLOGY AN SCIENCE, VOL.11, NO.1, MARCH, 011 OI: /JSTS A 40fJ/c-s 1 V 10 bit SAR AC with ual Samplig Capacitive AC Topology Bihee Kim, Log Ya, Jerald Yoo, ad Hoi-Ju Yoo Abstract A 40 fj/c-s, 1 V, 10-bit SAR AC is preseted for eergy costraied wearable body sesor etwork applicatio. The proposed 10-bit samplig capacitive AC topology reduces switchig eergy by 6% compared with 10-bit covetioal SAR AC. Also, it is more robust to capacitor mismatch tha the covetioal architecture due to its cacellig effect of each capacitive AC. The proposed SAR AC is fabricated i 0.1 m 1P6M CMOS techology ad occupies 1.17 mm icludig pads. It dissipates oly 1.1 W with 1 V supply voltage while operatig at 100 ks/s. Ide Terms SAR AC, samplig, low eergy, wearable body sesor etwork I. INTROUCTION Recetly, a battery-less disposable healthcare sesor [1, ] with self cofigured etwork cotroller eables wearable healthcare i persoal daily life. Such healthcare sesor eeds to harvest the power from eteral etwork cotroller through cm-rage iductive couplig. I such circumstaces, the power budget of etire sesor is etremely limited as low as 1 W []. A AC is oe of the key fuctioal blocks whose power cosumptio ad coversio rate are essetial to realize cotiuous healthcare. Amog may types of ACs, the SAR (Successive Approimatio Register) AC is oe of the most widely Mauscript received Nov. 4, 010; revised Ja. 5, 011. ep. EE., KAIST, Korea vii@kaist.ac.kr used i eergy costraied applicatio [3, 4] due to its miimum aalog blocks. Eve though the SAR AC [3, 4] cosumes low power (about 5 W), it is still beyod the power budget of the battery-less disposable healthcare sesor [1, ]. For these reasos, a lot of previous works focused o reducig eergy of the SAR AC [6, 7]. The SAR AC cosists of digital logics to geerate cotrol sigal, a capacitive AC (digital-to-aalog coverter) for successive charge distributio to evaluate the sampled sigal, ad a comparator. Sice the switchig power of a capacitive AC is domiat portio i the SAR AC s power cosumptio, a lot of works focusig o savig the switchig eergy of the capacitive AC have bee reported [6, 7]. Previous works such as proposed i [6] reduce switchig eergy by elimiatig uecessary switchig operatio with splittig capacitors i the capacitive AC. These methods ca save 37% of the switchig eergy compared to the covetioal oes [5]. However, sice the requiremet of low power is much striget, this work proposes a ew architecture for the capacitive AC of SAR AC. It was proved that it would be able to save 6% of the switchig eergy compared to the covetioal switchig scheme [5] ad 40% eve compared to the previous work [6] i 10-bit resolutio. It elimiates MSB calculatio switchig eergy as well as uecessary switchig operatio by samplig iput voltage at both odes of the comparator. It is called samplig method i this paper. This paper proposes a ew 10-bit AC fabricated i a 0.1 m CMOS. Sectio II eplais the operatio of the proposed SAR architecture, compared with that of the covetioal oes. Various aalyses about switchig power are eplaied i sectio III. The effects of capacitor

2 4 BINHEE KIM et al : A 40FJ/C-S 1V 10 BIT SAR AC WITH UAL SAMPLING CAPACITIVE AC TOPOLOGY mismatch i the proposed architecture are ivestigated i sectio IV. Implemetatio results are preseted i sectio V. Fially, sectio VI draws our coclusios. II. THE PROPOSE SAR ARCHITECTURE I order to compare the operatios, we first review the operatio of the covetioal SAR AC show i Fig. 1. The SAR AC is composed of a biary capacitive AC, a comparator, ad SAR cotrol logics. The total capacitace of a biary capacitive AC is C where C is a uit capacitace. These capacitors are coected to oe side of a comparator i parallel. I sample mode, the AC samples V ref -V i, ad the etire bottom plates of capacitive AC are coected to the groud i hold mode. The bottom plates of capacitors are coected to the referece voltage or groud i calculatio phase. The proposed architecture splits a capacitive AC ito two ad samples iput voltage at both AC as show i Fig.. Total capacitace of a capacitive AC is the same as covetioal oe with C, but each capacitive AC of -1 C capacitace is coected to respective iput side of a comparator separately. The proposed architecture is sigle-eded, ot differetial. I other words, iput Fig. 1. Covetioal SAR AC Architecture ad Operatio. (a) Sample, (b) Hold ad (c) Calculatio. Fig.. The proposed SAR AC Architecture ad Operatio. (a) Sample, (b) Hold ad (c) Calculatio. voltage odes are same at upper capacitive AC ad lower capacitive AC. The operatio of the proposed SAR AC is as follows. First of all, the upper side capacitive AC samples V ref -V i, while the bottom side capacitive AC samples V i. I hold mode (after sample mode), the etire bottom plates of capacitive AC are coected to the groud. Simultaeously, MSB ca be calculated i hold mode. I this way, this samplig method iduces MSB calculatio with o switchig eergy cosumptios. Because almost the half of the total switchig eergy is cosumed at the MSB calculatio phase i the covetioal architecture, the proposed samplig method has the possibility of reducig total switchig eergy. The rest of the bits are calculated as follows. The timig diagram of 4-bit SAR AC operatio whe output code is 1000 is show as a eample i Fig. 3. Each switch ame is show i Fig. 1(c) ad Fig. (c). I the case of the covetioal SAR AC, S 3 is coected to the referece voltage to decide MSB i the first cycle. epedig o MSB, coectios of S 3 ad S is decided

3 JOURNAL OF SEMICONUCTOR TECHNOLOGY AN SCIENCE, VOL.11, NO.1, MARCH, III. SWITCHING ENERGY ANALYSIS Fig. 3. Timig iagram of operatio of Covetioal SAR AC ad the proposed ual Samplig SAR AC i calculatio phase. i the secod cycle. I the same maer, coectios of S ad S 1 are decided depedig o the secod bit i the third cycle. I the case of the proposed SAR AC, the MSB is decided i hold mode. epedig o the MSB, coectios of S U ad S are decided i the first cycle. S UX ad S X do the opposite operatio. I the secod cycle, coectios of S U1 ad S 1 are decided depedig o the secod bit. The completio of calculatio of 4-bit AC is doe at the third cycle i the proposed architecture, while doe at the fourth cycle i the covetioal architecture. Fig. 4 shows the circuit diagram of a comparator. A dyamic comparator is used for low power compesatio. PMOS ad NMOS coected to CLK# sigal block cotiuous curret flow. A comparator is activated at the edge of CLK# sigal. By the complemetary operatio of sw(switch) sigal ad CLK# sigal, the comparator output sigal is trasmitted to a latch. Fig. 4. Circuit iagram of Comparator. The SAR AC cosists of digital logics, a capacitive AC, ad a comparator as referred i sectio II. This sectio is focused o switchig eergy aalysis of the proposed ual Samplig SAR AC compared with the covetioal SAR AC. Usig the method of switchig eergy calculatio i referece [7], the eergy cosumptios for each bit geeratio i three kids of SAR AC s architecture have bee derived i Fig. 5. The split cap architecture i [6] also compared with the proposed architecture. The split cap architecture looks similar to the proposed oe from a view poit that the AC i covetioal oe [5] is split ito two blocks as show i Fig. 5. However, while the etire capacitors i the split cap method are coected to the oe iput ode of the comparator, split ACs i the proposed are coected to both iput odes of the comparator. I Fig. 5, 3-bit SAR AC is preseted as a eample. I the MSB calculatio phase of the covetioal architecture ad the split cap architecture, the half of the total capacitor has to be coected to the referece voltage. MSB calculatio power has great portio of weight o the total power cosumptio, especially i the split cap architecture. If switchig eergy of each bit ecept MSB phase is compared, proposed oe cosumes more power. Hece, switchig eergy of each bit is E 1 V REF ( Q 1 Q V REF ( C ( V 1 V ) C (( V 1 V ) ) V (1) )) 1 REF 1 where C 1 represets the capacitace coected to the referece voltage i th phase ad (+1)th phase simultaeously, C represets the capacitace ewly coected to the referece voltage i (+1)th phase, represet voltage at ode coected to the comparator i th phase, ad V 1 represet voltage at ode coected to the comparator i (+1)th phase. As lower bit is calculated, V 1 V ad C are gettig lower. Therefore, as lower bit is calculated, much less power is cosumed. With this result, eve though switchig eergy of each bit is cosumed more i the proposed architecture tha i V

4 6 BINHEE KIM et al : A 40FJ/C-S 1V 10 BIT SAR AC WITH UAL SAMPLING CAPACITIVE AC TOPOLOGY Covetioal Architecture[5] Split Cap Architecture[6] The proposed Architecture Architecture Vi 1/ V ref CV ref 3/ V ref CV ref 5/ V ref CV ref 7/ V ref CV ref Normalized Average Each Bit Calculatio Eergy MSB d 3rd MSB d 3rd MSB d 3rd 5 CVref 5 CVref 3 9 CVref 5 CVref 13 CVref 7 CV ref CV ref CV ref CV ref 1 CVref 1 1 CVref 5 CVref CV ref 0 CV ref 0 CV ref 0 CV ref 0 1 Fig. 5. Comparisos of switchig power of three architectures. Covetioal [5], Split Cap [6], the proposed architectures. 1 CVref 4 3 CVref 4 3 CVref the covetioal ad the split cap architecture, total sum of every bit calculatio eergy is less i the proposed oe tha i the covetioal ad the split cap oe due to the elimiated MSB calculatio eergy. Accumulated switchig eergy distributio at each bit is preseted i Fig. 6. As show i Fig. 6, switchig eergy of MSB calculatio i the proposed architecture is 0. By this property, switchig eergy of coversio i the proposed architecture is almost half of that i the split cap architecture, as plotted i 10 th bit i Fig. 6. As a result, the proposed architecture ca save 6% of switchig eergy compared to the covetioal oe i 10-bit resolutio. Also it ca eve save 40% of switchig eergy compared to the split cap architecture. Fig. 7 shows the compariso of switchig eergy at each code i three kids of architectures: the covetioal architecture, the split cap, ad the proposed oe. These models are proved with rigorous SPICE simulatios. This figure shows the switchig eergy at each output code. As show i Fig. 6, the proposed architecture ca save 6% of switchig eergy compared to the covetioal oe ad save 40% of switchig eergy compared to the Fig. 6. Accumulated Average Switchig Eergy at Each Bit. Covetioal architecture [5], Split cap architecture [6], the proposed architecture. Fig. 7. Compariso of Switchig Eergy i 10-bit AC Calculatio Phase. Covetioal architecture [5], Split cap architecture [6], the proposed architecture. Switchig eergy of the proposed architecture is almost half of that of split cap architecture.

5 JOURNAL OF SEMICONUCTOR TECHNOLOGY AN SCIENCE, VOL.11, NO.1, MARCH, split cap architecture i 10-bit resolutio. ue to similarity i the switchig mechaism method, the shape of eergy distributio curve of the proposed oe looks similar to that of the split cap architecture. IV. CAPACITOR MISMATCH Accuracy of SAR AC ca be affected by capacitor mismatch, which is occurred by parasitic capacitaces of capacitive AC, process variatios of capacitors, etc. I this sectio, two factors of capacitor mismatch, parasitic capacitaces of capacitive AC ad process variatios of each capacitor, are aalyzed i the covetioal SAR AC ad the proposed ual Samplig SAR AC. 1. Parasitic Capacitaces SAR AC suffers from the parasitic capacitaces of the output odes of the capacitive AC. I the ual Samplig SAR AC, the output odes of two capacitive AC suffer from the ow parasitic capacitaces respectively, while the covetioal ad the split capacitor structures have oe ode with parasitic capacitaces. To compare the effect of parasitic capacitaces of the ual Samplig SAR AC with that of the covetioal ad the split capacitor SAR AC, effect to the accuracy of each ACs by parasitic capacitace variatios are cov aalyzed. Whe idicates parasitic capacitace of the covetioal SAR AC, each bit, C ( 0), C (1),..., C ( 1) is decided with followig equatio i the covetioal SAR AC. ( 0), (1),..., ( 1) is decided with followig equatio i the ual Samplig SAR AC (0) arg mi Vref ( (,.. (0) (1) ( 1) 1 (0) (1) _ dow... (1) _ up ( 1)... )) V ( 1) The error betwee output of coversio ad iput i the ual Samplig SAR AC ca be represeted as Eq. (5). Error V ref ( 1 (0) (1)... i ( 1) ) V Based o these equatios, SNR versus a ratio of parasitic capacitaces to total capacitace of capacitive AC with the siusoidal iput is draw i Fig.. This graph is draw with two assumptios. First assumptio is that parasitic capacitace is proportioal to the total capacitace of capacitive AC. Accordigly, parasitic capacitace of the covetioal SAR AC, cov, is same as sum of parasitic capacitaces of the ual Samplig SAR AC, _ up _ dow. Secod assumeptio is that parasitic capacitace of upper capacitive AC ad lower capacitive AC is same, i (4) (5) _ up _ dow. With these assumptios, the graph i Fig. idicates that SNR of the ual Samplig SAR arg mi C ( 0 ), C (1).. C ( 1) V ref ( 1 C (0) C (1) cov... C ( 1) ) V i () The error betwee output of coversio ad iput i the covetioal SAR AC ca be represeted as Eq (3). Error cov V ref ( 1 C(0) C(1)... C( 1) ) V i (3) Whe _ idicates parasitic capacitace of upper up capacitive AC ad _ idicates parasitic dow capacitace of lower capacitive AC, each bit, Fig.. SNR versus a ratio of parasitic capacitaces to total capacitace of capacitive AC with the siusoidal iput.

6 BINHEE KIM et al : A 40FJ/C-S 1V 10 BIT SAR AC WITH UAL SAMPLING CAPACITIVE AC TOPOLOGY AC is higher tha that of the covetioal SAR AC i all the variatios of parasitic capacitace rates. To aalyze the effect of differece betwee parasitic capacitaces of upper capacitive AC ad those of lower AC i the ual Samplig SAR AC, SNR versus ratio of parasitic capacitace of upper capacitive AC to that of lower capacitive AC is show i Fig. 9. ash lie idicates the SNR of case that ratio of parasitic capacitaces to total capacitace of capacitive AC is i the covetioal SAR AC. ots idicate SNR poits correspodig to the ratio of parasitic capacitaces of upper capacitive AC to that of lower capacitive AC i the ual Samplig SAR AC. I this case, total parasitic capacitaces of upper capacitive AC ad lower capacitive AC is fied as 1.1% of total capacitace of capacitive AC to make same coditio with the covetioal SAR AC. As show i Fig. 9, eve worst case rate of SNR of the ual Samplig SAR AC is higher tha SNR of the covetioal SAR AC i the same coditio i which total parasitic capacitace is same. Worse SNR of the covetioal SAR AC with parasitic capacitaces tha the ual Samplig SAR AC with parasitic capacitaces ca be eplaied with Fig. 10 ad Fig. 11. Fig. 10 idicates the NL ad Fig. 11 idicates the INL of the covetioal SAR AC ad the ual Samplig SAR AC i the case that the rate of parasitic capacitaces ad total capacitace of capacitive AC is NL of the covetioal SAR AC ad that of the ual Samplig SAR AC does t have much differece. INL of the covetioal SAR AC is much worse tha the ual Samplig SAR AC. INL graph shows the sie iput ca be trucated more at the upper part i the covetioal SAR AC tha the ual Samplig SAR AC. (a) Fig. 9. SNR versus ratio of parasitic capacitace of upper capacitive AC to that of lower capacitive AC. (b) Fig. 11. INL of case that rate of parasitic capacitaces ad total capacitace of capacitive AC is (a) Covetioal SAR AC, (b) Proposed SAR AC.. Process Variatios of Capacitors (a) (b) Fig. 10. NL of case that rate of parasitic capacitaces ad total capacitace of capacitive AC is (a) Covetioal SAR AC, (b) Proposed SAR AC. Capacitor mismatch by process variatios largely affect to accuracy i the SAR AC architecture. I this sectio, simulatio results with capacitor mismatch are preseted. To see the effect of capacitor mismatch, Mote Carlo simulatio is doe. The values of the uit capacitors are take to be Gaussia radom variables with stadard deviatio of 5% (σ 0 /C 0 =0.05), ad the AC is otherwise ideal. Fig. 1 ad Fig. 13 shows the results of 10,000 Mote Carlo rus, where the stadard deviatio of the INL ad NL are plotted versus output code at the 10-bit

7 JOURNAL OF SEMICONUCTOR TECHNOLOGY AN SCIENCE, VOL.11, NO.1, MARCH, level. Fig. 1 shows the results of the covetioal SAR AC ad Fig. 13 shows the results of the ual Samplig SAR AC. The graph shows that liearity characteristics of the ual Samplig SAR AC are better tha that of the covetioal SAR AC. The reaso of these results ca be eplaied with followig equatios. Each bit is decided as Eq. (6) i the Covetioal SAR AC, where _ idicates sum of capacitor mismatch ad cov cov tot _ idicates capacitor mismatch of -th capacitor. Each bit is decided as Eq. (7) i the ual Samplig SAR AC, where idicates sum of capacitor _ upp _ tot mismatch i upper capacitive AC, _ upp _ idicates capacitor mismatch of -th capacitor i upper capacitive AC, _ low _ tot idicates sum of capacitor mismatch i lower capacitive AC ad _ low _ idicates capacitor mismatch of -th capacitor i lower capacitive AC. arg mi C (0).. C ( 1) V ref ( ( 1 cov _ 0 ) C(0)... ( cov _ tot cov _ 1 ) C( 1) ) V i (6) arg mi (0).. ( 1) ( ( _ upp _ 0) (0)... ( _ upp _ 1) ( 1) Vref ( ( _ upp _ tot _ low _ 0 )... ( (0) _ low _ 1 _ low _ tot ) ( 1) 1 ) ) V i (7) I the case of the ual Samplig SAR AC, error terms are multiplied by half compared with the Covetioal SAR AC as show i Eq. (6) ad Eq. (7). This factor effects to the liearity characteristics. Fig. 1. Liearity simulatio results of 10,000 Mote Carlo rus, where the stadard deviatio of the INL ad NL are plotted versus output code at the 10-bit level i the covetioal SAR AC. The values of the uit capacitors are take to be Gaussia radom variables with stadard deviatio of 5% (σ 0 /C 0 =0.05), ad the AC is otherwise ideal. Fig. 14. Photomicrograph of the test chip. Fig. 13. Liearity simulatio results of 10,000 Mote Carlo rus, where the stadard deviatio of the INL ad NL are plotted versus output code at the 10-bit level i the ual Samplig SAR AC. The values of the uit capacitors are take to be Gaussia radom variables with stadard deviatio of 5% (σ 0 /C 0 =0.05), ad the AC is otherwise ideal. Fig. 15. Measured NL/INL plots of AC.

8 30 BINHEE KIM et al : A 40FJ/C-S 1V 10 BIT SAR AC WITH UAL SAMPLING CAPACITIVE AC TOPOLOGY V. IMPLEMENTATION RESULTS The AC has bee fabricated i a 0.1- m CMOS techology. A die photograph is show i Fig. 14. The static performace of the AC is show i Fig. 15. To overcome capacitor mismatch problem i layout, commo cetroid layout method is chose for this work ad recursive rearrage of layout is doe with post layout simulatio. The NL is i the rage of -0.63/+0.66 ad INL is i the rage of -0.9/+0.9. The dyamic performace of the AC is show i Fig. 16. A fast Fourier trasform of a 1 khz sie wave iput sampled at 100 ks/s is show i Fig. 16 (a). AC has its peak at 1 khz with 5.4 db of SNR. It correspods to a effective umber of bit (ENOB) of.4 bits. The iput frequecy swept from C to Nyquist ad correspodig SNR is plotted i Fig. 16(b). The SNR does ot drop by 3 db util past the Nyquist frequecy. Table 1 shows the summary of performace with this work. It is fabricated i 0.1- m CMOS 1P6M. The supply voltage is 1 V, ad has 100 ks/s samplig rate. Iput rage is 0 V 600 mv. It achieves SNR of 5.4 db with 1 khz sie wave sampled at 100 ks/s. This Figure of merits has 40 fj/coversio-step. Its area is 1.33 mm 0. mm with 53 ff of uit capacitace icludig pads. Table shows performace comparisos with other works. The proposed AC speds least eergy with a efficiet coversio step. It has least power dissipatio with 1.1 W compared with other works. FoM(Figure of Merits) is also least value with 40 fj/coversio-step compared with other works. Table 1. Summary of Performace (a) Techology 0.1 m CMOS 1P6M Supply Voltage 1 V Samplig Rate 100 ks/s Resolutio 10-bit Iput Rage mv SNR (f i = 1 khz) 5.4 db ENOB.4 FOM 40 fj/c-s Active Area (icludig pads) 1.33 mm 0. mm VI. CONCLUSIONS (b) Fig. 16. (a) FFT of 1kHz sie wave sampled at 100 ks/s, (b) SNR at iput frequecy swept from C to Nyquist frequecy. A eergy-efficiet SAR AC is preseted. The proposed ual-samplig architecture provides eergyefficiet switchig process with capacitive AC divided ito two. This ual Samplig architecture saves switchig eergy at calculatio phase by 6% compared with the covetioal architecture [5] ad 40% compared with the split cap architecture [6] i 10-bit resolutio. Table. Performace Compariso Source JSSC 07 [] JSSC 07 [9] ISSCC 0 [10] This Work Techology 0.1 m 0.1 m 0.1 m 0.1 m Supply Voltage(V) 1 V 0.9 V 1 V 1 V Samplig Rate 100 ks/s 00 ks/s 100 ks/s 100 ks/s ENOB FoM 166 fj/c-s 64 fj/c-s 56 fj/c-s 40 fj/c-s Power issipatio 5 W 6.15 W 3. W 1.1 W

9 JOURNAL OF SEMICONUCTOR TECHNOLOGY AN SCIENCE, VOL.11, NO.1, MARCH, Also, it is more robust to capacitor mismatch tha the covetioal architecture due to its cacellig effect of each capacitive AC. It is demostrated by AC test chip with 1.1 W, 1 V,.4-ENOB performace. ACKNOWLEGMENTS This work was supported by the IT R& program of MKE/KEIT, [00-F-04, Wearable Persoal Compaio for u-computig collaboratio]. Bihee Kim (S 0) received the B.S. degrees i epartmet of Electrical Egieerig from the Korea Advaced Istitute of Sciece ad Techology (KAIST), aejeo, Korea, i 00, where she is curretly workig toward the master degree i the same departmet at KAIST. Her curret research iterests iclude the low power SAR AC. REFERENCES [1] Log Ya, Jerald Yoo, Bihee Kim ad Hoi-Ju Yoo, A 0.5 V rms 1 W patch type fabric sesor for wearable body sesor etwork, IEEE A-SSCC, pp , Nov., 009. [] Jerald Yoo, Log Ya, Seulki Lee, Yogsag Kim ad Hoi-Ju Yoo, A 5. mw Self-Cofigured Wearable Body Sesor Network Cotroller ad a 1 W 54.9% Efficiecy Wirelessly Powered Sesor for Cotiuous Health Moitorig System, IEEE J. Solid-State Circuits, Vol.45, pp.17-1, Ja., 010. [3] Rafal, lugosz, ad K. Iiewski, Fleible architecture of ultralow-power curret-mode iterleaved successive approimatio aalog-to digital coverter for wireless sesor etworks, VLSI esig, 007, Apr [4] N. Verma ad A.C Chadrakasa, A 5 W 100 ks/s 1b AC for wireless applicatio, IEEE Iteratioal Solid State Circuits., Coferece ig. Tech. Papers(ISSCC), pp.-3, Feb., 006. [5] James L.Mccreary et al, All-MOS Charge Redistributio Aalog-to-igital Coversio Techiques- Part I, IEEE J. Solid-State Circuits, pp , ec., [6] Bria P. Gisburg ad Aatha P. Chadrakasa, 500-MS/s 5-bit AC i 65-m CMOS With Split Capacitor Array AC, IEEE J. Solid-State Circuits, Vol.4, No.4, pp , Apr., 007. [7] Bria P. Gisburg ad Aatha P. Chadrakasa, A Eergy- Efficiet Charge Recyclig Approach for a SAR Coverter With Capacitive AC, i Proc. IEEE It. Symp. Circuits ad Systems, 005, Vol.1, pp.14-17, May., 005. Log Ya (S 07) received the B.S. ad M.S degrees i epartmet of Electrical Egieerig from the Korea Advaced Istitute of Sciece ad Techology (KAIST), aejeo, Korea, i 007 ad 009, respectively. He is curretly pursuig the Ph.. degree i electrical egieerig at KAIST. He has worked o developig the low power FSK trasmitter for body chael commuicatio, ad low oise, wirelessly powered sesor for wearable body sesor etwork. His curret research iterests iclude desig of eergy-efficiet biomedical micro-system for body area etwork. Jerald Yoo (S 05) received the B.S., M.S. ad Ph.. degrees i epartmet of Electrical Egieerig from the Korea Advaced Istitute of Sciece ad Techology (KAIST), aejeo, Korea, i 00, 007 ad 010, respectively. His Ph.. work cocered low eergy wearable body area etwork trasceiver, wireless power trasmissio ad low-power biomedical microsystem. I 010, he joied the faculty of the Microsystems Egieerig at Masdar Istitute of Sciece ad Techology, Masdar City, Abu habi, Uited Arab Emirates ad ow is a assistat professor.

10 3 BINHEE KIM et al : A 40FJ/C-S 1V 10 BIT SAR AC WITH UAL SAMPLING CAPACITIVE AC TOPOLOGY Hoi-Ju Yoo (M 95-SM 04-F 0) graduated from the Electroic epartmet of Seoul Natioal Uiversity, Seoul, Korea, i 193 ad received the M.S. ad Ph.. degrees i epartmet of Electrical Egieerig from the Korea Advaced Istitute of Sciece ad Techology (KAIST), aejeo, i 195 ad 19, respectively. His Ph.. work cocered the fabricatio process for GaAs vertical optoelectroic itegrated circuits. From 19 to 1990, he was with Bell Commuicatios Research, Red Bak, NJ, where he iveted the two-dimesioal phase-locked VCSEL array, the frot-surface-emittig laser, ad the high-speed lateral HBT. I 1991, he became a maager of the RAM desig group at Hyudai Electroics ad desiged a family of fast-1m RAMs to 56M sychroous RAMs. I 199, he joied the faculty of the epartmet of Electrical Egieerig at KAIST ad ow is a full professor. From 001 to 005, he was the director of System Itegratio ad IP Authorig Research Ceter (SIPAC), fuded by Korea Govermet to promote worldwide IP authorig ad its SOC applicatio. From 003 to 005, he was the full time Advisor to Miister of Korea Miistry of Iformatio ad Commuicatio ad Natioal Project Maager for SoC ad Computer. I 007, he fouded System esig Iovatio & Applicatio Research Ceter (SIA) at KAIST to research ad to develop SoCs for itelliget robots, wearable computers ad bio systems. His curret iterests are high-speed ad low-power Network o Chips, 3- graphics, Body Area Networks, biomedical devices ad circuits, ad memory circuits ad systems. He is the author of the books RAM esig (Seoul, Korea: Hogleug, 1996; i Korea), High Performace RAM (Seoul, Korea: Sigma, 1999; i Korea), Low- Power NoC for High-Performace SoC esig (CRC Press, 00), ad chapters of Networks o Chips (New York, Morga Kaufma, 006). r. Yoo received the Electroic Idustrial Associatio of Korea Award for his cotributio to RAM techology i 1994, the Hyi evelopmet Award i 1995, the esig Award of ASP- AC i 001, the Korea Semicoductor Idustry Associatio Award i 00, the KAIST Best Research Award i 007, the Asia Solid-State Circuits Coferece (A-SSCC) Outstadig esig Awards i 005, 006 ad 007, ad the AC/ISSCC Studet esig Cotests Award i 007 ad 00. He is a IEEE fellow ad servig as a Eecutive Committee Member ad the Far East Secretary for IEEE ISSCC, ad a Steerig Committee Member of IEEE A-SSCC. He was the Techical Program Committee Chair of A-SSCC 00.