f Sum(n) = 6 8 δ(n)+ 1 8 δ(n 1)+ 1 δ(n+1) (1) f Sum(n) = 2 8 δ(n)+ 1 8 δ(n 1)+ 4 8 δ(n 2)+ 1 δ(n 3) (2) n f Sum (n) 0 e 0 = 1 p ap b p c p ap b p c

Transcription

1 FEMTO: Fast Error Aalysis i Multipliers through Topological Traversal Deepashree Segupta ad Sachi S. Sapatekar Departmet of Electrical ad Computer Egieerig Uiversity of Miesota, Mieapolis, MN 55455, USA. Abstract Approximate computig has emerged as a circuit desig techique that ca reduce system power without sigificatly sacrificig the output quality i error-resiliet applicatios. However, there are few systematic approaches for systematically ad efficietly determiig the error itroduced by approximate hardware uits. This paper focuses o the developmet of error aalysis techiques for approximate multipliers, which are a key hardware compoet used i error-resiliet applicatios, ad presets a ovel algorithm that efficietly determies the probability distributio of the error itroduced by the approximatio. The accuracy of the techique is demostrated to be comparable to Mote Carlo simulatios, but is sigificatly less computatioally itesive. I. INTRODUCTION Approximate computig [] has emerged as a promisig approach that ca potetially achieve large efficiecies i the desig of errorresiliet systems, such as those that implemet applicatios related to multimedia image/video processig ad streamig), data miig, ad huma auditory ad visual perceptio. By deliberately itroducig approximatios, this approach reduces hardware costs, i terms of eergy, power, ad area, while esurig that errors are limited to a level that ca be tolerated by the ed-user. A vital igrediet of ay methodology based o approximate desig is a fast ad accurate procedure that ca quatify the distributio of error ijected ito a computatio by a approximatio scheme. The most commo buildig blocks that are used to build hardware for error-resiliet computatios are adders ad multipliers. While existig methods have made some progress i aalyzig errors i adders [] [5], desig of the approximate multipliers [6] [9] still relies o error metrics from Mote Carlo simulatios for performace evaluatio sice there are o kow aalytical methods that ca scalably ad accurately aalyze the error i multipliers. I this work, we propose a ovel algorithm, FEMTO: Fast Error Aalysis i Multipliers through TOpological Traversal, to efficietly quatify the errors i the output of a approximate multiplier by determiig their probability of occurrece. The errors i approximate circuits which follow discrete asymmetric distributios [], are propagated through etworks usig a topological traversal, ad FEMTO uses the frequecy domai to reduce computatio. At the gate level of approximate circuit desig, the error of a logic fuctio ca be quatified by comparig the truth table of the approximate ad exact implemetatios. However, this is ot scalable beyod a small umber of iputs because the size of the truth table grows expoetially with the umber of iputs. Prior approaches that attempt to overcome the computatioal bottleeck of error estimatio ca be classified ito two categories: ) Methods that estimate the rage of error: These methods capture the rage of the error i approximate computatio i terms of its miimum ad maximum value, ad are primarily based o iterval ad affie arithmetic [], with modificatios [3], [], [] suitable for asymmetric distributios of errors i approximate circuits. However, these approaches are computatioally itesive, may lead to storage explosio [], ad ofte overestimate errors [3]. ) Methods that capture the statistics of the error distributio: These methods use the computatioally itesive Mote Carlo simulatios usig millios of radom iput vectors to obtai various error metrics i a approximate computatio such as the error rate, error sigificace, average error, ad mea square error to quatify the error i approximate systems [], [5], [6], [], [4]. I several scearios, it is essetial to determie the etire probability distributio of error, e.g. for hypothesis testig i stochastic sesor circuits [5] ad for accuracy evaluatio [], [9] of approximate circuits which is curretly performed by exhaustive/mote Carlo simulatios). FEMTO captures the etire probability distributio of error, ad is sigificatly faster tha Mote Carlo simulatios. The advatage of obtaiig a aalytical expressio for the error probability mass fuctio PMF) is that the error rage, its statistics ad percetiles ca be easily deduced from the cumulative distributio fuctio CDF), ad this method ca be used i ay framework that relies o Mote Carlo simulatios to evaluate performace of approximate multipliers. pmfa) A Partial product geeratio Σ Σ B PP lasṫ.. PP 3 PP PP Σ S + S S last+ S last N-bit product, R+ R NxN Multiplier pmfb) S + S Error distributio of Σ FEMTO Framework pmf S ) pmf S ) pmf S last) Covolve pmf R) Fig.. Schematic of the FEMTO algorithm o a usiged multiplier. Our algorithm is schematically represeted i Fig. o a N-bit N-bit usiged multiplier. The statistics of the two N-bit operads A ad B i.e., the probability that they take o values ad ) are provided as a iput to our approach. The multiplicatio process geerates partial products PP,, PP last ) as show i the figure, ad the computatio proceeds by successively addig each partial product to the partial sum computed so far. Each such additio is performed by a array, Σ, of approximate ad/or exact full adders, ad is characterized by a error PMF for the adder array. Our approach proceeds as follows: ) We express the PMF of the error of each full adder Sectio II). ) We use these PMFs to compute the PMF of S i, the error itroduced by the approximate adders at the i th level, over the statistical distributio of iputs A ad B. 3) The total error itroduced by the multiplicatio is the sum of the

2 S i variables. We show that the PMF of the total error ca be expressed as a covolutio of a weighted set of error PMFs for idividual full adders, ad demostrate how this covolutio is performed efficietly i the frequecy domai i a itelliget maer, avoidig a explosio i the umber of terms i the frequecy-domai represetatio of the PMF Sectio III). 4) We ehace the speed of our algorithm by partitioig the N-bit operads ito K-bit slices Sectio IV). We experimetally validate our results i Sectio V o a set of approximate multiplier schemes ad coclude the paper i Sectio VI. II. CHARACTERIZING THE PMF OF FULL ADDERS I priciple, the PMF of ay combiatioal structure ca be characterized through its truth table ad the statistics of the iputs. However, the size of the truth table icreases expoetially with the size of the iput space, ad such a direct characterizatio is impractical for a multiplier. Hece, we work with a fudametal uit that ca reasoably be characterized i this case, a full adder FA) ad develop the error PMF for the multiplier hierarchically. Specifically, the error PMF of a sigle adder is used to obtai the error PMF of each row of FAs that sums the partial products, ad fially the error distributio of the etire approximate multiplier. This sectio explais how we use the iput distributio ad Boolea fuctio of a FA to obtai its output error distributio. Let us explai our approach with the example of a approximate FA, appx from [6], show i Fig.. The truth table of its output, Sum, as compared agaist the exact output, Sum, is also show i the figure. The iputs, a, b ad c, are modeled as radom variables with a kow distributio, ad the error ijected by the multiplier is deoted as Sum. Sice the iputs are biary, we represet their probability of beig as p a, p b ad p c, respectively. Similarly, p x = p x, x = a,b,c), are the probabilities of a, b ad c, respectively, to be. The PMF of the resultat sum Sum) combiig both the output bits, s ad c out, ad the PMF of the error Sum) i the resultat sum are defied by f Sum) ad f Sum), respectively. Sum= Sum + Sum c out a FA Sum= c out+ s s b c a b c Sum 3 Sum Sum - 3 Fig.. Full adder FA) with the associated truth table appx" from [6]). f Sum ) f Sum ) Fig. 3. Output sigal ad error distributio for the appx" adder from [6]. If the iputs are idepedet, ad represeted by a idetical uiform distributio p a=p b =p c=.5), the f Sum) ad f Sum) ca trivially be obtaied from the truth table, ad are depicted i the two plots i Fig. 3. For example, the PMF of Sum ca be computed by observig that it takes the value i six of eight etries i the truth table, ad the values ad i the remaiig two etries. Whe the iputs are equiprobable, this leads to the PMF show here. The PMFs i the figure ca equivaletly be represeted as a weighted sum of discrete Kroecker delta fuctios as: f Sum) = 6 δ)+ δ )+ δ+) ) f Sum) = δ)+ δ )+ 4 δ )+ δ 3) ) The coefficiets of the delta fuctios i ) ad ) are the PMF values of the associated radom variable Sum or Sum) ad are the legth of the stems i Fig. 3. Whe the iputs are ot equiprobable, the coefficiet of δ k) i the PMF of a radom variable is the probability of the variable to be k; hece, assumig the iputs to be idepedet, the coefficiets ca also be expressed as fuctios of p a, p b ad p c as show i Table I ad II. TABLE I PMF OF THE FA OUTPUT. f Sum ) p = p ap b p c +p ap b p c p = p a p b pc p = p ap b +p ap b pc +pap bp c 3 p 3 = p ap b p c TABLE II PMF OF THE ERRORS IN FA OUTPUT. f Sum ) - e = p ap b p c e = p ap b p c p ap b p c e = p a p bp c For a geeral approximate FA, Sum ca rage from 3 to 3, as the two output bits may have error of ay of, or although for the approx adder show i Fig., it oly rages from to ). Hece, the PMF of Sum ad Sum ca, i geeral, be expressed as a sum of Kroecker delta fuctios as: f Sum) = 3 i= 3eiδ i) 3) f Sum) = 3 i=piδ i) 4) where the p is ad e is are expressed as fuctios of p a, p b ad p c similar to Table I ad II, respectively, ad ca be computed by substitutig the values from the kowledge of the iput distributio. III. OVERVIEW OF THE FEMTO ALGORITHM Cosider a 4-bit 4-bit array multiplier with operads, A a 3a a a ) ad B b 3b b b ), as show i Fig. 4. The full adders i the array are each idexed as FA ij, where i correspods to the row umber, startig from the top, ad j to the positio of the FA i the row, startig from the least sigificat bit, as show i Fig. 4. The output of a sigle adder, FA ij, is modeled as the radom variable, Sum ij = Sum ij, + Sum ij, where Sum ij, is the true sum correspodig to a exact FA), ad Sum ij is the error due to the approximate additio, similar to the example of the FA i Fig.. Before proceedig further, let us commet o the iput data distributio, ad our assumptios regardig the correlatio betwee the various Sum ij radom variables described earlier. Although we assume the iputs, A ad B, to be idepedet radom variables, their distributio is a user-iput ad ca be ay arbitrary distributio) from which the sigal probability, p ai ad p bi, of each iput bit, a i ad b i, respectively, ca be iferred. I additio to the error PMF, FEMTO has the capability to produce the output PMF sigal probability of the output bits of the multiplier), which ca be used as iput sigal probability i subsequet multipliers withi a data flow graph. Thus FEMTO ca propagate the probability distributio of the data from iput to the output of the multiplier. Additioally, withi the multiplier, we cosider the correlatio betwee the s ad c out bits of ay adder by combiig them ito a two-bit output, Sum, ad the correspodig error, Sum, both expressed i decimal, with their PMF characterized by similar methods as Tables I ad II, respectively. This techique captures the most importat correlatio which is the iterdepedece of the two output bits of ay adder withi the

3 multiplier array. Although we igore the correlatios betwee the outputs of differet adders by cosiderig Sum ij to be idepedet radom variables, this assumptio does ot affect the quality of our results sice correlatios due to recoverget faout ted to be diluted as the logic depth of the recoverget faout paths icreases. Fidig the error PMF for the multiplier array ivolves three steps: ) determiig the iput probabilities for all iputs of each idividual FA ij, ad usig the approach i Sectio II to compute the PMF of Sum ij, ) fidig the PMF of the error, S i, itroduced by the i th row of the multiplier array, ad 3) fidig the PMF of the etire multiplier, i.e., the PMF of the sum of the S i variables over all rows, i. Step : The first step simply ivolves probability propagatio withi a Boolea etwork, ad we use established techiques for this purpose [7]. Based o this, we obtai the PMF of Sum ij, deoted by f Sumij ), as a sum of delta fuctios similar to 3). Sum ij = Sum ij, + Sum ij a 3 b 3 FA43 Sum 43 S i = Σ j j Sum ij ) Sum 33 a 3 b FA33 FA4 Sum 4 a b 3 a 3 b FA3 Sum 3 Sum 3 FA3 FA4 Sum 4 Sum 3 a b a b 3 R 7 R 6 R 5 R 4 R 3 R R R -bit fial result: product of A ad B a 3 b FA3 FA Sum Sum 3 S 4 FA3 a b Sum a b a b 3 S 3 a b FA FA Sum a b Sum a b S a b FA Fig. 4. Structure of a 4-bit 4-bit array multiplier. Step : Next, we determie the error i the partial product accumulatio, S i, i the i th row, which is the total error resultig from a array of N approximate FAs, as depicted i Fig. 4 for N = 4. For each row, i {,,N}, a simple aalysis yields: S i = N j= a b S a b i+j Sum ij 5) If, for simplicity, we cosider the Sum ij radom variables to be idepedet, we ca utilize the fact that the PMF of sum of idepedet radom variables equals the covolutio of the PMF of those radom variables. Hece the PMF of S i ca be expressed as: N f Si ) = f i+j Sum ij ) 6) j= where is the covolutio operator, applied here to covolve N operads, ad f i+j Sum ij ) is the PMF of the radom variable, i+j Sum ij. If the absolute value of the largest output error of FA ij is M e.g., M = for the appx" FA i Sectio II), the usig 3), M f i+j Sum ij ) = e k δ i+j k) 7) The assumptios are bore out by results. Step 3: The error, R, i the multiplier output is simply the sum of the errors, S i, over all N rows. Assumig the S i radom variables to be idepedet, we obtai the error PMF of the multiplier result, f R), by covolvig the f Si ) PMFs: N N N f R) = f Si ) = f i+j Sum ij ) ) i= i= j= We implemet the followig techiques to solve the above covolutio problem to obtai the PMF of error i the fial product: A. Use the Z-Trasform [] to covert the covolutio ito a friedlier multiplicatio i the frequecy domai, yieldig a polyomial i z. This polyomial ca have expoetial umber of terms, ad special techiques are required to maage the cost of workig i the trasform domai. B. Use the Iverse Fast Fourier Trasform IFFT) [] to ifer the PMF of R from the polyomial obtaied i the previous step. Next, we explai each of these techiques i detail. A. Represetig the covolutio usig the Z-Trasform Accordig to the priciples of trasform calculus, the Z-Trasform of a covolutio of multiple fuctios i the origial domai is equivalet to the product of the Z-Trasforms of those idividual fuctios i the trasform domai. Hece we ca represet F Rz), the Z-Trasform of f R) i ), as: F Rz) = N N i= j= F i+j Sum ij z) 9) where F i+j Sum ij z), is the Z-Trasform of the PMF, f i+j Sum ij ). Applyig the Z-Trasform to both sides of 7), F i+j Sum ij z) = M e k z i+j k Substitutig ) i 9), we ca rewrite F Rz) as: N N M ) F Rz) = e k z i+j k i= j= ) ) = z E a iz i ) i= = z E φz) 3) where R rages from E to E, with E = N )M derivatio of E is omitted due to space limitatios), ad the a is are the coefficiets of the polyomial i z, deoted by φz) i 3). Performig the Iverse Z-Trasform of ), f R) = i= a iδ+i E) 4) Hece a i is the probability of the error, R, to be i E). Thus fidig the PMF of the error reduces to the problem of fidig the coefficiets, a i, i φz) = E i= ai z ), i which is a polyomial of degree E with o-egative coefficiets. While this scheme presets a clear picture of our computatio scheme, the cost of a direct implemetatio of this idea is prohibitive. The most expesive step is the determiatio of the coefficiets, a i, by multiplyig the terms i ). Therefore, we develop a efficiet scheme for fidig the coefficiets, a i. 3

4 B. Usig the IFFT to ifer f R) from φz) ad F Rz) I this subsectio, we preset a method for efficietly computig the a i coefficiets i 4). So far we have worked i the Z-Trasform domai to formulate the error PMF equatio, F Rz). Let us ow cosider discrete Fourier domai to determie the coefficiets, a i, i φz) from 3), by usig their Fourier-Trasformed values followed by performig Iverse Fast Fourier Trasform IFFT). This iterchage of domais is possible sice, by defiitio, Z-Trasform is equivalet to Discrete Time Fourier Trasform DTFT) whe the magitude of z = []. We begi by observig that the DTFT of the sequece, {a,a,,a E}, is give by the Fourier coefficiets, A k = a iexp j πik ) = a izk i 5) E + i= i= ) where z k = exp j πk. It is iterestig to ote that the values E+ of z k are the reciprocal of the E +) th complex roots of uity. Therefore, if we take φz) i 3) ad substitute z = z k, for the reciprocal of each of the E + ) th complex roots of uity, we obtai the Fourier coefficiet, A k. I other words, A k = φz k ) = z E k N N i= j= M e k z i+j k k ) 6) This provides us with the discrete Fourier coefficiets of the sequece of a is, which are the obtaied by performig Iverse Discrete Time Fourier Trasform IDFT) of the A k values as: a i = E + k= A k exp j πik E + ) 7) To compute the IDFT i 7) efficietly, we use the Iverse Fast Fourier Trasform IFFT) to obtai the values of thea is. As explaied i the previous subsectio, obtaiig the a is directly provides the PMF of the error, R, i the multiplier output. IV. ENHANCING EFFICIENCY OF FEMTO The error PMF obtaied by the FEMTO algorithm provides probability of occurrece of errors with uit-graularity. I other words, we obtai f R) i 4), for each iteger value of withi the error rage, i.e., with uit spacig betwee successive values of. To ehace efficiecy, we propose to process the multiplicatio by partitioig each of the N-bit operads, A ad B, i a N-bit N-bit multiplier, ito K-bit slices. The product of A ad B is obtaied usig the results of K N/K-bit N/K-bit multipliers as show i Fig. 5. We call this the partitioed-graularity approach of obtaiig the PMFs. propagate probabilities N/K N/K N/K A K A A B K B B A B Multiplier # A B A B AMultiplier # A B A B K A B K A A K B K A A A K B A A N-bit product, R+ R Multiplier # A K B Multiplier # A B K Multiplier # A B K Multiplier # A K B K Fig. 5. N-bit N-bit multiplier from N/K-bit N/K-bit multipliers. We the process the computatio hierarchically. Istead of a FA, as i the previous sectio, we ow use a N/K-bit N/K-bit multiplier as the fudametal uit. However, while the PMF of a FA ca be exactly characterized through the truth table, this is ot the case for the N/K-bit N/K-bit multiplier; istead, we use the approach i Sectio III to obtai this PMF. Characterizig the PMF of the N/K-bit N/K-bit multiplier requires two types of iput data: the error distributio of the FAs, which is provided i Sectio II, ad the PMFs of the iputs to the multiplier, which is computed usig the probability propagatio algorithm i Step of Sectio III ote that these probabilities are cheap to compute, ad do ot chage whether we use this hierarchical scheme or the previous flat scheme). Give the PMF of the N/K-bit N/K-bit multiplier as the fudametal block, the scheme i Sectio III ca ow be used to fid the PMF of the multiplier error. Practical rutime ehacemet of FEMTO: The error rage, E K to E K E K N/K ), of the N/K-bit N/K-bit multiplier, ca be grouped or bied" ito P widows for further rutime ehacemet of FEMTO, where P is chose empirically. This idea is best explaied with a example i Fig. 6. If the output error i the N/K-bit N/K-bit multiplier is represeted by the radom variable, R, with E K = 5, ad the PMF of R is f R), the we ca group R ito P = 5 widows to obtai the bied versio of the PMF, f R,bi ) with fewer data poits. 3 f R ) 3 Bied ito five widows f R,bi ) Fig. 6. A error PMF ot to scale) with uit-graularity left) ad its bied versio ito five widows right). EK P There is a trade-off betwee the computatioal effort, ad the accuracy of the PMF) obtaied by this approach. While the algorithm speeds up by X, iaccuracy is itroduced due to the represetatio of E K P error values by a sigle value. Therefore, P should be chose depedig o the value of E K to maitai a acceptable rutime-accuracy trade-off. V. RESULTS We implemet FEMTO i MATLAB Rb i a.53 GHz Itel Core i3 CPU with 4Gb RAM ad -bit Widows 7 OS, ad preset the results relatig to approximate usiged multipliers. The approximate adders that costitute the multipliers are the various trasistor level approximatios of the mirror adders [6], the Boolea expressios of which are metioed i Table III for the two outputs, s ad c out, ad iputs, a, b ad c. TABLE III FIVE VERSIONS OF APPROXIMATE ADDERS FROM [6]. Approximate versio s c out appx ā bc+abc abc+ab c+a bc+ābc+āb c appx c out ab+ābc+a bc appx3 c out abc+ab c+a bc+ābc+āb c appx4 ā bc+ābc+abc a appx5 b a Sice i practice, o more tha 5% of the resultat bits are usually approximated to maitai accuracy [], [6], we use a similar strategy to approximate differet umber adders to implemet the 4

5 multipliers. We obtai the PMF of the errors ormalized to the dyamic rage of the output of the approximate multiplier. The ormalizatio factor, R, is the total rage differece of maximum ad miimum values) of the output whe the multiplier is implemeted usig differet combiatios of approximate ad accurate adders. The outputs are obtaied by performig Mote Carlo logic simulatios o the approximate multiplier. Such a ormalizatio step is ecessary sice the same magitude of error may have differet levels of severity depedig o the magitude of the product. First, we preset the results for the combiatio of approximate ad accurate adders to costruct the multipliers, such that exactly 5% of the product bits from the secod-least sigificat bit positio are approximate. Referrig to Fig. 4, this meas that for the 4 4 multiplier, the resultat bits, R,,R 4, are approximate ad the rest are exact. The least sigificat bit LSB), R, is exact sice it is ot produced by ay adder ad is simply the output of a AND gate. I geeral, for a N N multiplier, to approximate 5% of the LSBs i the product, N i LSB adders i the i th row of the adder array i each partial product accumulatio level should be approximate, with the rest beig accurate, for i =,,N. We implemet FEMTO o 6 6,, ad 6 6 approximate multipliers. While the error PMFs for 6 6 ad are obtaied by the uit-graularity approach, the error PMF for 6 6 multiplier is obtaied by the partitioed-graularity approach usig K =, i.e., usig the results of the multiplier, ad P = 3 widows to ehace the practical rutime, as explaied i Sectio IV. We compare the mea ad stadard deviatio of the error PMFs obtaied by FEMTO ad Mote Carlo simulatios usig the absolute value of the ormalized percetage error i mea ad stadard deviatio, µ orm ad σ orm, respectively, defied as: µ orm = σ orm = µfemto µmc R σfemto σmc R ) 9) where µ FEMTO µ MC) ad σ FEMTO σ MC) are the mea ad stadard deviatio of the error PMF of each multiplier obtaied by FEMTO Mote Carlo simulatio), respectively, ad R is the ormalizig factor defied earlier. We summarize the µ orm ad σ orm values, respectively, i Tables IV ad V, correspodig to the error PMFs of the 6 6,, ad 6 6 approximate multipliers with 5% of the product bits approximated). Clearly, the error is less tha % as observed by the µ orm ad σ orm values for all the approximate multipliers with differet versios of the approximate adders) cosidered here. This idicates that the error statistics obtaied by FEMTO are very similar to those obtaied by the Mote Carlo simulatios. TABLE IV NORMALIZED PERCENTAGE ERROR IN ESTIMATED MEAN µ orm) OF PMF OBTAINED BY FEMTO COMPARED AGAINST MONTE CARLO SIMULATION. Multiplier Adder appx.3.. appx appx appx4... appx5...6 TABLE V NORMALIZED PERCENTAGE ERROR IN ESTIMATED STANDARD DEVIATION σ orm) OF PMF OBTAINED BY FEMTO COMPARED AGAINST MONTE CARLO SIMULATION. CDF of ormalized error.5 Multiplier Adder appx..6.6 appx...6 appx appx appx True Estimated.5 9 bits.5.5 bits 7 bits a) appx b) appx bits bits 7 bits c) appx3 9 bits bits 7 bits bits.5 bits.5 7 bits bits.5 bits.5 7 bits Normalized error.5.5 d) appx4 e) appx5 Fig. 7. CDF of ormalized error for multipliers with differet percetages 45%, 5% ad 55%) of LSBs i the product beig approximate. The adders i a)-e) are the oes from Table III, with seve, eight ad ie bits 45%, 5% ad 55% of 6 bits) beig approximated i the product. Next, we cosider cases whe differet percetages 45%, 5% ad 55%) of LSBs are approximate i the product. Due to limited space, we oly preset the error CDFs of the multipliers as a example. Each colum of subplots i Fig. 7 correspods to a specific umber of approximate bits i the 6-bit product of the multiplier. The umbers, 7, ad 9 bits, respectively, correspod to 45%, 5% ad 55% of the 6-bits beig approximated. Each row of subplots i Fig. 7 correspods to the type of adders from Table III used to implemet the approximate multiplier. The blue plot labeled True" represets the CDF obtaied by Mote Carlo simulatios, ad is assumed to be the referece or golde CDF. The red plot labeled Estimated" is the CDF obtaied by FEMTO. As expected, the errors are reduced with fewer approximate bits i the product. Additioally, we observe that the PMFs obtaied by FEMTO are very close to those obtaied by Mote Carlo simulatio for differet levels of approximatio i the multiplier as see across each row of subplots i Fig. 7). Hece, for the various approximate multipliers cosidered here, FEMTO ca predict the error distributio with accuracy comparable to Mote Carlo simulatios. To compare with oe of the existig approaches of obtaiig error 5

6 PMF i approximate circuits, we also geerate the error PMF of the multipliers usig the modified iterval arithmetic MIA) based approach []. The authors of [] had reported MIA to be very efficiet i terms of rutime ad storage complexity. Hece we compare our approach with the MIA-based oe to obtai the error PMF. The multipliers are approximated such that 5% of the product LSBs are approximate, ad the rest are accurate. We compare the accuracy of the PMFs obtaied by both FEMTO ad MIA implemeted based o []), by observig the Helliger distace [9] from the correspodig PMFs obtaied from Mote Carlo simulatios. Helliger distace is a well-kow metric to compare probability distributios, ad is defied as: Helliger distace = allˆf) f) ) ) where ˆf) ad f) are the estimated ad the true Mote Carlo) PMFs, respectively. The factor,, esures that this distace rages from to. We plot the Helliger distaces of the error PMFs obtaied by FEMTO ad MIA for the 6 6 ad multipliers i Fig., from the PMFs obtaied by Mote Carlo simulatios. The smaller the distace, the closer is the estimate to the true PMF; thus clearly our approach yields more accurate PMFs compared to the MIA-based oes as see by the lower values of the Helliger distace for the approximate multipliers cosidered here. Helliger distace.7 6x6 multiplier FEMTO MIA appx appx appx3 appx4 appx5 Adder type i multiplier Helliger distace.7 x multiplier FEMTO MIA appx appx appx3 appx4 appx5 Adder type i multiplier Fig.. Helliger distace betwee Mote Carlo-geerated PMF, ad PMFs obtaied by FEMTO ad our implemetatio of MIA. The rutime to obtai the PMFs are summarized i Table VI. The 6 6 multiplier did ot fiish computatio withi 36 secods which was set as the maximum observatio time usig the MIAbased approach, hece its rutime is labeled timed out" i the table for all approximate versios of the adders. TABLE VI RUNTIME COMPARISON TO OBTAIN THE ERROR PMFS. Multiplier Adder FEMTO MIA FEMTO MIA FEMTO MIA appx.s 6.6s 4.5s 74.s 363.s timed out appx.7s 9.3s 4.s 65.s 3.6s timed out appx3.s 9.7s 3.9s 57.5s 365.3s timed out appx4.s 9.6s 4.4s 63.3s 369.9s timed out appx5.6s.s.9s 93.5s 36.5s timed out Clearly, ot oly is the accuracy of our method higher tha MIA, but also the rutime shows excellet improvemets. I coclusio, although MIA ca quatify the error PMFs, due to the above reasos of iaccuracy ad poor rutime, it has ot bee implemeted yet i ay multiplier desig. Our approach is thus superior to the existig approaches to quatify the error PMF, ad ca be icorporated ito the multiplier desig framework to speed up the performace evaluatio process. VI. CONCLUSION We have proposed a fast algorithm to aalytically obtai the error PMF i a usiged multiplier. The algorithm has bee implemeted to obtai error PMFs i differet types ad sizes of approximate multipliers comprisig of trasistor-level approximate adders. We have validated the results of our algorithm agaist Mote Carlo simulatios, i terms of the various statistics ad the error CDFs. The ease with which the PMF ca be obtaied will help approximate circuit desigers to use FEMTO i a optimizatio framework to evaluate the circuit performace, ad desig low power approximate systems withi a specified error tolerace. ACKNOWLEDGMENT This work was supported by the NSF grat CCF-777 ad CCF-667). REFERENCES [] J. Ha ad M. Orshasky, Approximate computig: A Emergig Paradigm For Eergy-Efficiet Desig, i Proc. ETS, pp. 6, 3. [] J. Miao, K. He, A. Gerstlauer, ad M. Orshasky, Modelig ad Sythesis of Quality-Eergy Optimal Approximate Adders, i Proc. ICCAD, pp ,. [3] N. Zhu, W. L. Goh, ad K. S. Yeo, A Ehaced Low-Power High- Speed Adder For Error-Tolerat Applicatio, i Proc. ISIC, pp. 69 7, 9. [4] Y. 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