P D Storage Temperature Range T stg - 65 to +150 C Case Operating Temperature T C 150 C

Transcription

1 echnical Data RF Power Field Effect ransistors N-Channel Enhancement-ode Lateral OSFEs Designed for class B PCN and PCS base station applications with frequencies from 1800 to 2000 Hz. Suitable for F, D, CD and multicarrier amplifier applications. CD 1990 Hz, 26 Volts IS-95 CD Pilot, Sync, Paging, raffic Codes 8 hru khz -47 dbc in 30 khz BW 1.25 Hz -55 dbc in 12.5 khz BW 2.25 Hz -55 dbc in 1 Hz BW Output Power 4.5 Watts vg. Power Gain 13.5 db Efficiency 17% Capable of Handling 10:1 26 Vdc, 1960 Hz, 30 Watts CW Output Power Features Internally atched for Ease of Use High Gain, High Efficiency and High Linearity Integrated ESD Protection Designed for aximum Gain and Insertion Phase Flatness Excellent hermal Stability Characterized with Series Equivalent Large- Signal Impedance Parameters Low Gold Plating hickness on Leads, 40μ Nominal. RoHS Compliant In ape and Reel. R3 Suffix = 250 Units per 32 mm, 13 Inch Reel. able 1. aximum Ratings Rating Symbol Value Unit Drain-Source Voltage V DSS -0.5, +65 Vdc Gate-Source Voltage V GS -0.5, +15 Vdc otal Device C = 25 C Derate above 25 C Document Number: RF19030 Rev. 12, 5/2006 RF19030LR3 RF19030LSR Hz, 30 W, 26 V LERL N- CHNNEL RF POWER OSFEs CSE 465E-04, SYLE 1 NI-400 RF19030LR3 CSE 465F-04, SYLE 1 NI-400S RF19030LSR3 P D Storage emperature Range stg - 65 to +150 C Case Operating emperature C 150 C W W/ C Operating Junction emperature J 200 C able 2. hermal Characteristics Characteristic Symbol Value Unit hermal Resistance, Junction to Case R θjc 2.1 C/W able 3. ESD Protection Characteristics est Conditions Class Human Body odel achine odel 2 (inimum) 3 (inimum), Inc., 2006, ll rights reserved. 1

2 able 4. Electrical Characteristics ( C = 25 C unless otherwise noted) Characteristic Symbol in yp ax Unit Off Characteristics Drain-Source Breakdown Voltage (V GS = 0 Vdc, I D = 20 μ) Zero Gate Voltage Drain Current (V DS = 28 Vdc, V GS = 0 Vdc) Gate-Source Leakage Current (V GS = 5 Vdc, V DS = 0 Vdc) On Characteristics Gate hreshold Voltage (V DS = 10 Vdc, I D = 100 μdc) V (BR)DSS 65 Vdc I DSS 1 μdc I GSS 1 μdc V GS(th) Vdc Gate Quiescent Voltage (V DS = 28 Vdc, I D = 300 m) Drain-Source On-Voltage (V GS = 10 Vdc, I D = 1 dc) Forward ransconductance (V DS = 10 Vdc, I D = 1 dc) Dynamic Characteristics Input Capacitance (Including Input atching Capacitor in Package) (1) (V DS = 26 Vdc, V GS = 0, f = 1 Hz) Output Capacitance (1) (V DS = 26 Vdc, V GS = 0, f = 1 Hz) Reverse ransfer Capacitance (V DS = 26 Vdc, V GS = 0, f = 1 Hz) Functional ests (In Freescale est Fixture, 50 ohm system) wo-one Common-Source mplifier Power Gain (V DD = 26 Vdc, P out = 30 W PEP, I DQ = 300 m, f1 = Hz, f2 = Hz) wo-one Drain Efficiency (V DD = 26 Vdc, P out = 30 W PEP, I DQ = 300 m, f1 = Hz, f2 = Hz) 3rd Order Intermodulation Distortion (V DD = 26 Vdc, P out = 30 W PEP, I DQ = 300 m, f1 = Hz, f2 = Hz) Input Return Loss (V DD = 26 Vdc, P out = 30 W PEP, I DQ = 300 m, f1 = Hz, f2 = Hz) wo-one Common-Source mplifier Power Gain (V DD = 26 Vdc, P out = 30 W PEP, I DQ = 300 m, f1 = Hz, f2 = Hz and f1 = Hz, f2 = Hz) wo-one Drain Efficiency (V DD = 26 Vdc, P out = 30 W PEP, I DQ = 300 m, f1 = Hz, f2 = Hz and f1 = Hz, f2 = Hz) 3rd Order Intermodulation Distortion (V DD = 26 Vdc, P out = 30 W PEP, I DQ = 300 m, f1 = Hz, f2 = Hz and f1 = Hz, f2 = Hz) Input Return Loss (V DD = 26 Vdc, P out = 30 W PEP, I DQ = 300 m, f1 = Hz, f2 = Hz and f1 = Hz, f2 = Hz) 1. Part is internally matched both on input and output. V GS(Q) Vdc V DS(on) Vdc g fs 2 S C iss 98.5 pf C oss 37 pf C rss 1.3 pf G ps 13 db η 36 % ID -31 dbc IRL -13 db G ps db η % ID dbc IRL db 2

3 V BIS B1 B2 R3 B3 B4 B5 V SUPPLY + C2 R1 R2 C3 C4 R4 C6 + C9 R5 C5 R6 R7 + C8 L2 L3 RF INPU Z1 L1 Z2 C1 DU B1 - B5 Short Ferrite Beads C1, C7 10 pf Chip Capacitors C2, C8 470 μf, 35 V Electrolytic Capacitors C3, C5 0.1 μf Chip Capacitors C4, C6 5.1 pf Chip Capacitors C9 22 μf antalum Chip Capacitor C pf Variable Capacitor, Johanson Gigatrim L1 - L nh Inductors R1 - R7 12 Ω Chip Resistors (0805) Z x icrostrip Z x icrostrip Z3 Z4 Z5 Figure 1. RF19030LR3(SR3) est Circuit Schematic Z6 Z7 C10 Z8 C7 RF OUPU Z x icrostrip Z x icrostrip Z x icrostrip Z x icrostrip Z x icrostrip Z x icrostrip Z x icrostrip Z x icrostrip Substrate x 3.00 x 5.00 Glass eflon, rlon Z9 L4 Z10 3

4 C2 C3 C5 C8 R1 B1 B2 R2 C4 R6 B4 R7 B5 R3 R4 L2 B3 R5 C9 L3 C6 L1 C1 C7 L4 Figure 2. RF19030LR3(SR3) est Circuit Component Layout C10 RF19030 Rev. 0 Freescale has begun the transition of marking Printed Circuit Boards (PCBs) with the signature/logo. PCBs may have either otorola or Freescale markings during the transition period. hese changes will have no impact on form, fit or function of the current product. 4

5 YPICL CHRCERISICS η, DRIN EFFICIENCY (%), G ps, POWER GIN (db) RCHIVE ID, INERODULION INFORION DISORION (dbc) G ps, POWER GIN (db) Figure 3. Class B Broadband Circuit Performance m P out, OUPU POWER (WS) PEP IRL V DD = 26 Vdc I DQ = 300 m, P out = 30 W (PEP) wo one easurement, 100 khz one Spacing Figure 5. Intermodulation Distortion versus Output Power 10 P out, OUPU POWER (WS) PEP η IRL, INPU REURN LOSS (db) ID, INERODULION DISORION (dbc) η, DRIN EFFICIENCY (%), G ps, POWER GIN (db) G ps 15 ID V DD = 26 Vdc I DQ = 350 m, f = 1960 Hz, Channel Spacing (Channel Bandwidth): 885 khz (30 khz), 1.25 Hz (12.5 khz), 2.25 Hz (1 Hz) 2.25 Hz 885 khz 1.25 Hz CD 9 Channels Forward PILO:0, PGING:1, RFFIC:8 13, SYNC: f, FREQUENCY (Hz) P out, OUPU POWER (WS vg.) CD V DD = 26 Vdc, f = 1960 Hz wo one easurement, 100 khz one Spacing 350 m 400 m 350 m 300 m 300 m 200 m 200 m 300 m 400 m V DD = 26 Vdc, f = 1960 Hz wo one easurement, 100 khz one Spacing ID, INERODULION DISORION (dbc) G ps, POWER GIN (db) Figure 4. CD CPR, Power Gain and Drain Efficiency versus Output Power V DD = 26 Vdc, I DQ = 300 m, f = 1960 Hz wo one easurement, 100 khz one Spacing 5th Order 10 P out, OUPU POWER (WS) PEP 3rd Order Figure 6. Intermodulation Distortion Products versus Output Power f = 1960 Hz I DQ = 300 m, P out = 30 W (PEP) wo one easurement, 100 khz one Spacing ID G ps V DD, DRIN VOLGE (VOLS) η G ps 7th Order DJCEN CHNNEL POWER RION (db) ID, INERODULION DISORION (dbc) Figure 7. Power Gain versus Output Power Figure 8. Power Gain and Intermodulation Distortion versus Supply Voltage 5

6 f = 1990 Hz f = 1990 Hz Z load f = 1930 Hz Z o = 25 Ω f Hz f = 1930 Hz Z source Ω Z source V DD = 26 V, I DQ = 300 m, P out = 30 W PEP j j j7.21 Z load Ω j j j4.35 Z source = est circuit impedance as measured from gate to ground. Z load = est circuit impedance as measured from drain to ground. Input atching Network Device Under est Output atching Network Z source Z load Figure 9. Series Equivalent Source and Load Impedance 6

7 PCKGE DIENSIONS ccc N (LID) aaa E SEE NOE 4 ccc aaa 2X K E 1 2 G 1 2 (INSULOR) 2X D bbb 2X K N (LID) C SEING PLNE (FLNGE) (INSULOR) 3 bbb H 2X D C B B SEING PLNE 2X bbb Q CSE 465E-04 ISSUE F NI-400 RF19030LR3 3 B (FLNGE) R (LID) ccc B ccc R (LID) S (INSULOR) aaa F S (INSULOR) aaa F H NOES: 1. CONROLLING DIENSION: INCH. 2. INERPRE DIENSIONS ND OLERNCES PER SE Y14.5, DIENSION H IS ESURED (0.762) WY FRO PCKGE BODY. 4. INFORION ONLY: CORNER BREK (4X) O BE.060±.005 (1.52±0.13) RDIUS OR.06±.005 (1.52±0.13) x 45 CHFER. INCHES ILLIEERS DI IN X IN X B C D E F G.600 BSC BSC H K N Q R S aaa.005 BSC BSC bbb.010 BSC BSC ccc.015 BSC BSC SYLE 1: PIN 1. DRIN 2. GE 3. SOURCE NOES: 1. CONROLLING DIENSION: INCH. 2. INERPRE DIENSIONS ND OLERNCES PER SE Y DIENSION H IS ESURED (0.762) WY FRO PCKGE BODY. INCHES ILLIEERS DI IN X IN X B C D E F H K N R S aaa.005 REF REF bbb.010 REF REF ccc.015 REF 0.38 REF SYLE 1: PIN 1. DRIN 2. GE 3. SOURCE CSE 465F-04 ISSUE E NI-400S RF19030LSR3 7

8 How to Reach Us: Home Page: US/Europe or Locations Not Listed: echnical Information Center, CH N. lma School Road Chandler, rizona or Europe, iddle East, and frica: Freescale Halbleiter Deutschland GmbH echnical Information Center Schatzbogen uenchen, Germany (English) (English) (German) (French) support@freescale.com Japan: Japan Ltd. Headquarters RCO ower 15F 1-8-1, Shimo-eguro, eguro-ku, okyo Japan or support.japan@freescale.com sia/pacific: Hong Kong Ltd. echnical Information Center 2 Dai King Street ai Po Industrial Estate ai Po, N.., Hong Kong support.asia@freescale.com For Literature Requests Only: Literature Distribution Center P.O. Box 5405 Denver, Colorado or Fax: LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use products. here are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. reserves the right to make changes without further notice to any products herein. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ypical parameters that may be provided in data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals, must be validated for each customer application by customer s technical experts. does not convey any license under its patent rights nor the rights of others. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should Buyer purchase or use products for any such unintended or unauthorized application, Buyer shall indemnify and hold and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale and the Freescale logo are trademarks of, Inc. ll other product or service names are the property of their respective owners., Inc. 2006, ll rights reserved. Document Number: RF Rev. 12, 5/2006