1.0 Folded-Cascode OTA

Transcription

1 1.0 Folded-Cascode OTA DD DD IL IB o bias M2 i M1 M2 bias o i M1 IL (a) Telescopic Cascode (b) Folded Cascode g m2 gs2 G1 D1 S2 D2 i g m1 i g ds1 g mb2 bs2 g ds2 g IL o S1 (c) Equivalent Circuit of Telescopic Cascode g m2 gs2 G1 D1 S2 D2 i g m1 i g ds1 g IB g mb2 bs2 g ds2 g IL o S1 (d) Equivalent Circuit of Folded Cascode 1

2 DD b1 i M1 M2 b2 o b3 M3 b4 M4 Folded Cascode With Cascode Load 2

3 MB1 T0 + dd2.5 MB2 MB3 b11.2 R* MB0 (Wp/Lp)/n T + T + n (m2) MB4 MB5 b20.53 MB5 MB4 (Wn/Ln)/n MB0 T + n (m3) T + MB1 b MB2 T0 + MB3 b ss-2.5 R*380k (external resistor, adjusted to achieve the desired bias voltages as shown) (Wn/Ln)(18L/6L) (Wn/Ln)/7(6L/14L) (Wp/Lp)(54L/6L) (Wp/Lp)/7(9L/7L) Where the divisor n7 3

4 dd2.5 b1 b2 M4 T + M3 M6 M5 M8 M7 + in - b3 M1 M1 M3 T + M2 M2 M5 M7 o b4 T0 + M4 *OTE: All transistors are 3 -terminal type (D,G,S) with MOS bulk (B) connected to SS, and MOS bulk (B) connected to DD M6 ss-2.5 (Wn/Ln)(18L/6L) (Wp/Lp)(54L/6L) M8 * Filename"wsotadc1.cir" * Wide-swing OTA * Simulation using subckt * MOS input stage > poor negative CMR * OTA inputs in 1 0 DC 0 Xwsota WSOTA.SUBCKT WSOTA in+ in- out * ower supplies DD vdd 0 DC 2.5 SS vss 0 DC -2.5 * WminLmin6 Lambda for linear analog circuit.aram Wn10.8U, Ln3.6U.ARAM Wp32.4U, Lp3.6U.ARAM Wn73.6U, Ln78.4U.ARAM Wp75.4U, Lp74.2U.ARAM IB10UA * Biasing Circuit to generates vb1, vb2, vb3, vb4 MB1 vb1 vb1 vdd vdd MOS1 W{Wp} L{Lp} 4

5 MB2 m1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB3 vb2 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB4 m3 m2 m1 vdd MOS1 W{Wp} L{Lp} MB5 vss m2 vb2 vb2 MOS1 W{Wp} L{Lp} MB0 m2 m2 vb1 vb1 MOS1 W{Wp7} L{Lp7} MB0 m3 m3 vb4 vss MOS1 W{Wn7} L{Ln7} MB1 vdd m3 vb3 vss MOS1 W{Wn} L{Ln} MB2 vb4 vb4 vss vss MOS1 W{Wn} L{Ln} MB3 vb3 vb4 vss vss MOS1 W{Wn} L{Ln} ISS m2 vss {IB} * Wide Swing OTA Implementation M1 n1 in+ n3 vss MOS1 W{Wn} L{Ln} M2 n2 in- n3 vss MOS1 W{Wn} L{Ln} M3 n3 vb3 n7 vss MOS1 W{Wn} L{Ln} M4 n7 vb4 vss vss MOS1 W{Wn} L{Ln} M5 n4 vb3 n5 vss MOS1 W{Wn} L{Ln} M7 out vb3 n6 vss MOS1 W{Wn} L{Ln} M6 n5 n4 vss vss MOS1 W{Wn} L{Ln} M8 n6 n4 vss vss MOS1 W{Wn} L{Ln} M6 n1 vb1 vdd vdd MOS1 W{Wp} L{Lp} M8 n2 vb1 vdd vdd MOS1 W{Wp} L{Lp} M5 n4 vb2 n1 vdd MOS1 W{Wp} L{Lp} M7 out vb2 n2 vdd MOS1 W{Wp} L{Lp}.EDS.MODEL MOS1 MOS TO1 K40U + GAMMA1.0 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS1 MOS TO-1 K15U + GAMMA0.6 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0200 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 * Analysis.DC in ROBE.ED 5

6 6

7 b1 T0 + M4 dd2.5 M6 M8 b2 T + M3 M5 M7 + in - b3 M1 M2 M5 M7 o b4 *OTE: All transistors are 3 -terminal type (D,G,S) with MOS bulk (B) connected to SS, and MOS bulk (B) connected to DD M6 ss-2.5 (Wn/Ln)(18L/6L) (Wp/Lp)(54L/6L) M8 * Filename"wsotadc2.cir" * Wide-swing OTA * Simulation using subckt * MOS input stage>poor positive input CMR * OTA inputs in 1 0 DC 0 Xwsota WSOTA *Xwsota WSOTA *S 3 0 DC 0.SUBCKT WSOTA in+ in- out * ower supplies DD vdd 0 DC 2.5 SS vss 0 DC -2.5 * WminLmin6 Lambda for linear analog circuit.aram Wn10.8U, Ln3.6U.ARAM Wp32.4U, Lp3.6U.ARAM Wn73.6U, Ln78.4U.ARAM Wp75.4U, Lp74.2U.ARAM IB10UA 7

8 * Biasing Circuit to generates vb1, vb2, vb3, vb4 MB1 vb1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB2 m1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB3 vb2 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB4 m3 m2 m1 vdd MOS1 W{Wp} L{Lp} MB5 vss m2 vb2 vb2 MOS1 W{Wp} L{Lp} MB0 m2 m2 vb1 vb1 MOS1 W{Wp7} L{Lp7} MB0 m3 m3 vb4 vss MOS1 W{Wn7} L{Ln7} MB1 vdd m3 vb3 vss MOS1 W{Wn} L{Ln} MB2 vb4 vb4 vss vss MOS1 W{Wn} L{Ln} MB3 vb3 vb4 vss vss MOS1 W{Wn} L{Ln} ISS m2 vss {IB} * Wide Swing OTA Implementation M5 n4 vb3 n5 vss MOS1 W{Wn} L{Ln} M7 out vb3 n6 vss MOS1 W{Wn} L{Ln} M6 n5 n4 vss vss MOS1 W{Wn} L{Ln} M8 n6 n4 vss vss MOS1 W{Wn} L{Ln} M6 n1 vb1 vdd vdd MOS1 W{Wp} L{Lp} M8 n2 vb1 vdd vdd MOS1 W{Wp} L{Lp} M5 n4 vb2 n1 vdd MOS1 W{Wp} L{Lp} M7 out vb2 n2 vdd MOS1 W{Wp} L{Lp} M1 n5 in+ n8 vdd MOS1 W{Wp} L{Lp} M2 n6 in- n8 vdd MOS1 W{Wp} L{Lp} M4 n9 vb1 vdd vdd MOS1 W{Wp} L{Lp} M3 n8 vb2 n9 vdd MOS1 W{Wp} L{Lp}.EDS.MODEL MOS1 MOS TO1 K40U + GAMMA1.0 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS1 MOS TO-1 K15U + GAMMA0.6 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0200 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 * Analysis.DC in ROBE.ED 8

9 2.0 Wide-Swing Folded-Cascode OTA The problem with differential amplifier with nmos input pair is that the positive CMR extends beyond DD, while the negative CMR is limited by the minimum voltage across the differential input. On the other hand the problem with differential amplifier with pmos input pair is that the positive CMR is limited by the minimum voltage across the differential input, while the negative CMR extend beyond SS. Figure 2 shows a wide-swing differential amplifier which extends the input CMR beyond the power supply rails by combining both the nmos and pmos input pairs differential amplifiers. The circuit utilized foldedcascode load to increase the output impedance to approach, the output impedance of ideal OTA. To increase the output impedance, (W/L)n3 and (W/L)p3*(W/L)n9 are chosen. To reduce the effect of length modulation (2*DL)1u, the minumum length L6u is chosen. Figure 1 shows the biasing circuit which generates the four biasing voltages for the wide-swing folded-cascode OTA. This biasing circuit has been discuss earlier. In the ideal case of ignoring the bulk effects, the ratio needed to achieve the desired biasing voltages is ¼. But with the bulk effects included this ratio needs to be adjusted to guarantee that a 1 current flows in M3, M4, M3, M4. Experimentation with the given circuit, the best ratio was found to be 1/7. The circuit was simulated to determine its specification: A 93,560 R o 1.095G G m A /R o 85.44u This transconductance value of 85.44u was used in all the examples, so that the response of both the ideal OTA and actual OTA implementations can be compared. The wide-swing characteristic is simulated by applying input ranging from 3.5v to 3.5v with a power rails of 2.5v and 2.5v.The wide swing characteristic is important when designing filter circuit with high Q in cascaded filter implementation, 1 Filenamewsota.doc 9

10 where the output of one stage is the input of the next stage. The high Q stage could easily drive the output voltage beyond the power rails. MB1 T0 + dd2.5 MB2 MB3 b1 MB0 (Wp/Lp)/n T + T + n (m2) MB4 MB5 b2 R MB5 MB4 (Wn/Ln)/n MB0 T + n (m3) T + MB1 b3 MB2 T0 + MB3 b4 ss-2.5 (Wn/Ln)(18L/6L) (Wn/Ln)/7(6L/14L) (Wp/Lp)(54L/6L) (Wp/Lp)/7(9L/7L) Where the divisor n7 Figure 1. Biasing circuit for the wide-swing folded-cascode OTA. 10

11 b1 b2 T0 + M4 T + M3 dd2.5 M6 M5 M8 M7 + in - b3 M1 M1 M3 T + M2 M2 M5 M7 o b4 T0 + M4 *OTE: All transistors are 3 -terminal type (D,G,S) with MOS bulk (B) connected to SS, and MOS bulk (B) connected to DD M6 ss-2.5 (Wn/Ln)(18L/6L) (Wp/Lp)(54L/6L) M8 Figure 2. Wide-swing folded-cascode OTA 11

12 Wide Swing OTA etlist Wide Swing Single Ended OTA Circuit * Filename "wsotatf.cir" * Wide-swing OTA * Simulation showing all components * WminLmin6 Lambda for linear analog circuit.aram Wn10.8U, Ln3.6U.ARAM Wp32.4U, Lp3.6U.ARAM Wn73.6U, Ln78.4U.ARAM Wp75.4U, Lp74.2U * ower supplies DD vdd 0 DC 2.5 SS vss 0 DC -2.5 * OTA inputs in in+ 0 DC 0 AC 1 b in- 0 DC 0 * Biasing Circuit to generates vb1, vb2, vb3, vb4 MB1 vb1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB2 m1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB3 vb2 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB4 m3 m2 m1 vdd MOS1 W{Wp} L{Lp} MB5 vss m2 vb2 vdd MOS1 W{Wp} L{Lp} MB0 m2 m2 vb1 vdd MOS1 W{Wp7} L{Lp7} MB0 m3 m3 vb4 vss MOS1 W{Wn7} L{Ln7} MB1 vdd m3 vb3 vss MOS1 W{Wn} L{Ln} MB2 vb4 vb4 vss vss MOS1 W{Wn} L{Ln} MB3 vb3 vb4 vss vss MOS1 W{Wn} L{Ln} ISS m2 vss * Wide Swing OTA Implementation M1 n1 in+ n3 vss MOS1 W{Wn} L{Ln} M2 n2 in- n3 vss MOS1 W{Wn} L{Ln} M5 n4 vb3 n5 vss MOS1 W{Wn} L{Ln} M7 3 vb3 n6 vss MOS1 W{Wn} L{Ln} M6 n5 n4 vss vss MOS1 W{Wn} L{Ln} M8 n6 n4 vss vss MOS1 W{Wn} L{Ln} M3 n3 vb3 n7 vss MOS1 W{Wn} L{Ln} M4 n7 vb4 vss vss MOS1 W{Wn} L{Ln} M6 n1 vb1 vdd vdd MOS1 W{Wp} L{Lp} M8 n2 vb1 vdd vdd MOS1 W{Wp} L{Lp} M5 n4 vb2 n1 vdd MOS1 W{Wp} L{Lp} M7 3 vb2 n2 vdd MOS1 W{Wp} L{Lp} M1 n5 in+ n8 vdd MOS1 W{Wp} L{Lp} M2 n6 in- n8 vdd MOS1 W{Wp} L{Lp} M4 n9 vb1 vdd vdd MOS1 W{Wp} L{Lp} M3 n8 vb2 n9 vdd MOS1 W{Wp} L{Lp}.MODEL MOS1 MOS TO1 K40U + GAMMA1.0 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS1 MOS TO-1 K15U + GAMMA0.6 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0200 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 * Analysis.AC DEC 10 1Hz 100MegHz.TF (3) in 12

13 .ROBE.O.ED OTA Frequency Response Theoretical gain calculation of the OTA At the operating point, the biasing currents are shown in Figure λ r r g g R R R g DS DS A m m (7) r (8) r (1) g (1) g O O O m λ g g R g m -g m m O (7)r (7)r //R (1) + g m λ R DS DS m m O (7) (8) (7) (7) O DS DS (7)r (7)r R R m 1 λi 1 λi 2β I 2β I O DSQ7 DSQ8 DS DS O (8) (8) R O + R DSQ DSQ O 1 (0.02)(5E - 6) 1 (0.02)(10E - 6) 2K 2K (W /L (W /L 10E6 (37.947E - 6)(10E6)(5E6) (40.249E - 6)(10E6)(5E6) (1.8935E9)( E9) 1.19E9 (1.8935E9) + ( E9) (1) (40.38E - 6 ) + (43.23E - 6) (83.61E - 6)(1.19E9) 9.9E4 p n 5E6 p n )I )I DSQ DSQ 2(40E - 6)(10.6/(3.6-1))(5E - 6) 2(15E - 6)(32.4/(3.6-1))(5E - 6) E E E - 6 The OTA is simulated, the results shown below are very closed to the calculated one E E

14 **** SMALL-SIGAL CHARACTERISTICS g A R (3)/in 9.356E+04 IUT RESISTACE AT in 1.000E+20 OUTUT RESISTACE AT (3) 1.095E E E9 m O 85.44µ OTA Transfer Characteristic * Filename"wsotadc.cir" * Wide-swing OTA * Simulation using subckt * OTA inputs in 1 0 DC 0 Xwsota WSOTA.SUBCKT WSOTA in+ in- out * ower supplies DD vdd 0 DC 2.5 SS vss 0 DC -2.5 * WminLmin6 Lambda for linear analog circuit.aram Wn10.8U, Ln3.6U.ARAM Wp32.4U, Lp3.6U.ARAM Wn73.6U, Ln78.4U.ARAM Wp75.4U, Lp74.2U.ARAM IB10UA * Biasing Circuit to generates vb1, vb2, vb3, vb4 MB1 vb1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB2 m1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB3 vb2 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB4 m3 m2 m1 vdd MOS1 W{Wp} L{Lp} MB5 vss m2 vb2 vb2 MOS1 W{Wp} L{Lp} MB0 m2 m2 vb1 vb1 MOS1 W{Wp7} L{Lp7} MB0 m3 m3 vb4 vss MOS1 W{Wn7} L{Ln7} MB1 vdd m3 vb3 vss MOS1 W{Wn} L{Ln} MB2 vb4 vb4 vss vss MOS1 W{Wn} L{Ln} MB3 vb3 vb4 vss vss MOS1 W{Wn} L{Ln} ISS m2 vss {IB} * Wide Swing OTA Implementation M1 n1 in+ n3 vss MOS1 W{Wn} L{Ln} M2 n2 in- n3 vss MOS1 W{Wn} L{Ln} M5 n4 vb3 n5 vss MOS1 W{Wn} L{Ln} M7 out vb3 n6 vss MOS1 W{Wn} L{Ln} M6 n5 n4 vss vss MOS1 W{Wn} L{Ln} M8 n6 n4 vss vss MOS1 W{Wn} L{Ln} M3 n3 vb3 n7 vss MOS1 W{Wn} L{Ln} M4 n7 vb4 vss vss MOS1 W{Wn} L{Ln} M6 n1 vb1 vdd vdd MOS1 W{Wp} L{Lp} M8 n2 vb1 vdd vdd MOS1 W{Wp} L{Lp} M5 n4 vb2 n1 vdd MOS1 W{Wp} L{Lp} M7 out vb2 n2 vdd MOS1 W{Wp} L{Lp} M1 n5 in+ n8 vdd MOS1 W{Wp} L{Lp} 14

15 M2 n6 in- n8 vdd MOS1 W{Wp} L{Lp} M4 n9 vb1 vdd vdd MOS1 W{Wp} L{Lp} M3 n8 vb2 n9 vdd MOS1 W{Wp} L{Lp}.EDS.MODEL MOS1 MOS TO1 K40U + GAMMA1.0 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS1 MOS TO-1 K15U + GAMMA0.6 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0200 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 * Analysis.DC in ROBE.ED Biasing The OTA Circuit The goal of the biasing circuit shown in Figure 11 is to generate the biasing voltages needed by the OTA circuit shown in Figure 12 so that the gate to source voltages of the four transistors M3, M4, M3, M4 are as shown.to generate the same current. That is, I D (3) I T D (4) I T0 D (3) I ( D T (4) ) ( T0 ) ; since T0 T0 Transistor M3 and M3 both have non-zero bulk to source voltage. Hence their threshold voltages increase. These values are computed as follows: 15

16 BS T BS T (3) (3) - (3) (3) (3) - (3) T0 T0 B + γ ( B γ ( φ S S φ + BS BS φ ) DD SS φ ) ( T0 ( T0 SS + γ ( DD + γ ( φ ) φ ) φ ) 1+ 1( φ ) 1 1( ) ) 1.19 The value of the biasing voltage can now be calculated from the OTA circuit. b4 b3 b2 b1 T0 T DD DD + T0 + + SS T ( 2.5) SS (0.34) + ( 2.5) DD + T ( ) ( 0.34) 0.82 The biasing circuit must determine the value of the divisor n to achieve the desired biasing voltages. b4 and b1 are satisfied by selecting the same transistor size as that of the OTA circuit. For b3 and b2, the value of n must be determined to achieve the biasing voltages. The voltage on the biasing circuit side is determined and equated to the corresponding required OTA bias voltage. This is illustrated as follows: n ( ) + n + b3 SS T0 Equating with corresponing equation in the OTA side, one obtains ( T0 + n 2) n T n + T0 T SS T T0 T + 2( ) SS T Similarly, b2 on both sides are equated to obtain n, this value should the same as that obtain for b3. T0 ss b2 DD + T0 + T + n - ( T ) DD + T0 + n Equating with corresponing equation in the OTA side, one obtains ( DD + n 2) n T T0 + n T0 T T0 DD + T + 2( ( 1) ) Figure 11 uses n7 in the final implementation. The circuit using the subckt netlist of OTA in wsotatf.cir is simulated to show the internal node voltages. These voltages are shown below: ODE OLTAGE ODE OLTAGE ODE OLTAGE ODE OLTAGE 16

17 ( 3) ( m1) ( m2) ( m3) ( n1) ( n2) ( n3) ( n4) ( n5) ( n6) ( n7) ( n8) ( n9) ( in+) ( in-) ( vb1) ( vb2).7197 ( vb3) ( vb4) ( vdd) ( vss) The desired and actual biasing voltages are compared in the following table: Biasing oltage Desired alue Actual alue with n7 b b b b i - I1 G 1 m1 + + C1 G m2 - I2 o C (a) Ftype L i 0 0 H 0 0 i B 0 i 0 BR i 0 i (b) Actual 2 OTAs Circuit Implementation etlist *Filename "univ2_a2.cir" *Biquad 2nd order filter. fo100k 17

18 in 1 0 DC 0 AC 1 *L *Xs2flt S2FLT *H *Xs2flt S2FLT *B *Xs2flt S2FLT *BR Xs2flt S2FLT.SUBCKT S2FLT v1 v2 v3 v0.aram C135.98pF.ARAM Q Xota1 v1 v0 n2 WSOTA Xota2 n2 v0 v0 WSOTA C1 n2 v2 {C/Q} IC0 C2 v0 v3 {Q*C} IC0.EDS.SUBCKT WSOTA in+ in- out * ower supplies DD vdd 0 DC 2.5 SS vss 0 DC -2.5 * WminLmin6 Lambda for linear analog circuit.aram Wn10.8U, Ln3.6U.ARAM Wp32.4U, Lp3.6U.ARAM Wn73.6U, Ln78.4U.ARAM Wp75.4U, Lp74.2U.ARAM IB10UA * Biasing Circuit to generates vb1, vb2, vb3, vb4 MB1 vb1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB2 m1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB3 vb2 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB4 m3 m2 m1 vdd MOS1 W{Wp} L{Lp} MB5 vss m2 vb2 vb2 MOS1 W{Wp} L{Lp} MB0 m2 m2 vb1 vb1 MOS1 W{Wp7} L{Lp7} MB0 m3 m3 vb4 vss MOS1 W{Wn7} L{Ln7} MB1 vdd m3 vb3 vss MOS1 W{Wn} L{Ln} MB2 vb4 vb4 vss vss MOS1 W{Wn} L{Ln} MB3 vb3 vb4 vss vss MOS1 W{Wn} L{Ln} ISS m2 vss {IB} * Wide Swing OTA Implementation M1 n1 in+ n3 vss MOS1 W{Wn} L{Ln} M2 n2 in- n3 vss MOS1 W{Wn} L{Ln} M5 n4 vb3 n5 vss MOS1 W{Wn} L{Ln} M7 out vb3 n6 vss MOS1 W{Wn} L{Ln} M6 n5 n4 vss vss MOS1 W{Wn} L{Ln} M8 n6 n4 vss vss MOS1 W{Wn} L{Ln} M3 n3 vb3 n7 vss MOS1 W{Wn} L{Ln} M4 n7 vb4 vss vss MOS1 W{Wn} L{Ln} M6 n1 vb1 vdd vdd MOS1 W{Wp} L{Lp} M8 n2 vb1 vdd vdd MOS1 W{Wp} L{Lp} M5 n4 vb2 n1 vdd MOS1 W{Wp} L{Lp} M7 out vb2 n2 vdd MOS1 W{Wp} L{Lp} M1 n5 in+ n8 vdd MOS1 W{Wp} L{Lp} M2 n6 in- n8 vdd MOS1 W{Wp} L{Lp} M4 n9 vb1 vdd vdd MOS1 W{Wp} L{Lp} M3 n8 vb2 n9 vdd MOS1 W{Wp} L{Lp} 18

19 .EDS.MODEL MOS1 MOS TO1 K40U + GAMMA1.0 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS1 MOS TO-1 K15U + GAMMA0.6 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0200 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 * Analysis.AC DEC 100 1Hz 100MegHz.ROBE.ED i - G m1 + + C 1 G m2 - C 2 - G m3 + o (a) Ftype L i 0 0 H 0 i 0 B 0 0 i BR i i 0 (b) Actual 3 OTAs Circuit Implementation etlist *Filename "univ2_a3.cir" *Biquad 2nd order filter. fo100k in 1 0 DC 0 AC 1 *L *Xs3flt S3FLT *H *Xs3flt S3FLT *B *Xs3flt S3FLT *BR Xs3flt S3FLT.SUBCKT S3FLT v1 v2 v3 v0 19

20 .ARAM C135.98pF Xota1 v1 v0 n2 WSOTA Xota2 n2 0 v0 WSOTA Xota3 v3 v0 v0 WSOTA1 C1 n2 0 {C} IC0 C2 v0 v2 {C} IC0.EDS.SUBCKT WSOTA in+ in- out * ower supplies DD vdd 0 DC 2.5 SS vss 0 DC -2.5 * WminLmin6 Lambda for linear analog circuit.aram Wn10.8U, Ln3.6U.ARAM Wp32.4U, Lp3.6U.ARAM Wn73.6U, Ln78.4U.ARAM Wp75.4U, Lp74.2U.ARAM IB10UA * Biasing Circuit to generates vb1, vb2, vb3, vb4 MB1 vb1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB2 m1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB3 vb2 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB4 m3 m2 m1 vdd MOS1 W{Wp} L{Lp} MB5 vss m2 vb2 vb2 MOS1 W{Wp} L{Lp} MB0 m2 m2 vb1 vb1 MOS1 W{Wp7} L{Lp7} MB0 m3 m3 vb4 vss MOS1 W{Wn7} L{Ln7} MB1 vdd m3 vb3 vss MOS1 W{Wn} L{Ln} MB2 vb4 vb4 vss vss MOS1 W{Wn} L{Ln} MB3 vb3 vb4 vss vss MOS1 W{Wn} L{Ln} ISS m2 vss {IB} * Wide Swing OTA Implementation M1 n1 in+ n3 vss MOS1 W{Wn} L{Ln} M2 n2 in- n3 vss MOS1 W{Wn} L{Ln} M5 n4 vb3 n5 vss MOS1 W{Wn} L{Ln} M7 out vb3 n6 vss MOS1 W{Wn} L{Ln} M6 n5 n4 vss vss MOS1 W{Wn} L{Ln} M8 n6 n4 vss vss MOS1 W{Wn} L{Ln} M3 n3 vb3 n7 vss MOS1 W{Wn} L{Ln} M4 n7 vb4 vss vss MOS1 W{Wn} L{Ln} M6 n1 vb1 vdd vdd MOS1 W{Wp} L{Lp} M8 n2 vb1 vdd vdd MOS1 W{Wp} L{Lp} M5 n4 vb2 n1 vdd MOS1 W{Wp} L{Lp} M7 out vb2 n2 vdd MOS1 W{Wp} L{Lp} M1 n5 in+ n8 vdd MOS1 W{Wp} L{Lp} M2 n6 in- n8 vdd MOS1 W{Wp} L{Lp} M4 n9 vb1 vdd vdd MOS1 W{Wp} L{Lp} M3 n8 vb2 n9 vdd MOS1 W{Wp} L{Lp}.EDS.SUBCKT WSOTA1 in+ in- out * ower supplies DD vdd 0 DC 2.5 SS vss 0 DC -2.5 * WminLmin6 Lambda for linear analog circuit.aram Wn10.8U, Ln3.6U.ARAM Wp32.4U, Lp3.6U.ARAM Wn73.6U, Ln78.4U.ARAM Wp75.4U, Lp74.2U.ARAM IB3.8UA 20

21 * Biasing Circuit to generates vb1, vb2, vb3, vb4 MB1 vb1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB2 m1 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB3 vb2 vb1 vdd vdd MOS1 W{Wp} L{Lp} MB4 m3 m2 m1 vdd MOS1 W{Wp} L{Lp} MB5 vss m2 vb2 vb2 MOS1 W{Wp} L{Lp} MB0 m2 m2 vb1 vb1 MOS1 W{Wp7} L{Lp7} MB0 m3 m3 vb4 vss MOS1 W{Wn7} L{Ln7} MB1 vdd m3 vb3 vss MOS1 W{Wn} L{Ln} MB2 vb4 vb4 vss vss MOS1 W{Wn} L{Ln} MB3 vb3 vb4 vss vss MOS1 W{Wn} L{Ln} ISS m2 vss {IB} * Wide Swing OTA Implementation M1 n1 in+ n3 vss MOS1 W{Wn} L{Ln} M2 n2 in- n3 vss MOS1 W{Wn} L{Ln} M5 n4 vb3 n5 vss MOS1 W{Wn} L{Ln} M7 out vb3 n6 vss MOS1 W{Wn} L{Ln} M6 n5 n4 vss vss MOS1 W{Wn} L{Ln} M8 n6 n4 vss vss MOS1 W{Wn} L{Ln} M3 n3 vb3 n7 vss MOS1 W{Wn} L{Ln} M4 n7 vb4 vss vss MOS1 W{Wn} L{Ln} M6 n1 vb1 vdd vdd MOS1 W{Wp} L{Lp} M8 n2 vb1 vdd vdd MOS1 W{Wp} L{Lp} M5 n4 vb2 n1 vdd MOS1 W{Wp} L{Lp} M7 out vb2 n2 vdd MOS1 W{Wp} L{Lp} M1 n5 in+ n8 vdd MOS1 W{Wp} L{Lp} M2 n6 in- n8 vdd MOS1 W{Wp} L{Lp} M4 n9 vb1 vdd vdd MOS1 W{Wp} L{Lp} M3 n8 vb2 n9 vdd MOS1 W{Wp} L{Lp}.EDS.MODEL MOS1 MOS TO1 K40U + GAMMA1.0 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0550 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9.MODEL MOS1 MOS TO-1 K15U + GAMMA0.6 LAMBDA0.02 HI0.6 + TOX0.05U LD0.5U CJ5E-4 CJSW10E-10 + U0200 MJ0.5 MJSW0.5 CGSO0.4E-9 CGDO0.4E-9 * Analysis.AC DEC 100 1Hz 100MegHz.ROBE.ED Frequency Response of Actual OTA Circuit Implementation 21

22 Implemented Second Order Lowpass Filter Response Implemented Second Order Highpass Filter Response 22

23 Implemented Second Order Bandpass Response Implemented Second Order Bandreject Response 23