Microelectronics Circuit Analysis and Design. MOS Capacitor Under Bias: Electric Field and Charge. Basic Structure of MOS Capacitor 9/2/2013
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1 Micrelectrics Circuit Aalysis ad Desig Dald A. Neae Chapter 3 The Field Effect Trasistr I this chapter, we will: Study ad uderstad the perati ad characteristics f the varius types f MOSFETs. Uderstad ad bece failiar with the dc aalysis ad desig techiques f MOSFET circuits. Exaie three applicatis f MOSFET circuits. Ivestigate curret surce biasig f MOSFET circuits, such as thse used i itegrated circuits. Aalyze the dc biasig f ultistage r ultitrasistr circuits. Neae Micrelectrics, 4e Chapter 3-1 Neae Micrelectrics, 4e Chapter 3-2 Basic Structure f MOS Capacitr MOS Capacitr Uder Bias: Electric Field ad Charge Parallel plate capacitr Negative gate bias: Hles attracted t gate Neae Micrelectrics, 4e Chapter 3-3 Neae Micrelectrics, 4e Chapter 3-4 1
2 Scheatic f -Chael Ehaceet Mde MOSFET Basic Trasistr Operati Befre electr iversi layer is fred After electr iversi layer is fred Neae Micrelectrics, 4e Chapter 3-5 Neae Micrelectrics, 4e Chapter 3-6 Curret Versus Vltage Characteristics: Ehaceet-Mde MOSFET Faily f i D Versus v DS Curves: Ehaceet-Mde MOSFET Neae Micrelectrics, 4e Chapter 3-7 Neae Micrelectrics, 4e Chapter 3-8 2
3 p-chael Ehaceet-Mde MOSFET Sybls fr -Chael Ehaceet-Mde MOSFET Neae Micrelectrics, 4e Chapter 3-9 Neae Micrelectrics, 4e Chapter 3-10 Sybls fr p-chael Ehaceet-Mde MOSFET -Chael Depleti-Mde MOSFET Neae Micrelectrics, 4e Chapter 3-11 Neae Micrelectrics, 4e Chapter
4 Faily f i D Versus v DS Curves: Depleti-Mde MOSFET p-chael Depleti- Mde MOSFET Sybls Neae Micrelectrics, 4e Chapter 3-13 Sybls Neae Micrelectrics, 4e Chapter 3-14 Suary f I-V Relatiships Regi NMOS PMOS Nsaturati v DS <v DS (sat) v SD <v SD (sat) 2 2 i K [2( v V ) v v ] i K [2( v + V ) v v ] D GS TN DS DS D p SG TP SD SD NMOSFET Cducti Paraeters K Wµ C 2L x k ' W 2L Saturati v DS >v DS (sat) v SD >v SD (sat) i D K [ vgs VTN 2 ] i K [ v + VTP ] D p SG 2 PMOSFET K p Wµ pc 2L x k ' p W 2L Trasiti Pt. v DS (sat) v GS - V TN v SD (sat) v SG + V TP Ehaceet Mde Depleti Mde V TN > 0V V TN < 0V V TP < 0V V TP > 0V where: C x ε t x Neae Micrelectrics, 4e Chapter 3-15 Neae Micrelectrics, 4e Chapter
5 MOS Circuits Prble-Slvig Techique: NMOSFET DC Aalysis 1. Assue the trasistr is i saturati. a. V GS > V TN, I D > 0, & V DS V DS (sat) 2. Aalyze circuit usig saturati I-V relatis. 3. Evaluate resultig bias cditi f trasistr. a. If V GS < V TN, trasistr is likely i cutff b. If V DS < V DS (sat), trasistr is likely i saturati regi 4. If iitial assupti is prve icrrect, ake ew assupti ad repeat Steps 2 ad 3. Neae Micrelectrics, 4e Chapter 3-17 Neae Micrelectrics, 4e Chapter 3-18 NMOS C-Surce Circuit PMOS C-Surce Circuit Neae Micrelectrics, 4e Chapter 3-19 Neae Micrelectrics, 4e Chapter
6 Lad Lie ad Mdes f Operati: NMOS C-Surce Circuit MOS Sall-Sigal Aplifier Neae Micrelectrics, 4e Chapter 3-21 Neae Micrelectrics, 4e Chapter 3-22 Micrelectrics Circuit Aalysis ad Desig NMOS C-Surce Circuit Dald A. Neae Chapter 4 Basic FET Aplifiers Neae Micrelectrics, 4e Chapter 3-23 Neae Micrelectrics, 4e Chapter
7 NMOS Trasistr Sall-Sigal Paraeters Siple NMOS Sall-Sigal Equivalet Circuit Values depeds Q-pit g g id vgs 2K r ( id vds r [ λk i v ) ( V 1 ( V d gs GSQ GSQ V V TN ) 2 ) ] 2 1 TN K I [ λi DQ ] 1 DQ Neae Micrelectrics, 4e Chapter 3-25 Neae Micrelectrics, 4e Chapter 3-26 Chael Legth Mdulati: Early Vltage NMOS C-Surce Circuit AC Sall-sigal A V v V i g ( r RD ) Neae Micrelectrics, 4e Chapter 3-27 Neae Micrelectrics, 4e Chapter
8 Prble-Slvig Techique: MOSFET AC Aalysis 1. Aalyze circuit with ly the dc surces t fid quiescet sluti. Trasistr ust be biased i saturati regi fr liear aplifier. 2. Replace eleets with sall-sigal del. 3. Aalyze sall-sigal equivalet circuit, settig dc surces t zer, t prduce the circuit t the tie-varyig iput sigals ly. C-Surce Cfigurati DC aalysis: Cuplig capacitr is assued t be pe. AC aalysis: Cuplig capacitr is assued t be a shrt. DC vltage supply is set t zer vlts. Neae Micrelectrics, 4e Chapter 3-29 Neae Micrelectrics, 4e Chapter 3-30 Sall-Sigal Equivalet Circuit DC Lad Lie Q-pit ear the iddle f the saturati regi fr axiu syetrical utput vltage swig,. A V v V g i ( r RD )( R i Ri + R Si ) Sall AC iput sigal fr utput respse t be liear. Neae Micrelectrics, 4e Chapter 3-31 Neae Micrelectrics, 4e Chapter
9 C-Surce Aplifier with Surce Resistr Sall-Sigal Equivalet Circuit fr C-Surce with Surce Resistr grd Av 1 + g R S Neae Micrelectrics, 4e Chapter 3-33 Neae Micrelectrics, 4e Chapter 3-34 C-Surce Aplifier with Bypass Capacitr NMOS Surce-Fllwer r C Drai Aplifier Sall-sigal equivalet circuit Neae Micrelectrics, 4e Chapter 3-35 Neae Micrelectrics, 4e Chapter
10 Sall-Sigal Equivalet Circuit fr Surce Fllwer Deteriig Output Ipedace NMOS Surce Fllwer A v Ri ( R + R S 1 + RS r i Si g R r ) R O 1 g R S r Neae Micrelectrics, 4e Chapter 3-37 Neae Micrelectrics, 4e Chapter 3-38 Cparis f 3 Basic Aplifiers Cfigurati Vltage Gai Curret Gai Iput Resistace Output Resistace C Surce A v > 1 R TH Mderate t high Surce Fllwer A v 1 R TH Lw C Gate A v > 1 A i 1 Lw Mderate t high Neae Micrelectrics, 4e Chapter
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