FET Biasing. Electronic Circuit Design ME /8/2013. Spring Chapter 2. Chapter Contents. Course Support

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1 Spring Chapter 2 ME-2401 Electronic Circuit Design 4 th Semester (Mechatronics) SZABIST, Karachi 3 Chapter Contents 4 Course Support humera.rafique@szabist.edu.pk Office: 100 Campus (404) Ext. (120) Official: ZABdesk Fixed biased Self biased Voltage Divider Common Gate Configurations of D-MOSs Configurations of E-MOSs p-channel configurations Practical Applications Computer Analysis 1

2 5 Amplifier Device Analysis: Introduction 6 DC Bias Introduction AC signal Amplifier DC analysis: DC Bias analysis (AC suppressed) Output (Amplified) AC analysis: AC input signal analysis (DC Suppressed) Hybrid analysis: AC & DC Common J Circuits: Introduction 7 Basic Current Relationships: Introduction 8 J Circuits Fixed Bias Self-Bias Voltage-Divider Bias For all s: 0 D-Type MOS Circuits For JS and D-Type MOSs: Self-Bias Voltage-Divider Bias E-Type MOS Circuits Feedback Configuration Voltage-Divider Bias For E-Type MOSs: 1 2

3 9 10 J Configurations Fixed Biased J Fixed Bias: Coupling capacitors (Open for DC & short for AC) Fixed Biased 11 J Fixed Bias: Fixed Biased

4 Fixed Biased 13 Fixed Biased 14 Quiescent Point: Finding Quiescent Point in Lab: Plotting Shockley s equation Finding the solution for the fixed-bias configuration Measuring the quiescent values of I D and V GS Fixed Biased 15 Fixed Biased 16 Example 7-1: Determine the following: Example 7-1: 4

5 Fixed Biased 17 Fixed Biased 18 Example 7-1: Computer Analysis Example 7-1: Computer Analysis ID (ma) example 7-1 X: -2 Y: % J DC Configurations % Fixed bias % Example 7-1 Boylestad RD = 2000; VGG= 2; VDD = 16; IDSS = 10/1000; Vp = -8; VGS = Vp:0.1:0; ID = IDSS*(1-VGS/Vp).^2; plot(vgs,id), grid on, title('example 7-1'), xlabel('vgs(v)'), ylabel('id (ma)') % Fixed bias line hold, plot(-vgg,id,'*') VGS (V) 19 Self Bias 20 J: Self Biased Self Bias 5

6 DC Analysis: Self Bias 21 Calculations: For the indicated loop, Self Bias 22 To solve this equation: Select an I D < I DSS and use the component value of R S to calculate V GS Plot the point identified by I D and V GS. Draw a line from the origin of the axis to this point. Plot the transfer curve using I DSS and V P (V P = V GSoff in specification sheets) and a few points such as I D = I DSS / 4 and I D = I DSS / 2 etc. The Q-point is located where the first line intersects the transfer curve. Use the value of I D at the Q-point (I DQ ) to solve for the other voltages: Self Bias 23 Self Bias 24 Calculations: Calculations: 6

7 Self Bias 25 Self Bias 26 Example 7-2: Determine the following: Example 7-2: Self Bias 27 Self Bias 28 Example 7-2: Example 7-2: 7

8 Self Bias 29 Self Bias 30 Example 7-2: Computer Analysis Example 7-2: Computer Analysis 8 x 10-3 Example 7-2 %% EXAMPLE 7-2 % Self Bias Configuration ID (ma) X: Y: RD = 3300; Rs=1000; IDSS= 8/1000; Vp= -6; VDD= 20; VGS = Vp:0.001:0; ID = IDSS*(1-VGS/Vp).^2; plot(vgs,id), grid on, title('example 7-2'), xlabel('vgs(v)'), ylabel('id (ma)') % self bias line calculations VGS (V) Vgs = -ID*Rs; hold, plot(vgs, ID,'r.-') Self Bias 31 Self Bias 32 Example 7-3: Example 7-3: Computer Analysis Find the quiescent point for the given network: (Example 7.2) Find the quiescent point for the given network: (Example 7.2) %% EXAMPLE 7-3 % Self Bias Configuration RD = 3300; IDSS = 8/1000; Vp = -6; VDD = 20; VGS = Vp:0.001:0; ID = IDSS*(1-VGS/Vp).^2; plot(vgs,id), grid on, title('example 7-3'), xlabel('vgs (V)'), ylabel('id (ma)') % self bias line calculations for Rs = 100 Ohms Rs=100; Vgs = -ID*Rs; hold, plot(vgs, ID,'r.-') % self bias line calculations for Rs = 10k Ohms Rs= 10000; Vgs = -ID*Rs; plot(vgs, ID,'m.-') 8

9 Example 7-3: Computer Analysis Find the quiescent point for the given network: (Example 7.2) Self Bias x 10-3 Example 7-3 ID (ma) X: Y: Voltage Divider Bias VGS (V) VDB: I G = 0 A Voltage Divider Bias 35 VDB: V G is equal to the voltage across divider resistor R 2 : Voltage Divider Bias 36 I D responds to changes in V GS ; Using Kirchhoff s Law: The Q point is established by plotting a line that intersects the transfer curve. 9

10 Voltage Divider Bias 37 Voltage Divider Bias 38 VDB: VDB Q-point: I G = 0 A and I D responds to changes in V GS Using the value of I D at the Q-point, solve for the other variables in the voltage-divider bias circuit: ; Step 1 Plot the line by plotting two points: V GS = V G, I D = 0 A V GS = 0 V, I D = V G / R S Step 2 Plot the transfer curve by plotting I DSS, V P and the calculated values of I D Step 3 The Q-point is located where the line intersects the transfer curve Voltage Divider Bias 39 Voltage Divider Bias 40 Effect of increasing R S : Example 7-5: For the given network, find: a. I DQ and V GSQ b. V D and V S c. V DS and V DG 10

11 Voltage Divider Bias 41 Voltage Divider Bias 42 Example 7-5: Example 7-5: %% EXAMPLE 7-5 % Voltage Divider Bias Configuration R1 = 2.1*10^6; R2 = 270*10^3; RD = 2400; IDSS = 8/1000; Vp = -4; VDD = 16; VGS = Vp:0.1:0; ID = IDSS*(1-VGS/Vp).^2; plot(vgs,id), grid on, title('example 7-5'), xlabel('vgs (V)') ylabel('id (A)') 8 x X: -8 Y: Example 7-5 % Load line (Voltage Divider Bias) calculations % Rs= 1.5k Ohms ID (A) 4 3 X: Y: Rs=1500; Vg = VDD*R2/(R1+R2); Vgs= Vg-(ID*Rs); hold, plot(vgs, ID,'r.-') 2 1 X: e-005 Y: VGS (V) X: Y: 0 Practive 43 Practive 44 Problem 1 & 2: Problem 3 & 6: 11

12 Practive Problem 12 & 14: Common Gate Configuration Common Gate Configuration 47 Common Gate Configuration 48 Common Gate: Common Gate: I V V 12

13 Example 7-4: Determine the following: I DQ, V GSQ, V DS, V D and V S : Common Gate Configuration 49 Example 7-6: Common Gate Configuration 50 Determine the following: (R D = 1.5 kω, R S = 680 Ω, V DD = 12 V) Example 7-6: Common Gate Configuration 51 Special Case: V GSQ = 0 V: Common Gate Configuration 52 %% EXAMPLE 7-6: % Common Gate Configuration RD = 1500; IDSS = 12/1000; Vp = -6; VDD = 12; VGS = Vp:0.1:0; ID = IDSS*(1-VGS/Vp).^2; plot(vgs,id), grid on, title('example 7-6'), xlabel('vgs (V)') ylabel('id (A)') Example 7-6 I V % Load line (Common Gate) calculations for % Rs = 680 Ohms Rs=680; Vss = 0; Vgs= Vss-(ID*Rs); hold, plot(vgs, ID,'r.-') ID (A) X: Y: X: Y: X: 0 Y: 0 V VGS (V) 13

14 53 D-MOSs 54 Configurations: 1. Voltage Divider 2. Self Bias 3. Common Gate Special Case D-MOS Configurations 55 D-MOSs 56 Voltage Divider Bias Voltage Divider Bias: Example 7-7: Determine the following: a. Q-point b. V DS 14

D-MOSs 57 58 Example 7-8: Determine the following: (Data of Ex.

15 D-MOSs Example 7-8: Determine the following: (Data of Ex. 7-7, R S = 150Ω) Self Bias Self Bias: Example 7-9: D-MOSs 59 Determine the following, if R D = 6.2 k, R S = 2.4 k, I DSS = 8mA and V P = 8V. Common Gate (Special case): Example 7-10: Determine V DS for the following network: D-MOSs 60 15

16 61 E-MOSs 62 Configurations: 1. Feedback Arrangement 2. Voltage Divider Arrangement E-MOS Configurations 63 E-MOSs 64 The transfer characteristic for the e-type MOS is very different from that of a simple J or the d-type MOS. Feedback Bias 16

E-MOSs 65 E-MOSs 66 Feedback Arrangement: Feedback Q-point: I G = 0 A V RG = 0 V Step 1 Plot the line using V GS = V DD, I D = 0 A I D = V DD / R D, V GS = 0 V V DS = V GS V GS = V DD I D R D Step 2

17 E-MOSs 65 E-MOSs 66 Feedback Arrangement: Feedback Q-point: I G = 0 A V RG = 0 V Step 1 Plot the line using V GS = V DD, I D = 0 A I D = V DD / R D, V GS = 0 V V DS = V GS V GS = V DD I D R D Step 2 Using values from the specification sheet, plot the transfer curve with V GSTh, I D = 0 A V GS(on), I D(on) Step 3 The Q-point is located where the line and the transfer curve intersect Step 4 Using the value of I D at the Q-point, solve for the other variables in the bias circuit E-MOSs 67 E-MOSs 68 Example 7-11: Determine I DQ and V DSQ : Example 7-11: 17

18 69 Voltage Divider Bias: Plotting the line and the transfer curve to find the Q-point: E-MOSs 70 Voltage Divider Bias ; E-MOSs 71 E-MOSs 72 Voltage Divider Bias Q-point: Step 1 Plot the line using V GS = V G = (R 2 V DD ) / (R 1 + R 2 ), I D = 0 A I D = V G /R S, V GS = 0 V Example 7-12: Determine I DQ, V GSQ and V DS : Step 2 Using values from the specification sheet, plot the transfer curve with V GSTh, I D = 0 A V GS(on), I D(on) Step 3 The point where the line and the transfer curve intersect is the Q-point. Step 4 Using the value of I D at the Q-point, solve for the other circuit values. 18

19 73 Summary 74 Summary Summary Design 19

20 Design 77 Design 78 Example 7-15: Example 7-16: Determine R S and R D : Determine R S when R D = 1800 Ω, R 1 = 91kΩ, R 2 = 47 kω, V DD = 16 V, V GSQ = -2V. Design Example 7-17: Determine V DD and R D, when V DS = ½ V DD and I D = I D(on). p-channel s 20

21 p-channel s 81 p-channel s 82 For p-channel sthe same calculations and graphs are used, except that the voltage polarities and current directions are reversed. The graphs are mirror images of the n-channel graphs. p-channel D MOS (VDB) p-channel J p-channel s 83 p-channel s 84 p-channel E MOS (FB) p-channel DMOS (VDB) 21

22 p-channel s Example 7-18: Determine I DQ, V GSQ and V DS : Applications Applications 87 Home Task 88 Applications: 1. Voltage Controlled Resistor 2. J Voltmeter 3. Timer Network 4. Fiber Optic System 5. MOS Relay Driver 1. ExerciseProblem1,2and4 2. ExerciseProblem7and11 3. Exercise Problem ExerciseProblem15and17 5. Exercise Problem Exercise Problem Exercise Problem Exercise Problem 31 CH 12 22

23 1. Boylestad References 89 CH 12 23

Chapter 7: FET Biasing

Chapter 7: FET Biasing Common FET Biasing Circuits JFET Biasing Circuits Fixed Bias Self-Bias oltage-ivider Bias -Type MOSFET Biasing Circuits Self-Bias oltage-ivider Bias E-Type MOSFET Biasing Circuits