Status of the EKV3.0 MOS Transistor Model

Transcription

1 Status of the EKV3.0 Transistor Model Matthias Bucher, Technical University of Crete Antonios Bazigos, National Technical University of Athens François Krummenacher, École Polytechnique Fédérale de Lausanne -/ESSDERC/ESSCIRC Workshop Compact Modelling for Emerging Technologies Friday, 22 September 2006 Montreux Switzerland

2 Presentation Outline About EKV3 Model Code in Verilog-A Physical Effects & Parameters Parameter Extraction Basic Methodology Modelling Results Summary A. Bazigos -- - Workshop, September 22,

3 About EKV3 A Design-Oriented, Charge-Based Model Moderate and Weak Inversion Special Attention to Analog/RF IC Design Requirements High Frequency Operation, Noise All Pertinent Effects to 45nm C Scaling over Technologies, Geometry, Temperature, Bias Validated on Various C Technologies. TOSHIBA, Infineon, Cypress, Atmel. Used for Commercial IC Design. A. Bazigos -- - Workshop, September 22,

4 EKV: Charge Based Modelling Inversion Charge q = q ( Ψ ); q, q i i S s d Drain Current i = q + q q q 2 2 s s d d Transconductance-to-Current Ratio g i d m sat 1 = 1/ 2 + i + 1/ 4 Short-Channel Thermal Noise Induced Gate Noise Transconductances g g g ms md m q s s q q d q n d Capacitances & Charges L x L 1 x QD W qidx, QS W qidx O L O L QX CXY = ± V Y A. Bazigos -- - Workshop, September 22,

5 EKV3 in Verilog-A The Verilog-A Code of EKV3.0 Hierarchical Structure 18 files one main file many smaller In Total: 83KB Compatible with (at least) ELDO, ADS, SPECTRE, ADMS, Used as the Reference Code for all Model Implementations ADMS provides standard C-code Various Simulators. ekv3.va include statements ekv3_extrinsic.va ekv3_overlap.va ekv3_gate_current.va ekv3_noise.va A. Bazigos -- - Workshop, September 22,

6 EKV3 and ADMS EKV3 Verilog-A Code Tested with ADMS (v2.1) Current version: ADMS v2.2.4 Tested with XML Interface for SPICE3 Different XML Interfaces for Different Simulators A. Bazigos -- - Workshop, September 22,

7 EKV3 Design Kit in ADS Tiburon: A Verilog-A Compiler in ADS An EKV3 Design Kit for ADS has been developed Design Kit contains 8 Elements, only FET QS / NQS N / P MODEL-CARD / INSTANCE 120nm C Design Kit has been used to Design Base-Band Elements (OP-AMPs) LNA A. Bazigos -- - Workshop, September 22,

8 EKV3 in ELDO (C-code) In ELDO a Hand-Written C-code Version of the Model exists Verilog-A Code: Simpler but less Efficient Not always Efficiently handled by the Simulators Generally Verilog-A + ADMS and C-code have the same Functionality A. Bazigos -- - Workshop, September 22,

9 Phenomena covered by EKV Associated Parameters 1/2 Modelled effect Related Parameters / Comments Physical Modelling of Charges Including Accumulation Region Polysilicon Depletion, Quantum Mechanical Effects COX(TOX), PHIF, GAMMA(NSUB), VTO(VFB), GAMMAG(NGATE) Bias-Dependent Overlap Capacitances NQS RF Model External Sub-Circuit LOV, GAMMAOV(NOV), VFBOV [Channel Segmentation] [Appropriate Scaling of RG, RSUBs with W, L and NF] Mobility (Reduction due to Vertical Field Effect) Surface Roughness-, Phonon-, Coulomb Scattering KP(U0), E0, E1, ETA ZC, THC Impact Ionization Current Gate Current (IGS, IGD, IGB) IBA, IBB, IBN KG, XB, UB A. Bazigos -- - Workshop, September 22,

10 Phenomena covered by EKV Associated Parameters 2/2 Reverse Short Channel Effect Inverse Narrow Width Effect Drain Induced Barrier Lowering Source and Drain Charge Sharing Halo/Pocket implant effects Edge Conduction Geometrical Effects, Width scaling Noise Flicker Noise, Short-Channel Thermal Noise, Induced Gate and Substrate Noise Temperature Effects TOTAL Modelled effect Longitudinal Field Effect Velocity Saturation, Channel Length Modulation Related Parameters / Comments UCRIT(VSAT), LAMBDA, DELTA LR, QLR, NLR WR, QWR, NWR ETAD, SIGMAD LETA, {LETA2}, WETA LETA0 WEDGE, DGAMMAEDGE, DPHIEDGE Various Parameters (DL, WQLR, ) AF, KF Various Parameters <100 A. Bazigos -- - Workshop, September 22,

11 Basic Parameter Extraction Methodology Wide Wide Long Long CV CV CGG vs vsvg: COX, VTO, GAMMA, PHIF, GAMMAG Wide Wide Long Long IV IV Wide Wide Short Short IV IV gm vs vsvg (lin): DL, RSX (fixing RSCE for correct V TO TO ) ID ID vs vsvg (sat): ETAD, [LETA] Wide Wide All All Lengths Lengths IV IV VTO vs vsl: LR, QLR, NLR {RSCE}, [LETA, LETA2, ETAD] Wide Wide Short Short CV CV CGG vs vsvg: LOV, GAMMAOV, [VFBOV], DLC Narrow Narrow channel channel similar similar procedure procedure gm gm vs vsvg (lin): KP, E0, E1, [ETA] ID ID vs vsvg (lin): LETA, [ETAD] Width Width scaling: scaling: All All lengths lengths w.r.t. w.r.t. width width Id, gds vs vsvd [strong inversion]: UCRIT, LAMBDA, DELTA [weak inversion]: ETAD Temperature Temperature analysis analysis END Narrow Narrow short short combined combined effects effects [fine [fine tuning] tuning] A. Bazigos -- - Workshop, September 22,

12 Short-Channel Characteristics L=70nm VD=1.5V L = 70nm L=70nm VD=1.5V 1.0E E E E-01 measured EKV E E-01 ID [A] 1.0E E E-07 GM*UT/ID [-] 5.0E E E-01 weak strong 1.0E E-09 measured EKV E E-01 moderate 1.0E VG [V] 0.0E E E E E E E E-02 ID [A] Correct Weak & Moderate Inversion Behaviour Smoothness and Correct Asymptotic Behaviour Correct Weak Inversion Slope and DIBL Modeling Transconductance-to-Current Ratio vs. Drain Current (log. axis) A. Bazigos -- - Workshop, September 22,

13 Short-Channel Output Characteristics L = 70nm L=70nm VB=0V L=70nm VB=-1V 9.0E E E E-03 measured EKV E E E-03 measured EKV3.0 ID [A] 5.0E E E E E E VD [V] ID [A] 5.0E E E E E E VD [V] gds [A/V] 1.0E E E-03 L=70nm VB=0V measured EKV3.0 gds [A/V] 1.0E E E-03 L=70nm VB=-1V measured EKV E E VD [V] 1.0E VD [V] A. Bazigos -- - Workshop, September 22,

14 NQS RF [Re(Y21), Im(Y21)] N Lg=80nm N Lg=2um Multifinger Various VG Values, Saturation A. Bazigos -- - Workshop, September 22,

15 Edge Conduction Effect on I D and g m /I D 100 N 10um/10um 100 N 10um / 80nm VD=1V id[-] 0.1 id[-] gm/id[-] vgb[-] L=10um N 10um/10um VD=1V id[-] gm/id[-] vgb[-] L=80nm N 10um / 80nm VD = 1V id[-] A. Bazigos -- - Workshop, September 22,

16 Gate Current & Edge Conduction N 10um / 10um VD = 50mV N 10um / 80nm VD = 50mV IG [A] 1.0E-6 1.0E-7 1.0E-8 1.0E-9 1.0E E E E E L=10um VGB[V] IG[A] 1.0E-8 1.0E-9 1.0E E E E E VGB[V] L=80nm Gate Current is also affected by Edge Conduction EKV3.0 gives reasonable fits to ID, gm/id, IG even in case of presence of Edge Conduction Effect Edge Conduction affects gm/id dramatically in Weak- Moderate Inversion A. Bazigos -- - Workshop, September 22,

17 Temperature Scaling L = 150nm I D V G and I D (g ds ) - V D vs. Temperature A. Bazigos -- - Workshop, September 22,

18 EKV3 and Industries TOSHIBA Semiconductors 140nm 110nm 80nm Infineon Technologies 120nm 90nm 65nm Cypress Semiconductors 150nm Atmel Corporation 350nm 130nm AustriaMicroSystems XFAB 350nm 180nm 350nm Various Co-Operations Tektronix A. Bazigos -- - Workshop, September 22,

19 Developments underway (EKV3.1) Vertical Non-Uniform Doping. Accounting for Carrier Heating/Velocity Saturation in Induced Gate Noise. A. S. Roy and C. C. Enz, WCM 2006 Mobility Effect to Improve Flexibility for Short-Channel Back-Bias Output Conductance Effects in Long Channel Halo/Pocket Implanted Devices Layout Dependent Stress Effects EKV3.1 Release expected: A. Bazigos -- - Workshop, September 22,

20 Summary EKV3.0: a design-oriented, charge-based, compact model for Next Generation C Moderate and Weak Inversion, Analog/RF IC Design Validated on Various C Technologies to 65nm. Used for Commercial IC Design. Developed in Verilog-A Verilog-A Code is Available to CAD Vendors. Specific Simulators require Specific XML interface in ADMS Design Kits developed. Implementation ongoing for: ELDO, Smash, GoldenGate, Spectre, HSPICE, A. Bazigos -- - Workshop, September 22,

21 Thank you very much for your time and attention