ULTRA LOW NOISE PSEUDOMORPHIC HJ FET PACKAGE OUTLINE

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1 FEATURES SUPER LOW NOISE FIGURE:.35 db Typ at f = 1 HIGH ASSOCIATED GAIN: 13. db Typ at f = 1 GATE LENGTH:. µm GATE WIDTH: 16 µm DESCRIPTION NEC's NE31 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to create high electron mobility. Its excellent low noise figure and high associated gain make it suitable for commercial, industrial and space applications. NEC's stringent quality assurance and test procedures assure the highest reliability and performance. ELECTRICAL CHARACTERISTICS (TA = 5 C) ULTRA LOW NOISE PSEUDOMORPHIC HJ FET PART NUMBER PACKAGE OUTLINE Drain Current, ID (ma) NE31 CHIP SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN TYP MAX NF Noise Figure, VDS = V, ID = 1 ma, f = 1 db GA 1 Associated Gain, VDS = V, ID = 1 ma, f = 1 db 13.5 IDSS Saturated Drain Current, VDS = V, VGS = V ma VP Pinch-off Voltage, VDS = V, ID = 1 µa V gm Transconductance, VDS = V, ID = 1 µa ms 4 55 NE31 IGSO Gate to Source Leakage Current, VGS = -3 V µa.5 1 Note: 1. RF performance is determined by packaging and testing 1 samples per wafer. Wafer rejection criteria for standard devices is rejects per 1 samples. Noise Figure, NF (db) NOISE FIGURE & ASSOCIATED GAIN vs. DRAIN CURRENT VDS = V f = NF GA Associated Gain, GA (db) California Eastern Laboratories

2 NE31 ABSOLUTE MAXIMUM RATINGS 1 (TA = 5 C) SYMBOLS PARAMETERS UNITS RATINGS VDS Drain to Source Voltage V 4. VGS Gate to Source Voltage V -3. IDS Drain Current ma IDSS IG Gate Current µa 1 PT Total Power Dissipation mw TCH Channel Temperature C 175 TSTG Storage Temperature C -65 to +175 Notes: 1. Operation in excess of any one of these parameters may result in permanent damage.. Chip mounted on Alumina heat sink. TYPICAL PERFORMANCE CURVES (TA = 5 C) Total Power Dissipation, (PT) mw Drain Current, IDS (ma) TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE Ambient Temperature, TA ( C) DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE VGS = V Drain to Source Voltage, VDS (V) -. V -.4 V -.6 V. RECOMMENDED OPERATING CONDITIONS (TA = 5 C) PART NUMBER NE31 SYMBOLS PARAMETERS UNITS MIN TYP MAX VDS Drain to Source Voltage V 1 3 ID Drain Current ma PIN Input Power dbm Maximum Stable Gain, MSG (db) Maximum Available Gain, MAG (db) Forward Insertion Gain, S1S (db) Drain Current, IDS (ma) MAXIMUM AVAILABLE GAIN, FORWARD INSERTION GAIN vs. DRAIN CURRENT MSG. (S1S) 4 Frequency, f (GHz) DRAIN CURRENT vs. GATE TO SOURCE VOLTAGE 6-1 VDS = V ID = 1 ma VDS = V Gate to Source Voltage, VGS (V) 3

3 NE31 NOISE PARAMETERS VDS = V, ID = 1 ma FREQ.(GHz) NF MIN (db) GA (db) Γopt RN/5 MAG ANG (DEG) CHIP DIMENSIONS (Units in µm) SOURCE Bonding Pad Area NE31 (CHIP) 5 DRAIN GATE Note: All dimensions are typical unless otherwise specified 6 SOURCE Chip Thickness: µm typical ORDERING INFORMATION PART NUMBER QUALITY GRADE NE31 Standard (Grade D)

4 NE31 TYPICAL SCATTERING PARAMETERS (TA = 5 C). VDS = V, IDS = 1 ma FREQUENCY S1 S1 S K S1 MAG 1 (GHz) MAG ANG MAG ANG MAG ANG MAG ANG (db) (db) Notes: 1. Gain Calculations: MAG = S1 (K ± K - 1 ). When K 1, MAG is undefined and MSG values are used. MSG = S1, K = S, = S - S1 S1 S S S MAG = Maximum Available gain MSG = Maximum Stable Gain. S Parameters include bond wires. Gate : Total 1 wire(s), 1 per bond pad,(46 µm) long each wire ; 131 µm height. Drain : Total 1 wire(s), 1 per bond pad,(49 µm) long each wire ; µm height. Source : Total wire(s), per side,(665 µm) long each wire ; 315 µm height. Wire :.1in (5.4 µm) Dia., Gold S1-15 S S S1 S1 S S1-3

5 NE31 TYPICAL SCATTERING PARAMETERS (TA = 5 C) S S VDS = V, IDS = ma FREQUENCY S1 S1 S K S1 MAG 1 (GHz) MAG ANG MAG ANG MAG ANG MAG ANG (db) (db) Notes: 1. Gain Calculations: MAG = S1 (K ± K - 1 ). When K 1, MAG is undefined and MSG values are used. MSG = S1, K = S, = S - S1 S1 S1 S1 S1 S1 MAG = Maximum Available gain MSG = Maximum Stable Gain. S Parameters include bond wires. Gate : Total 1 wire(s), 1 per bond pad,(46 µm) long each wire ; 131 µm height. Drain : Total 1 wire(s), 1 per bond pad,(49 µm) long each wire ; µm height. Source : Total wire(s), per side,(665 µm) long each wire ; 315 µm height. Wire :.1in (5.4 µm) Dia., Gold S S S1-6 S1-3

6 NE31 NE31 NONLINEAR MODEL SCHEMATIC GATE CGSx.pF Lgx.39nH FET NONLINEAR MODEL PARAMETERS (1) Parameters Q1 Parameters Q1 VTO RG 3 VTOSC RD 3 ALPHA RS 3 BETA.1 RGMET GAMMA.5 KF GAMMADC. AF 1 Q.5 TNOM 7 DELTA. XTI 3 VBI.6 EG 1.43 IS 1e- VTOTC N 1 BETATCE RIS FFE 1 RID TAU e-1 CDS.e-1 RDB 5 CBS 1e-9 CGSO CGDO.1e-1.5e-1 DELTA1.3 DELTA. FC.5 VBR Infinity (1) Series IV Libra TOM Model Q1 Ldx.39nH Lsx.13nH SOURCE UNITS Parameter CDSx.PF DRAIN Life Support Applications These NEC products are not intended for use in life support devices, appliances, or systems where the malfunction of these products can reasonably be expected to result in personal injury. The customers of CEL using or selling these products for use in such applications do so at their own risk and agree to fully indemnify CEL for all damages resulting from such improper use or sale. EXCLUSIVE NORTH AMERICAN AGENT FOR RF, MICROWAVE & OPTOELECTRONIC SEMICONDUCTORS CALIFORNIA EASTERN LABORATORIES Headquarters 459 Patrick Henry Drive Santa Clara, CA (4) 9-35 Telex FAX (4) Hour Fax-On-Demand: (U.S. and Canada only) Internet: DATA SUBJECT TO CHANGE WITHOUT NOTICE //1 time capacitance inductance resistance voltage current Units seconds farads henries ohms volts amps MODEL RANGE Frequency: to GHz Bias: VDS = 1 V to 3 V, ID = 1 ma to 3 ma Date: 1/99