Analog performance of advanced CMOS and EKV3 model

Transcription

1 NanoTera Workshop on Next-Generation MOSFET Compact Models EPFL, December 15-16, 2011 Analog performance of advanced CMOS and EKV3 model Matthias Bucher Assistant Professor Technical University of Crete (TUC) Chania, Greece bucher at electronics.tuc.gr

2 Outline Motivation the need for moderate inversion design Evolution of CMOS device performance from planar bulk to double-gate and FinFET EKV3 charge-based compact model EKV3 high-frequency model Conclusions 2

3 Scaling of F T for 180nm > 65nm CMOS 1,0E+12 1,0E+11 FT [Hz] 1,0E+10 1,0E+09 1,0E+08 0, IC = ID / Ispec [-] L=50nm (65nm NMOS, VD=1.2V) L=70nm (90nm NMOS, VD=1V) EKV3 L=110nm (110nm NMOS, VD=1.4V) EKV3 L=180nm (180nm NMOS, VD=1.3V) EKV3 NMOS transistors, high V D bias (variable) F T reaches 187, 134, 101, 52 GHz, respectively A plateau (max. F T ) is reached slightly above Moderate Inversion (MI, 0.1 < IC < 10) IC ~= 20 50, depends on V D 3

4 Scaling of normalized transconductance 1,00 SI: velocity saturation, vert. field mobility reduction. g m * U T / I D [-] 0,10 G(IC)/n0 180nm CMOS (L=180nm) 150nm CMOS (L=140nm) 110nm CMOS (L=110nm) 90nm CMOS (L=70nm) 0,01 0,01 0, IC [-] Weak Inversion (WI, IC<0.1): highest transconductance per given current Strong Inversion (SI, IC>10): stronger degradation due to higher fields in more advanced technology 4

5 Normalized transconductance WI: (DIBL, CS) STI. g ms U I D T = G( IC) = 1 2 gms * UT / ID [-] Inversion Coefficient: measured V D =V G + IC L I IC = I IC = ID / Ispec [-] Moderate Inversion D SPEC Normalization factor for drain current: I spec Normalized g m and g ds vs. IC and L Anomalous scaling of output conductance in WI Specific Current: 10x10 10x2 10x1 10x0.5 10x0.3 10x x0.2 10x x x x0.125 SI: VS, CLM. L = 10 um 125nm I Spec = 2nU 2 T μc ox W L 5

6 g ms /I D, g mb /I D vs. IC, L gmb *UT / ID [-] gms * UT / ID [-] L L measured V D =V G IC = ID / Ispec [-] 10x10 10x2 10x1 10x0.5 10x0.3 10x x0.2 10x x x x IC = ID / Ispec [-] 10x10 10x2 10x1 10x0.5 10x0.3 10x x0.2 10x x x x0.125 g g ms g U I m D U I mb D T T U I D = G( IC) = T = G( IC) n n 1 = G( IC) n + IC EKV model offers convenient estimation of large- and small-signal quantities for ideal charge-based MOSFET not available from other modelling approaches Moderate Inversion 6

7 Early voltage vs. IC, L Anomalous VA scaling 1000 measured V D =V G VA = ID/gds [1/V] L IC = ID / Ispec [-] Moderate Inversion 10x10 10x2 10x1 10x0.5 10x0.3 10x x0.2 10x x x x0.125 U I Early Voltage V A scaling is dominated by DIBL effect (δv TO /δv D ) V A scaling related to transconductance function G(IC) In strong inversion, velocity saturation & CLM dominate Anomalous scaling of output conductance in WI U V T A = g ds D T V V TO D 1 G( IC) n DIBL effect dominates gds in WI-MI 7

8 Scaling of DC gain planar bulk CMOS 100 A = gm / gds [-] 10 L=140nm (150nm CMOS), VD=VG L=180nm (180nm CMOS), VD=1V L L=110nm (110nm CMOS), VD=1.5V 1 L=70nm (90nm CMOS), VD=1.2V 0,01 0, IC [-] DC gain is strongly degraded (@minimum length!) for scaled CMOS problem for analog/rf design! 8

9 Outline Motivation the need for moderate inversion design Evolution of CMOS device performance from planar bulk to double-gate and FinFET EKV3 charge-based compact model EKV3 high-frequency model Conclusions 9

10 Double gate MOSFETs DG MOSFET is (one of!?!) the most promising device, because it has less geometry effects such as corner and narrow width effects The two gates are easy to be biased separately as they are formed in different process steps symmetric or asymmetric operation possible Effective control of short channel effects Higher current drive capability and transconductance Ideal weak inversion slope 10

11 Double gate FET transconductance and gain scaling Transconductance efficiency (g m /I D ) and intrinsic gain (g m /g ds ) V DS = 0.5 V V DS = 0.5 V N A = cm -3 t si = 6 nm t ox = 1.1 nm For gate lengths below 50 nm, important decrease in device efficiency and voltage gain drain/gate engineered DG MOSFETs required TCAD simulation 11

12 Double gate FET capacitance and F T scaling Capacitance C GS +C GD and cut-off frequency F T V DS = 0.5 V V DS = 0.5 V Extremely high speed of intrinsic devices Parasitics need to be considered 12

13 FinFET transconductance & gain Raskin e.a., TED(53), 2006 FinFET: short-channel effects on gm/id 13

14 Comparison planar-finfet Wambacq e.a., ISSCC 2008 Better gm/gds in FinFETs compared to planar Higher speed in planar bulk CMOS (strained silicon) Higher parasitic capacitances series resistance in FinFETs 14

15 FinFET V T & n scaling 0,6 0,5 FinFET Vth, n (VDS=1.2V) 2,0 1,8 0,4 1,6 VTH [V] 0,3 1,4 n [-] 0,2 0,1 VTH n 1,2 1,0 80nm, n-finfets, measured characteristics. Scaling versus channel length RSCE appears 0 1,0E-08 1,0E-07 1,0E-06 1,0E-05 L [m] Show severe subthreshold slope L=80nm 0,8 15

16 FinFET Early voltage scaling 10000,0 Early Voltage vs. L 1000,0 VG=0.5V VG=1V bulk Si MOSFET VA [V] 100,0 10,0 1,0 1,0E-08 1,0E-07 1,0E-06 1,0E-05 FinFET L [m] 80nm n-finfets V A scaling versus channel length FinFET Early voltage is very high V A,FinFET >= 10V A,planar L entails high intrinsic gain vs. planar 16

17 FinFET IV modelling with EKV3 1,0E-04 6,0E-05 1,0E-02 measured n-finfet L=10um measured 1,0E-05 model 1,0E-03 model 5,0E-05 model 1,0E-06 model 1,0E-04 measured measured 1,0E-07 4,0E-05 1,0E-05 n-finfet L = 90 nm 1,5E-03 1,3E-03 1,0E-03 ID [A] 1,0E-08 1,0E-09 3,0E-05 ID [A] 1,0E-06 1,0E-07 7,5E-04 1,0E-10 2,0E-05 1,0E-08 5,0E-04 1,0E-11 1,0E-12 1,0E-05 1,0E-09 1,0E-10 2,5E-04 1,0E-13 0,0E ,2 0,4 0,6 0,8 1 1,2 1,0E+00 VG [V] n-finfet L=10um 1,0E-11 0,0E ,2 0,4 0,6 0,8 1 1,2 1,0E+00 VG [V] n-finfet L=90nm 8,0E-01 8,0E-01 gm.ut/id [-] 6,0E-01 4,0E-01 measured model gm.ut/id [-] 6,0E-01 4,0E-01 measured model 2,0E-01 2,0E-01 0,0E+00 1E-12 1E-11 1E-10 1E-09 1E-08 1E-07 1E-06 0, ,0001 ID [A] 0,0E+00 1E-10 1E-09 1E-08 1E-07 1E-06 0, ,0001 0,001 0,01 ID [A] Ideal transconductance to current ratio planar-like (very low substrate doping) Short channel weak inversion slope remains good (L=90nm) similar observations as in planar bulk Si MOSFETs moderate inversion degradation of gm/id 17

18 FinFET IV modelling with EKV3 1,5E-03 6,0E-05 n-finfet L=10um measured measured model model 5,0E-05 n-finfet L=90nm 4,0E-05 1,0E-03 ID [A] 3,0E-05 ID [A] 2,0E-05 5,0E-04 1,0E-05 0,0E ,2 0,4 0,6 0,8 1 1,2 1,0E-05 VD [V] n-finfet L=10um measured 1,0E-06 model 0,0E ,2 0,4 0,6 0,8 1 1,2 VD[V] 1,0E-03 n-finfet L=90nm measured model 1,0E-04 gds [S] 1,0E-07 1,0E-08 1,0E-09 gds [S] 1,0E-05 1,0E-06 1,0E-10 1,0E-11 1,0E-07 1,0E-12 1,0E ,2 0,4 0,6 0,8 1 1,2 0 0,2 0,4 0,6 0,8 1 1,2 VD [V] VD [V] Short-channel output characteristics Velocity saturation effects, CLM, DIBL, needed many similarities with bulk Si MOSFETs 18

19 Outline Motivation the need for moderate inversion design Evolution of CMOS device performance from planar bulk to double-gate and FinFET EKV3 charge-based compact model EKV3 high-frequency model Conclusions 19

20 EKV3 model overview Due to CMOS scaling, ICs operate more and more in moderate and weak inversion Design methods and models are required classical methods don t cover moderate inversion EKV3 is a Compact MOS Transistor Model dedicated to Analog/RF IC design Developed as a successor of EKV2.6 Full charge-based modelling approach close to physics and design Special attention to analog/rf IC design requirements Covers essential effects down to 45nm CMOS Scaling over Technology Width Length T Bias EKV3 available for implementation to CAD vendors. 20

21 Configurations of EKV3 Simple model only internal accounting for (S,D) series resistance Simple model with external series resistance Simple RF model with gate and substrate resistance Full RF model with substrate resistivity network Full RF & NQS (channel segmentation) model. Bucher e.a., SSE(52),

22 EKV3 charge based model & extensions Basis of charge model development is surface potential equation & inversion charge linearization Same parameters as surface potential model Preserves the essence of a surface potential model. Extensions for CV: Vertical non-uniform doping Polydepletion Quantum effects Extensions of IV: Charge-based vertical field mobility Charge-based velocity saturation Charge-based CLM Gate tunnelling 22

23 EKV3 model scaling effects RSCE, INWE, combined short&narrow-channel effects DIBL, charge-sharing Halo/pocket implant effects channel Bias-dependent overlap & inner fringing capacitances Bias-dependent series resistance Geometry & temperature scaling Parasitic effects modelling Layout dependent stress Edge conduction Gate tunneling. 23

24 EKV3 model basic parameters 24

25 EKV3 model IV-CV-T parameter extraction M.-A. Chalkiadaki, Master Thesis, TUC

26 EKV3 long channel W = 2um, L = 0.5um sqrt(id) [sqrt(a)] ID [A] 3.0E E E E E E E E E E E E E E E E-11 Data EKV3 Series3 Series4 Series5 Series6 Series7 Series8 Series9 Series VG [V] Series1 Series2 Series3 Series4 Series5 Series6 Series7 Series8 Series9 Series VG [V] gm [S] gm. UT / ID [-] 9.0E E E E E E E E E E Data EKV3 Series4 Series5 Series6 Series7 Series8 Series9 Series10 EKV3 Series12 Series13 Series14 Series15 EKV3 Series17 Series18 Series19 Series20 VG [V] 1.0E E E E E E E-03 ID [A] Series1 Series2 Series3 Series4 Series5 Series6 Series7 Series8 Series9 Series10 26

27 EKV3 short-channel L=70nm VD=1.5V L=70nm VD=1.5V 1.0E E-01 W = 2um, L = 70nm ID [A] 1.0E E E E E E E-09 measured EKV3.0 GM*UT/ID [-] 7.0E E E E E E E-01 measured EKV E VG [V] 0.0E E E E E E E E-02 ID [A] Correct weak & moderate inversion behavior Smoothness and correct asymptotic behavior Correct weak inversion slope and DIBL modelling Transconductance-to-current ratio vs. drain current (log. axis) 27

28 EKV3 short-channel 9.0E-03 L=70nm VB=0V 8.0E-03 L=70nm VB=-1V W = 2um, L = 70nm gds [A/V] ID [A] 8.0E E E E E E E E-03 measured EKV3.0 L=70nm VB=0V 0.0E E VD [V] measured EKV E E-03 ID [A] gds [A/V] 7.0E E E E E E E E E-03 measured EKV3.0 L=70nm VB=-1V 0.0E E VD [V] measured EKV E E VD [V] 1.0E VD [V] Illustrates combination of: DIBL, CS, velocity saturation, CLM Lgate = 70nm 28

29 EKV3 CV characteristics of MOSFETs 1.4 C / Cox*Weff*Leff [-] Overlap & fringing caps. (do NOT scale with L) VG [V] CGG Vc=0V EKV3.0 CGC Vc=0V EKV3.0 CGC Vc=0.5V EKV3.0 CGC Vc=1V EKV3.0 Moderate Inversion Moderate inversion in MOSFETs highly important for analog/rf IC design Good trade-off among gain, speed, linearity, noise, matching Low-medium saturation voltage, series resistance effect negligible Reduced impact of mobility effects (vertical field) and velocity saturation 29

30 Outline Motivation the need for moderate inversion design Evolution of CMOS device performance from planar bulk to Double-gate and FinFET EKV3 charge-based compact model EKV3 high-frequency model Conclusions 30

31 EKV3 scalable model for high frequency Non quasi-static model (NQS) channel segmentation consistent AC/transient Gate- and substrate- parasitics scale with multi-finger layout R G ~W f /(L*N F ) R SB, R DB ~1/W f R B R DSB ~1/W f ~L/(W f *N F ) 31

32 Multi-finger RF MOSFETs Source=Bulk Width of finger G G G G G G G G G G Gate Source=Bulk Drain 150 μm pitch Drain Layout of RF multi-finger MOSFET Number of fingers N F Finger Width W f Gate Length L Source=Bulk Bazigos e.a., Physica Status Solidi C(5), 2008 Ground-Signal-Ground (GSG) RF Pads 2 port configuration Open-Short de-embedding structures 32

33 STI stress in multi-finger RF MOSFETs EKV3 meas. V DS =50m, 0.5, 1V Bazigos e.a., Physica Status Solidi C(5), 2008 NMOS, L=180nm, W f =2μm Layout-dependent stress effects due to shallow-trench isolation (STI) Threshold voltage dependence V T vs. N F Max. drain current dependence I D / N F vs. N F 33

34 CV Long/short gate and inversion capacitance Bucher e.a., RFMiCAE(18),

35 EKV3 RF scalability with L EKV3 meas. Y parameter scalability over channel length for NMOS L=110 nm, 180 nm, 250 nm, 450 nm, 1 um, 2um W=5 um, NF=10 VG=0.6V, VD=0.5V Bucher e.a., RFMiCAE(18),

36 EKV3 F T modelling EKV3 meas. NMOS, L = 110nm PMOS, L=110nm F T versus IC in 110nm CMOS, EKV model Highest F T is reached at IC ~10-30 (!) Most probable range for biasing of RF circuits for low noise is: 1 < IC < 20 (depending on technology and application) Bucher e.a., RFMiCAE(18),

37 Low frequency noise with EKV3.1 SVG WL [(Vm) 2 /Hz] 1E-20 1E-21 1E-22 1E-23 1E-24 1E-25 1E-26 measured simple 1/f noise model McWorther Hooge McWorther + Hooge NMOS W=20x2μm, L=70nm, V DS =0.8V, f=10hz 0,01 0, IC [-] SVG WL [(Vm) 2 /Hz] 1E-20 1E-21 1E-22 1E-23 1E-24 1E-25 1E-26 measured simple 1/f noise model McWorther Hooge McWorther + Hooge PMOS W=20x2μm, L=70nm, V DS =0.8V, f=10hz 0,01 0, IC [-] Mavredakis e.a., WCM-NanoTech, 2010 Bias dependence of low frequency noise covered (EKV3.1) Combines carrier number and mobility fluctuations Increase in noise in strong inversion Increase in noise (referred to gate) may also be observed in weak inversion 37

38 Outline Motivation the need for moderate inversion design Evolution of CMOS device performance from planar bulk to Double-gate and FinFET EKV3 charge-based compact model EKV3 high-frequency model Conclusions 38

39 Conclusions Moderate inversion design even at RF (scaling!) Future (today!) DG and FinFET technologies give: better short-channel behaviour, higher intrinsic gain. FT may be channel length EKV3: analog/rf IC design-oriented, charge-based, compact model Native implementations in: ELDO (Mentor Graphics), Smash (Dolphin), Spectre (Cadence), Smartspice (Silvaco). Parameter extraction support (GMC Suisse & AdMOS) Model covers all RF aspects from DC to RF (small/large signal including NQS) and Noise. Extended RF validations in 180nm, 110nm, 90nm CMOS. Fully scalable with L, W, NF, bias, f, technology. Simple model structure & parameter extraction. EKV3.1 new model release in 1 st quarter

40 Acknowledgments All EKV Team Christian Enz, Jean-Michel Sallese, François Krummenacher Wladek Grabinski Antonios Bazigos, Maria-Anna Chalkiadaki Rupendra Sharma, Nikos Mavredakis, Angelos Antonopoulos, Nikos Makris Contact: Prof. Matthias Bucher Director, Electronics Laboratory ECE Dept., Technical University of Crete (TUC), Chania, Crete, Greece phone: bucher at electronics.tuc.gr, 40

41 References A. Bazigos, M. Bucher, F. Krummenacher, J.-M. Sallese, A.-S. Roy, C. Enz, "EKV3 Compact MOSFET Model Documentation, Model Version ", Technical Report, Technical University of Crete, June C. Enz, E. Vittoz, Charge-based MOS transistor modeling, Wiley, M. Bucher, A. Bazigos, F. Krummenacher, J.-M. Sallese, C. Enz, EKV3.0: An Advanced Charge Based MOS Transistor Model, in W. Grabinski, B. Nauwelaers, D. Schreurs (Eds.), Transistor Level Modeling for Analog/RF IC Design, pp , Springer, A. Bazigos, M. Bucher, J. Assenmacher, S. Decker, W. Grabinski, Y. Papananos, An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs, IEEE Trans. on Electron Devices, Vol. 58, N 11, pp , Nov N. Mavredakis, A. Antonopoulos, M. Bucher, Bias Dependence of Low Frequency Noise in 90nm CMOS, Workshop on Compact Modeling, NSTI-Nanotech/Microtech, Vol. 2, pp , Anaheim, California, June 21-25, M. Bucher, A. Bazigos, S. Yoshitomi, N. Itoh, A scalable advanced RF IC design-oriented MOSFET model, Int. Journal of RF and Microwave Computer Aided Engineering, Vol. 18, N 4, pp , M. Bucher, A. Bazigos, An efficient channel segmentation approach for a large-signal NQS MOSFET model, Solid- State Electronics, Vol. 52, N 2, pp , A. Bazigos, M. Bucher, P. Sakalas, M. Schroter, W. Kraus, High-frequency compact modelling of Si-RF CMOS, Physica Status Solidi (c), Vol. 5, N 12, pp ,