Small-signal Modelling of SOI-specific MOSFET Behaviours. D. Flandre

Transcription

1 Small-signal Modelling of SOI-specific MOSFET Behaviours D. Flandre Microelectronics Laboratory (DICE), Research Center in Micro- and Nano-Scale Materials and Electronics Devices (CeRMiN), Université catholique de Louvain (UCL) Louvain-la-Neuve, Belgium

2 SOI-specific device behaviors: Challenges for compact modelling as well as parameter extraction and process engineering? 1. Introduction 2. Specific phenomena 3. Recent scaling effect 4. Conclusion Acknowledgements : UCL colleagues (M. Bawedin, D. Lederer, D. Levacq, V. Kilchytska, P. Simon, J.-P. Raskin ), IMEC, LETI (for advanced devices), SINANO (EU Network)

3 I. Silicon-on-Insulator (SOI) Partially Depleted vs. Fully Depleted nm <400 nm depletion quasi-neutral Si buried oxide (BOX) V th f(t BOX, T Si ) Easier to manufacture at present (IBM, AMD ) V th = f(t BOX, T Si ) <<70 nm <400 nm Less industrialized (only OKI 0.15 µm), but higher promises (UTB, FinFET )

4 Basic I-V behavior Partially Depleted vs. Fully Depleted depletion quasi-neutral Si buried oxide (BOX) V th,front f(v Gb ) But sqrt (V B ) As in bulk CMOS V th,front = f(v Gb ) But linear and lower coupling vs. Bulk and PD In both cases, to 1st order, I-V curves as in bulk Similar models but with adequate parameters : BSIMSOI (+ EKV, PSP under development)!

5 II. Specific SOI Phenomena Partially-depleted MOSFET SOI MOSFET no V Gb, T ob, Q ob, N ob dependences V Gf Floating floating substrate node node V B V B - normal operation : V B - V S V ch - V B γ as in bulk V S V B V D - far in saturation : I ii V B > V S V th, I D (kink effect ) V Gb Impact Ionization, Gate tunneling Hole current in n-mos Drain current Drain voltage «KINK Effect» Also parasitic bipolar effect!

6 1.40E E E-03 NMOS (W=10µ, VGS=1V FD SOI PD SOI FB PD SOI BT ID (A) 8.00E E-04 BULK 4.00E E E VD (V) PD SOI BT = «Body tie» Source Drain P+ - substrate contact To source or ground N+ N+ Trade area vs FBE, but care with tie efficiency, Gate i.e. resistance!

7 1.40E E E-03 NMOS (W=10µ, VGS=1V FD SOI PD SOI FB PD SOI BT ID (A) 8.00E E-04 BULK 4.00E E E VD (V) PD SOI : FB = Floating body Beneficial for current increase, i.e. speed, But dynamic couplings can be detrimental!

8 Delay Time between DC point measurements What is DC?

9 Floating-body effects (FBE) compact modelling All static and dynamic Body (B) couplings to G, S, D and Gnd History effects AC/RF effects on small-signal parameters Gnd Introduced in major models : BSIMSOI But requires careful parameter extraction!

10 Output conductance vs. Frequency Wideband frequency measurements = solution for parameter extraction!

11 Output conductance vs. Frequency Wideband = from DC to > GHz FB FB BT FB : f pole < f zero BT : f pole > f zero

12 Output conductance : Modelling body C i.i. junctions body R

13 Output conductance : Modelling g bbi = g jbsi + g jbdi + R be -1 C bbi = C bsi + C bdi + C bgi

14 Output conductance : Modelling with BSIM FB BT Need for extraction : C gb, g bs, C bs, g bd, C bd!

15 Self-Heating Self-heating Observations : large Vg and Vd negative conductance Istatic < Idynamic Drain current rapid scan (20 ns) slower scan (1 µs) Origin : buried oxide = thermal isolator power not dissipated in substrate device temperature µ, I D Drain voltage important for device characterization, not for LVLP circuit operation motivation to scale BOX to increase heat evacuation?

16 Frequency response of output conductance Self-heating Floating body (PD) g intr no SH g intr body g intr SH kink no kink kink-effect f~ Hz f~ Hz f~ Hz g(f)=g intr +g SH (f)+g FB (f) R-coupled body C-coupled before kink W. Jin, W. Liu, S.K.H. Fung, P.C.H. Chan, and C. Hu, SOI thermal impedance extraction methodology and its significance for circuits simulation, IEEE Trans. Electron Devices, vol. 48, no. 4, pp , B.M. Tenbroek, W. Redman-White, M.J. Uren, et al., Identification of thermal and electrical time constants in SOI MOSFETs from small signal measurements, Proc. of 23 rd ESSDERC, Grenoble, France, Sept. 1993, pp

17 III. Recent scaling effect Length and BOX scaling SFBE: Substrate Floating Body Effect on g m and g d High frequency exp. FD SOI MOSFET : L eff =0.16µm, W=16x6.6µm, V D =V G =1V Substrate coupling? DC value Difference with DC is due to SH (in part) Kilchytska et al, IEEE EDL, 2004

18 Experimental results : Low frequency FD SOI MOSFET : L=90nm, W=5µm, V D =1.5V, V G =0.5V G DS sub, µs/µm V sub = 0.25V 0V 0.25V V 1V Not compatible with SH! Frequency, Hz Kilchytska et al, IEEE EDL, 2007

19 Conductance G SD, µs/µm 2D Atlas device simulations 3 rd transition L=1 µm, V D =V G = 1V nd transition 1.3 1st transition Selfheating Frequency, Hz With substrate S G n p n BOX substrate SUB D Without substrate S G D n p n BOX SUB 1 st and 3 rd tr. still present for simulation without SH Kilchytska et al, ESSDERC, st and 3 rd tr. disappear for simulation without substrate

20 2D Atlas simulations: Influence of substrate bias Reduced Output Conductance G SD = G SD (f) G SD (10 Hz), µs/µm Analogy with MOS capacitor inv LF HF UHF acc L=0.25µm; V D =V G =1V LF HF UHF Frequency, Hz accumulated BOX-substrate interface only 3 rd tr. in G SD (f) inverted BOX-substrate interface 1st and 3 rd tr. in G SD (f)

21 Analytical substrate model acccumulation C inversion LF 1 st tr. in G SD (f) BG C BOX HF UHF R SC R Si C SC C Si 3 rd tr. in G SD (f) V 1 st tr. is due to inertia of minority carriers 3 rd tr. is due to inertia of majority carriers

22 Equivalent macro compact model G Fully-depleted g m v GS G = g + SD ds g SDsub S C GS C sub C SBG BG g mb v BGS g ds C GBG C GD CBGD v BGS D C g BGD SDsub = ( n + C FD = CBGD + C SBG g mb 1) v v g m GBG BGS DS v v + C = BGS DS sub v DS

23 Substrate Coupling : Scaling trend source BOX source gate channel drain Si substrate Increased SCE T BOX shrinking gate channel drain BOX Si substrate Reduced G SD (µs/µm) SG FD SOI; L = 0.17 µm; Vg = 0.7 V; Vd = 1.5 V 100 T BOX =20nm 2D Atlas simulations: T BOX =150nm 80 T BOX =400nm 60 ~145% of DC value ~14% of DC value 0 ~1% of DC value Frequency (Hz) Amplitudes of substrate- related transitions in G SD increase very strongly with BOX thinning!!! Kilchytska et al, ULIS 2007

24 Conclusions SOI specific «floating body» phenomena = * special concern for new devices / circuits characterization methods (wideband) modelling and simulation process engineering / optimization * deserves attention for correct performance assessment parameter extraction application (avoid detrimental effects, exploit benefits, opportunities)