EE247 Lecture 17. EECS 247 Lecture 17: Data Converters 2010 Page 1. EE247 Lecture 17

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1 EE247 Lecure 17 Adminisraive issues Miderm exam posponed o Thurs. Oc. 28h o You can only bring one 8x11 paper wih your own wrien noes (please do no phoocopy) o No books, class or any oher kind of handous/noes, calculaors, compuers, PDA, cell phones... o Miderm includes maerial covered o end of lecure 14 EECS 247 Lecure 17: Daa Converers 2010 Page 1 EE247 Lecure 17 ADC Converers Sampling (coninued) Sampling swich consideraions Clock volage boosers Sampling swich charge injecion & clock feedhrough Complemenary swich Use of dummy device Boom-plae swiching Track & hold T/H circuis T/H combined wih summing/difference funcion T/H circui incorporaing gain & offse cancellaion T/H aperure uncerainy EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 2

2 P_N kt/c noise 2 C 12kBT VFS 0.72 R B f C s 2B Finie R sw limied bandwidh g sw = f (n ) disorion 2 Pracical Sampling Summary So Far! v IN 1 M1 v OUT C Vin W gon go 1 for go Cox VDD Vh VDD V h L Allowing long enough seling ime reduce disorion due o swich non-linear behavior EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 3 Consan S Sampling Circui VDD=3V M1 M2 M3 M8 M6 VP1 100ns P C1 PB C2 C3 M12 P M4 M5 M9 VS1 1.5V 1MHz Va Vg M11 Vb Chold This Example: All device sizes:w/l=10/0.35 All capacior size: 1pF (excep for Chold) Noe: Each criical swich requires a separae clock booser Sampling swich & C Ref: A. Abo e al, A 1.5-V, 10-bi, 14.3-MS/s CMOS Pipeline Analog-o-Digial Converer, JSSC May 1999, pp EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 4

3 Clock Volage Doubler VDD=3V 2VDD M1 M2 P_Boos R1 R2 VDD C1 C2 PB P 0 VP1 Clock period: 100ns *R1 & R2=1GOhm dummy resisors added for simulaion only EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 5 Consan S Sampler: F Low VDD=3V ~ 2 VDD (boosed clock) M3 Triode OFF VDD C3 M4 Sampling swich M11 is OFF VDD M12 Triode Inpu volage source OFF M11 OFF VS1 1.5V 1MHz Chold 1pF Device OFF C3 charged o ~VDD EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 6

4 Consan S Sampler: F High M8 C3 previously charged o VDD VDD C3 1pF M8 & M9 are on: C3 across G-S of M11 M9 VS1 1.5V 1MHz M11 Chold M11 on wih consan VGS = VDD Mission accomplished!? EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 7 Consan S Sampling Inpu Swich ae Chold Signal Inpu Signal EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 8

5 Consan S Sampling? EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 9 Consan S Sampling? During he ime period: n < V ou S =consan=v DD IR During he ime period: n >V ou : S = V DD - IR Larger S -V h compared o no boos S =ce and no a funcion of inpu volage Significan lineariy improvemen Larger S -V h compared o no boos S is a funcion of IR and hence inpu volage Lineariy improvemen no as pronounced as for n < V ou EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 10

6 Boosed Clock Sampling Design Consideraions Choice of value for C3: C3 oo large large charging curren large dynamic power dissipaion VDD C3 M8 C3 oo small (Vgae-Vs) M11 = VDD.C3/(C3+Cx) Loss of VGS M11 due o low raio of C3/Cx Cx includes C GS of M11 plus all oher parasiics caps. M9 Cx Vin M11 Chold Ref: A. Abo e al, A 1.5-V, 10-bi, 14.3-MS/s CMOS Pipeline Analog-o-Digial Converer, JSSC May 1999, pp EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 11 Boosed Clock Sampling Design Consideraions Reliabiliy issues: Avoid having any of he G-S and G-D, and D-S erminal volages for ALL circui devices exceed he maximum V DD prescribed by he SI processing firm. In paricular, he hin MOS device gae oxide could gradually susain damage hrough geing exposed o higher han prescribed volage. EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 12

7 Clock Muliplier M7 & M13 for reliabiliy Remaining issues: -S consan only for n <V ou -Nonlineariy due o Vh dependence of M11on bodysource volage Boosed Clock Sampling Complee Circui Ref: A. Abo e al, A 1.5-V, 10-bi, 14.3-MS/s CMOS Pipeline Analog-o-Digial Converer, JSSC May 1999, pp Swich EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 13 Advanced Clock Boosing Technique Ref: M. Walari e al., "A self-calibraed pipeline ADC wih 200MHz IFsampling fronend," ISSCC 2002, Dig. Tech. Papers, pp. 314 Sampling Swich Two floaing volages sources generaed and conneced o Gae and S & D EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 14

8 Advanced Clock Boosing Technique clk low Sampling Swich clk low Capaciors C1a & C1b charged o VDD MS off Hold mode EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 15 Advanced Clock Boosing Technique clk high Sampling Swich clk high Top plae of C1a & C1b conneced o gae of sampling swich Boom plae of C1a conneced o V IN Boom plae of C1b conneced o V OUT VGS & VGD of sampling swich (MS) VDD & ac signal on G of MS average of V IN & V OUT EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 16

9 Advanced Clock Boosing Technique Ref: M. Walari e al., "A self-calibraed pipeline ADC wih 200MHz IFsampling fronend," ISSCC 2002, Dig. Tech. Papers, pp. 314 Sampling Swich Gae racks average of inpu and oupu, reduces effec of I R drop a high frequencies Bulk also racks signal reduced body effec (echnology used allows connecing bulk o S) Repored measured SFDR = 76.5dB a f in =200MHz EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 17 Consan Conducance Swich Ref: H. Pan e al., "A 3.3-V 12-b 50-MS/s A/D converer in 0.6um CMOS wih over 80-dB SFDR," IEEE J. Solid-Sae Circuis, pp , Dec EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 18

10 Consan Conducance Swich OFF Ref: H. Pan e al., "A 3.3-V 12-b 50-MS/s A/D converer in 0.6um CMOS wih over 80-dB SFDR," IEEE J. Solid-Sae Circuis, pp , Dec EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 19 Consan Conducance Swich M2 Consan curren ON M1 replica of M2 & same VGS as M2 M1 also consan curren Noe: Auhors repor requiremen of 280MHz GBW for he opamp for 12bi 50Ms/s ADC Also, opamp common-mode compliance for full inpu range required Ref: H. Pan e al., "A 3.3-V 12-b 50-MS/s A/D converer in 0.6um CMOS wih over 80-dB SFDR," IEEE J. Solid-Sae Circuis, pp , Dec EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 20

11 Swich Off-Mode Feedhrough Cancellaion Ref: M. Walari e al., "A self-calibraed pipeline ADC wih 200MHz IF-sampling fronend," ISSCC 2002, Dig. Techn. Papers, pp. 314 EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 21 Pracical Sampling Issues 1 v IN M1 C v OUT Swich induced noise due o M1 finie channel resisance Clock jier Finie R sw limied bandwidh finie acquisiion ime R sw = f(n ) disorion Swich charge injecion & clock feedhrough EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 22

12 Sampling Swich Charge Injecion & Clock Feedhrough Swiching from Track o Hold V H +V h M1 VO V L V O DV C s off Firs assume is a DC volage When swich urns off unwaned offse volage induced on C s Why? EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 23 Sampling Swich Charge Injecion MOS xor operaing in riode region Cross secion view L D Disribued channel resisance & gae & juncion capaciances G C ov C ov L W S C j sb B C j db D C HOLD Channel disribued RC nework formed beween G,S, and D Channel o subsrae juncion capaciance disribued & volage dependan Drain/Source juncion capaciors o subsrae volage dependan Over-lap capaciance C ov = L D.W.C ox associaed wih G-S & G-D overlap EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 24

13 Swich Charge Injecion Slow Clock V H Device sill conducing +V h V L - off Slow clock clock fall ime >> device speed During he period (- o off ) curren in channel discharges channel charge ino low impedance signal source Only source of error Clock feedhrough from C ov o C s EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 25 Swich Clock Feedhrough Slow Clock VG V H C ov +V h D C D ov V Vi Vh VL Cov Cs Cov V h V L Cs o i D C s V L V O V V V C C C V V V V V V 1 V V V V 1 V ov ov ov o i i h L i h L C s C s Cs o i os - off DV Cov C where ; V V V C s ov os h L Cs EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 26

14 Swich Charge Injecion & Clock Feedhrough Slow Clock- Example M1 10/0.18 VO C s =1pF V H +V h ' 2 ov ox h L C 0.1fF / C 9 ff / V 0.4V V 0 Cov 10x0.1fF /.1% Cs 1pF Allowing 1/ 2LSB ADC resoluion ~ 9bi C V V V 0. 4mV ov os h L Cs V L V O - off DV EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 27 Swich Charge Injecion & Clock Feedhrough Fas Clock Q ch nqch n+m=1 M1 VO mq ch C s =1pF V H +V h V L V O DV off Sudden gae volage drop no gae volage o esablish curren in channel channel charge has no choice bu o escape ou owards S & D EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 28

15 Swich Charge Injecion & Clock Feedhrough Fas Clock Clock Fall-Time << Device Speed: C 1 Q DV V V ov ch o H L Cov Cs 2 Cs C 1 WC L V V V C C 2 C Vo Vi 1 Vos 1 WCoxL where 2 Cs C 1 WCoxL VH Vh V V V C 2 C ov ox H i h VH VL ov s s ov os H L s s V H V L V O off +V h DV For simpliciy i is assumed channel charge divided equally beween S & D Source of error channel charge ransfer + clock feedhrough via C ov o C s EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 29 Swich Charge Injecion & Clock Feedhrough Fas Clock- Example M1 10 /0.18 V H VO +V h C s =1pF ff ff Cov 0.1, Cox 9, V 2 h 0.4V,VDD 1.8V, VL 0 WLCox 10x0.18 x9 ff / 1/ 2 1.6% ~ 5 bi C 1pF ov os H L s s s 2 C 1 WCoxL VH Vh V V V 1.8mV 14.6mV 16.4mV C 2 C V L V O off DV EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 30

16 Swich Charge Injecion & Clock Feedhrough Example-Summary 1.6% 16mV V OS.1% Clock fall ime 0.4mV Clock fall ime Error funcion of: Clock fall ime Inpu volage level Source impedance Sampling capaciance size Swich size Clock fall/rise should be conrolled no o be faser (sharper) han necessary EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 31 Swich Charge Injecion Error Reducion How do we reduce he error? Reduce swich size o reduce channel charge? 1Qch DVo 2Cs Cs Ts RON C s ( noe : k ) W Cox VGS Vh 2 L Consider he figure of meri (FOM): W Cox VGS Vh 1 L Cs FOM 2 DV C WC LV V V FOM L o s ox H i h 2 Reducing swich size increases increased disorion no a viable soluion Small and small DV use minimum chanel lengh (mandaed by echnology) For a given echnology x DV ~ consan EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 32

17 Sampling Swich Charge Injecion & Clock Feedhrough Summary Exra charge injeced ono sampling swich device urn-off Channel charge injecion Clock feedhrough o C s via C ov Issues due o charge injecion & clock feedhrough: DC offse induced on hold C Inpu dependan error volage disorion Soluions: Slowing down clock edges as much as possible Complemenary swich? Addiion of dummy swiches? Boom-plae sampling? EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 33 Swich Charge Injecion & Clock Feedhrough Complemenary Swich 1 V H 1 1B 1B 1 1B V L In slow clock case if area of n & p devices & widhs are equal (W n =W p ) effec of overlap capacior for n & p devices o firs order cancel (cancellaion accuracy depends on maching of n & p widh and overlap lengh L D ) Since in CMOS echnologies n ~2.5 p choice of W n =W p no opimal from lineariy perspecive (W p >W n preferable) EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 34

18 Q W C L V V V chn n ox n H i hn Q W C L V V V ch p p ox p i L Swich Charge Injecion Complemenary Swich Fas Clock h p V H 1Qch n Q DVo 2 Cs C ch p s V L V V 1 V o i os 1 WnCox Ln WpCoxLp 2 Cs In fas clock case To 1 s order, offse due o overlap caps cancelled for equal device widh Inpu volage dependan error worse! 1 1B EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 35 Swich Charge Injecion Dummy Swich M1 M2 V O C s V H B Q 1 Q 2 W M2 =1/2W M1 1 Q Q Q 2 M1 M1 1 ch ov V L M 2 M 2 2 ch ov Q Q 2Q 1 For W W Q Q & Q 2Q 2 M1 M 2 M 2 M1 2 1 ov ov EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 36

19 M1 Swich Charge Injecion Dummy Swich B M2 V O C s V H B Q 1 Q 2 W M2 =1/2W M1 V L Dummy swich same L as main swich bu half W Main device clock goes low, dummy device gae goes high dummy swich acquires same amoun of channel charge main swich needs o lose Effecive only if exacly half of he charge sored in M1 is ransferred o M2 (depends on inpu/oupu node impedance) and requires good maching beween clock fall/rise EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 37 Swich Charge Injecion Dummy Swich R M1 B M2 W M2 =1/2W M1 VO C s C s To guaranee half of charge goes o each side creae he same environmen on boh sides Add capacior equal o sampling capacior o he oher side of he swich + add fixed resisor o emulae inpu resisance of following circui Issues: Degrades sampling bandwidh EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 38

20 Dummy Swich Effeciveness Tes Dummy swich W=1/2W main As Vin is increased Vc1-Vin is decreased channel charge decreased less charge injecion Noe large Ls good device area maching Ref: L. A. Biensman e al, An Eigh-Channel 8 13i Microprocessor Compaible NMOS D/A Converer wih Programmable Scaling, IEEE JSSC, VOL. SC-15, NO. 6, DECEMBER 1980 EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 39 + V O+ Swich Charge Injecion Differenial Sampling Cs V V V V V V o o od i i id V V V V Voc 2 2 V V 1 V o o i i Vic o i 1 os1 V V 1 V o i 2 os2 V V V V V V od id id 1 2 ic os1 os2 - Cs To 1 s order, offse erms cancel V O- Noe gain error sill abou he same Has he advanage of beer immuniy o noise coupling and cancellaion of even order harmonics EECS 247 Lecure 17: Daa Converers- ADC Design, Sampling 2010 Page 40

21 Avoiding Swich Charge Injecion Boom Plae Sampling 1D 1 M1 V O V H V L Cs 1D 1 M2 Swiches M2 opened slighly earlier compared o M1 Injeced charge due o urning off M2 is consan since is GS volage is consan & eliminaed when used differenially Since C s boom plae is already open when M1 is swiched off: No signal dependan charge injeced on C s EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 41 Flip-Around Track & Hold 2 1 S2A 1D 1D 2 v IN 1D C 2 S3 S1A S2 v OUT 1 S1 Concep based on boomplae sampling v CM EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 42

22 Flip-Around T/H-Basic Operaion 1 high 2 1 S2A 1D 1D 2 v IN 1D S1A C 2 S2 S3 Charging C vout Q 1 =V IN xc 1 S1 v CM Noe: Opamp has o be sable in uniy-gain configuraion EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 43 Flip-Around T/H-Basic Operaion 2 high 2 1 S2A 1D 1D 2 1D C 2 S3 Holding v IN S1A S2 v OUT 1 S1 v CM Q 2 =V OUT xc V OUT = V IN EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 44

23 Flip-Around T/H - Timing 2 S2A 1D 1 1D v IN 1D C 2 S3 2 S1A 1 S1 S2 v CM vout S1 opens earlier han S1A No resisive pah from C boom plae o Gnd charge can no change "Boom Plae Sampling" EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 45 Charge Injecion A he insan of ransiioning from rack o hold mode, some of he charge sored in sampling swich S1 is dumped ono C Wih "Boom Plae Sampling", only charge injecion componen due o opening of S1 and is o firs-order independen of v IN Only a dc offse is added. This dc offse can be removed wih a differenial archiecure EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 46

24 Flip-Around T/H Consan swich S o minimize disorion 2 1 S2A 1D 1D 2 v IN 1D S1A C 2 S2 S3 v OUT 1 S1 v CM Noe: Among all swiches only S1A & S2A experience full inpu volage swing EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 47 Flip-Around T/H S1 is chosen o be an n-channel MOSFET Since i always swiches he same volage, i s onresisance, R S1, is signal-independen (o firs order) Choosing R S1 >> R S1A minimizes he non-linear componen of R = R S1A + R S1 Typically, S1A is a wide (much lower resisance han S1) & consan S swich In pracice size of S1A is limied by he (nonlinear) S/D capaciance ha also adds disorion If S1A s resisance is negligible delay depends only on S1 resisance S1 resisance is independen of V IN error due o finie ime-consan independen of V IN EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 48

25 Differenial Flip-Around T/H Choice of Sampling Swich Size C s =7pF THD simulaed w/o sampling swich boosed clock -45dB THD simulaed wih sampling swich boosed clock (see graph) Ref: K. Vleugels e al, A 2.5-V Sigma Dela Modulaor for Broadband Communicaions Applicaions IEEE JSSC, VOL. 36, NO. 12, DECEMBER 2001, pp EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 49 Differenial Flip-Around T/H S11 S12 Offse volage associaed wih charge injecion of S11 & S12 cancelled by differenial naure of he circui During inpu sampling phase amp oupus shored ogeher Ref: W. Yang, e al. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC Wih 85-dB SFDR a Nyquis Inpu, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 50

26 Differenial Flip-Around T/H Gain=1 Feedback facor=1 high operaing speed EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 51 Differenial Flip-Around T/H Issues: Inpu Common-Mode Range 1.7V VCM=1.5V 1V 1V 1V 0.5V 1.2V 1.3V 0.8V Dn-cm =1-1.5= - 0.5V Dn-cm =V ou_com -V sig_com Drawback: Amplifier needs o have large inpu common-mode compliance EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 52

27 Inpu Common-Mode Cancellaion Noe: Shoring swich M3 added Ref: R. Yen, e al. A MOS Swiched-Capacior Insrumenaion Amplifier, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 53 Inpu Common-Mode Cancellaion 1V+0.2V V-0.2V Track mode ( high) V C1 =V I1, V C2 =V I2 V o1 =V o2 =0 Hold mode ( low) V o1 +V o2 =0 V o1 -V o2 = -(V I1 -V I2 )(C 1 /(C 1 +C 3 )) Inpu common-mode level removed EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 54

28 Swiched-Capacior Techniques Combining Track & Hold wih Oher Funcions T/H + Charge redisribuion amplifier T/H & Inpu difference amplifier T/H & summing amplifier Differenial T/H combined wih gain sage Differenial T/H including offse cancellaion EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 55 T/H + Charge Redisribuion Amplifier Track mode: (S1, S3 on S2 off) V C1 =V os V IN, V C2 =0 V o =V os EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 56

29 T/H + Charge Redisribuion Amplifier Hold Mode S1 & S3 open S2 closed 2 1 Hold/amplify mode (S1, S3 off S2 on) Offse NOT cancelled, bu no amplified Inpu-referred offse =(C 2 /C 1 ) x V OS, & ofen C 2 <C 1 EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 57 T/H & Inpu Difference Amplifier Sample mode: (S1, S3 on S2 off) V C1 =V os V I1, V C2 =0 V o =V os EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 58

30 Inpu Difference Amplifier Con d Subrac/Amplify mode (S1, S3 off S2 on) During previous phase: V C1 =V os V I1, V C2 =0 V o =V os 1 Offse NOT cancelled, bu no amplified Inpu-referred offse =(C 2 /C 1 )xv OS, & C 2 <C 1 EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 59 T/H & Summing Amplifier EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 60

31 T/H & Summing Amplifier Con d Sample mode (S1, S3, S5on S2, S4 off) V C1 =V os V I1, V C2 =V os -V I3, V C3 =0 V o =V os EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 61 T/H & Summing Amplifier Con d Amplify mode (S1, S3, S5off, S2, S4 on) 3 EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 62

32 Differenial T/H Combined wih Gain Sage Employs he previously discussed echnique o eliminae he problem associaed wih high common-mode volage excursion a he inpu of he opamp Ref: S. H. Lewis, e al., A Pipelined 5-Msample/s 9-bi Analog-o-Digial Converer IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 63 Differenial T/H Combined wih Gain Sage 1 High Ref: S. H. Lewis, e al., A Pipelined 5-Msample/s 9-bi Analog-o-Digial Converer IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 64

33 Differenial T/H Combined wih Gain Sage Gain=4C/C=4 Inpu volage common-mode level removed opamp can have low inpu common-mode compliance Amplifier offse NOT removed Ref: S. H. Lewis, e al., A Pipelined 5-Msample/s 9-bi Analog-o-Digial Converer IEEE JSSC, VOL. SC-22,NO. 6, DECEMBER 1987 EECS 247 Lecure 17: Daa Converers- Track & Hold- ADC Design 2009 Page 65

Summary of Last Lecture

Summary of Last Lecture EE47 Lecture 7 DAC Converters (continued) Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch considerations Thermal noise due to switch resistance Sampling switch