A 159 µw, Fourth Order, Feedforward, Multi-bit Sigma-Delta Modulator for 100 khz Bandwidth Image Sensors in 65-nm CMOS Process

Transcription

1 RADIOENGINEERING, VOL. 27, NO. 2, JUNE A 159 µw, Fourh Order, Feedforward, Muli-bi Sigma-Dela Modulaor for 100 khz Bandwidh Image Sensors in 65-nm CMOS Process Mudasir BASHIR, Sreehari RAO PATRI, K. S. R. KRISHNAPRASAD Dep. of Elecronics and Communicaion Engineering, Naional Insiue of Technology Warangal, India mudasir.mir7@gmail.com, {pari, krish}@niw.ac.in Submied March 19, 2017 / Acceped Sepember 28, 2017 Absrac. A fourh-order, hree-sage, feedforward cascade sigma-dela modulaor (ƩΔM) for CMOS image sensor applicaions is realized in low leakage, high hreshold volage 65 nm CMOS sandard process. A op down CAD mehodology is used for he design of building blocks, which involves saisical and simulaion opimizaion a differen sages of modulaor. The muli-bi ƩΔ archiecure employs OTA sharing echnique wih he dual inegraing scheme a he firs sage and he gain boosed pseudo-differenial class-c inverers as OTAs for he res wo sages for low area and power consumpion. The operaion of proposed ƩΔM is validaed hrough pos-layou simulaions, considering wors case. The ƩΔM operaes a a power supply of 1-V offering a peak signal-o-raio of 92 db and a peak signal-o-noise plus disorion raio of 89 db for a signal bandwidh of 100 khz. The overall power and esimaed area consumed by he ƩΔM including auxiliary blocks is 159 µw and mm 2, respecively. Keywords Analog fron end, CMOS image sensor, sigma-dela modulaor, signal-o-noise raio, swich capacior circuis, gain boosed echnology, dynamic elemen maching a CIS wih he column ADC is shown in Fig. 1.The CISs consis of a pixel array, column parallel readou circuiry, a row decoder, biasing circuis, buffer memory and a correlaed double sampling (CDS) circui [2]. The sigma-dela modulaors (ƩΔMs) are usually employed as ADCs because of heir high resoluion a low frequencies. However, he usage of muliple operaional ransconducance amplifiers (OTAs) in ƩΔMs makes hem bulky and power hungry. Therefore, he boleneck for designing low power and small size ƩΔMs is o amend he OTAs. The consrain of hreshold volage V TH on scaling and low power consumpion has led o developmen of many low volage design echniques like level shifing echniques [4] or using floaing gae (FG) meal-oxide semiconducor ransisor (MOST) [5], sub-hreshold MOST [6] or bulk driven (BD) MOST [7]. Oher exensive echniques employed for low power and compac size ƩΔMs are OTA sharing beween wo sages [8], [9], and using inverers as OTAs [10 17]. However, hese echniques limi he dynamic range of ƩΔMs and conribue more noise. In [13], a ƩΔM is inroduced which employs inverers near-hreshold volage insead of convenional 1. Inroducion The developmen in ubiquious compuing and arificial inelligence over he las decade has led o a remarkable rise in he applicaion of CMOS image sensors (CISs). The scaling down of CMOS echnologies permis a large number of sensor array implemenaion on he same die, herefore he demand of low power and compac size analog-o-digial converers (ADCs) wih moderae speed has increased. The main design challenges for signal condiioning circui for CISs are: 1) low power consumpion, 2) miniaure size, 3) immune o noise and 4) he signal should be processed in a sable sae before sen o he elemery sysem [1]. The concepual block diagram of Fig. 1. Block diagram of large array CMOS image sensor [2]. DOI: /re CIRCUITS

2 520 M. BASHIR, S. RAO PATRI, K.S.R. KRISHNAPRASAD, A 159 µw, 4TH ORDER, FEEDFORWARD, MUTLI-BIT Ʃ MODULATOR OTAs. This modulaor provides a good performance bu consumes more curren. In [14], a class-c inverer is used insead of OTAs for low-volage, low-supply incremenal ƩΔM. For low power consumpion and small saic curren, he ransisors in inverer are operaed in sub-hreshold region. Due o he low dc gain of class-c inverers, he ƩΔM resuls in low performance, non-lineariies and leakage. In [15], a high hreshold volage ransisor inverer is employed o improve he performance of ƩΔM. The leakage issues are decreased using swiches wih charge proecion and re-arranged reference signal schemes. In order o improve he signal-o-noise raio (SNR) of ƩΔM, a gain boosed class-c inverer is employed for ƩΔM in [16]. The gain boosed echnology resuled in improvemen of gain of radiional class-c inverer o 83 db, bu resuls in degradaion of ƩΔM performance for high speed CISs applicaions. This issue can be resolved using a rese clock wih small offse class-c inverers. A behavioral model is also inroduced in ƩΔM in [16], which needs furher developmen for beer accuracy. In [18], a ƩΔM is repored using discree-ime (DT) passive loop filer, gives an accepable performance wih low power consumpion. The use of large capaciors in loop filers increases he overall size. In [19], a DT ƩΔM uses bulk driven echnique for implemening he OTA bu resuls in degraded performances in erms of signal-o-noise plus disorion raio (SNDR) and dynamic range (DR). This paper presens a fourh-order cascade (2-1-1), 3-bi, feed-forward (FF) ƩΔM wih dual inegraing scheme (DIS), implemened in 65 nm CMOS echnology a a supply volage of 1 V. From he frequency range of CISs signals, he proposed ƩΔM is designed for 100 khz signal bandwidh, however, can be used for oher lower frequencies wih minor adjusmens. The design of ƩΔM banks on he exhausive behavioral modeling ha involves boh he saisical and simulaion opimizaion a subsysem level. The res of he paper is organized as follows. Secion 2 discusses he archiecural consideraions, rade-offs relaed o ƩΔM specificaions using canonical equaions and a deailed op-down behavioral modeling for block level specificaions. In Sec. 3, he circui level implemenaion of ƩΔM is presened and is operaion is validaed hrough pos-layou simulaion resuls presened in Sec. 4. Lasly, Secion 5 gives he conclusion of he paper. 2. Sigma Dela ADC Archiecure 2.1 ƩΔ Modulaor Sysem Level Design Consideraions For higher resoluion and speed of he ƩΔ converers, he oversampling raio (OSR) should be small o resric he clock speed and hence he bandwidh of he inegraors [20]. Single-loop, one-bi ƩΔ converers exhibi good accuracy a higher filer orders. Unforunaely, he increase in filer order resuls in sabiliy issues a he modulaor oupu in erms of low frequency oscillaions and large ampliudes, leading o deerioraion of modulaor's SNR [21], [22]. Cascaded opologies employ higher-order noise shaping echniques and second order modulaor for beer sabiliy [21]. These opologies demand high block level specificaions for he reducion of noise leakage a he inpu of he modulaor, which makes hem power hungry and consumes large area. Now, for he enhancemen of he DR of ƩΔM, he resoluion of he embedded quanizers is increased. The muli-bi quanizer roughly reduces he in-band quanizaion noise power by 6 db for every addiional bi [21]. Conrary, o single bi quanizers, hey add complexiy o he design wih more analog circuiry. The proposed modulaor employs a cascaded mulibi ƩΔ opology for achieving a high DR wih low OSR. The 2-1-1, 3-bi ƩΔM uilizes OTA sharing echnique wih DIS in is firs loop for low power and area. The use of 3-bi quanizer improves he overall accuracy by 12 db as compared o single bi quanizer. 2.2 ƩΔM Archiecure Selecion The archiecure and he block level specificaions of Σ M are decided by behavioral modeling of he modulaor [21 23]. In his paper, an opimizaion based CAD synhesis ool, SIMulink-based SIgma-DEla Simulaor (SIM- SIDES) [21], is used for developing he opology for given specificaions. The archiecure for he given specificaions is chosen from he cascade opologies of ƩΔM, based on he (2 1 L 2 ) relaion, where L is he modulaor order. The blocks of he cascaded opology are generally described by hree parameers: Quanizer resoluion (B), OSR and L. Once hese parameers are found, Schreier s MATLAB Dela-Sigma oolbox [24] is used for finding he suiable opology. The in-band error power (IBE) of ƩΔM is expressed as follows [21] IBE PCN PQ Pnl P (1) s where P CN, P Q, P nl and P s are IBE power of circui noise, quanizaion error, non-lineariy errors and seling errors, respecively. The ƩΔM is designed in such a way ha: 2L 1 2V ref PCN Pnl Ps PQ B 2L1. (2) L1 OSR Moreover, as he signal bandwidh is moderae, OSR can be more flexible [21]. Based on (2), a fourh order, opology is he bes fi. The deailed behavioral block diagram of he cascaded muli-bi ƩΔM for 16 bi resoluion is shown in Fig. 2, in which he scaling facors of inloop inegraors are denoed by a i, b i, c i where i = 1,2,3... The firs loop acs as a second-order Σ M followed by he second and hird sage as firs-order Σ M. The SNR of Σ M is furher improved by replacing he single bi quanizer of he hird sage by 3-bi quanizer. For he proper operaion of Σ M, he following equaions mus be saisfied [21].

3 RADIOENGINEERING, VOL. 27, NO. 2, JUNE Kq 1aa 1 21, Kq1a22, K a 1, K a 1 q2 3 q3 4 where K q is he gain of quanizer. The coefficiens are properly chosen o limi he oupu of inegraors wihin 10% o 80% of he supply volage, when he Σ M is no overloaded. The Σ M can be considered as a wo-por sysem wih inpu (x,e) and oupu (y), ha can be represened in Z-domain by: Yz ( ) STFz ( ) Xz ( ) NTFz ( ) Ez ( ) (4) (3) where X(z) and E(z) are he Z-ransform of he inpu signal and quanizaion noise, respecively, and he STF(z) and NTF(z) are he signal ransfer funcions and noise ransfer funcions. The firs hree scaling facors are chosen arbirarily and ohers are calculaed o map he corresponding STF(z) and NTF(z) in Z-domain. The overall ransfer funcion of Σ M is given by: Y( z) X( z) z 1 b1 11 z 1 b2 11 z. (5) z 1 z 1 b2 11 z c z cc 1 2 a 1 z 1 z 1 1 a 2 z 1 z 1 1 b 1 1 a a 1 2 c 1 a 3 z 1 z b 2 1 a3 c 2 a 4 z 1 z Fig. 2. Block diagram of he fourh-order cascaded bi feedforward Σ M.

4 522 M. BASHIR, S. RAO PATRI, K.S.R. KRISHNAPRASAD, A 159 µw, 4TH ORDER, FEEDFORWARD, MUTLI-BIT Ʃ MODULATOR Specificaions for: Modulaor Opamps Resisors Comparaors A/D/A converer Inegraor 0 Sampling frequency [MHz] Oversampling raio Supply volage [V] Differenial oupu swing [V] DC-gain [db] Oupu curren [ma] Swich-ON resisance [Ω] Offse [mv] Hyseresis [mv] Resoluion ime [µsec] Resoluion [bis] INL [%FS] bi, 100 khz signal bandwidh Inegraor 1 Inegraor 2 Inegraor ± Tab. 1. Block level specificaions of 2-1-1, 3-bi Σ M. Fig. 3. (a) Variaion of SNR wih DC gain of A0 and inpu signal ampliude. Fig. 3. (b). Variaion of SNR wih DC gain of A0 and A1. Fig. 3. (c) Variaion of SNR wih DC gain of A0 and A2. Fig. 3. (d) Variaion of SNR wih DC gain of A1 and A2.

5 RADIOENGINEERING, VOL. 27, NO. 2, JUNE Block-Level Specificaions (High Level Sizing) Afer he archiecure of modulaor is decided, he given specificaions (resoluion and signal bandwidh) of modulaor are mapped for he elecrical specificaions of differen sub-circuis, like amplifiers, swiches, comparaors and passive elemens like resisors and capaciors. The behavioral model of ƩΔM for 16 bi resoluion wih 100 khz signal frequency is implemened in SIMSIDES and is simulaed for ime (N 1)T s, where T s is he sampling ime and N is he number of levels. The model developed includes all he non-idealiies associaed wih he quanizer such as hose of swiched capacior (SC) circuis and comparaors. For he calculaion of DC gain, slew rae, oupu swing and maximum curren o be driven hrough OTAs, he DC gain of OTAs are varied agains each oher for he desired SNR. Figure 3 shows he 3-dimensional plos of SNR as a funcion of differen OTAs DC gain, where A0, A1 and A2 represen he DC gain of Inegraor 0, Inegraor 1 and Inegraor 2, respecively, and Ain is he inpu signal ampliude (in vols). Based on he resuls obained from behavioral model of cascaded 2-1-1, 3-bi Σ M, he block level specificaions are summarized in Tab. 1. The loop coefficiens of Σ M deermined from he capacior raios are given in Tab. 2. Coefficiens Values Coefficiens Values a 1 =a b 2 1 a 3 =a c b c Tab. 2. Summary of loop coefficiens. 2.4 Proposed Σ Modulaor A fourh-order cascade FF Σ M composed by a second-order FF Σ M and wo firs-order Σ M is proposed, as shown in Fig. 4. The benefis of employing FF a sysem level are: 1) Signal ransfer funcion (STF) is uniy; 2) Building blocks are less sensiive o non-idealiies; 3) Inernal signal swing is reduced; 4) Overload level ges improved, hus improving he DR and, 5) reduced complexiy of Σ M [25]. The inernal swing is furher reduced by employing a 3-bi quanizer, hus relaxing he gain requiremens of OTAs. A fully differenial swiched capacior is used for implemenaion of Σ M, because of is large DR and immuniy o surrounding noise. I consiss of wo non-overlapping phases ɸ 1 and ɸ 2, followed by delayed versions of ɸ 1 and ɸ 2 (ɸ 1d and ɸ 2d ) for he reducion of charge injecion effecs in swiched capacior circuis. During ɸ 1, he inpu signal is sampled hrough he sampling capacior (C 1 ) and in phase ɸ 2, he charge is ransferred o inegraion capacior (C 2 ) for inegraion. A symmerical volage reference +V ref and V ref, where +V ref = 1 V and V ref = 0 V, are used o minimize he effec of feedback levels on he DR of modulaor. The swiches are implemened using CMOS ransmission gaes. The ON-resisance of CMOS ransmis- Signals Noaions Signals Noaions ɸ 1 1 ɸ 2 2 ɸ 1d 3 ɸ 2d 4 ɸ S1 5 ɸ S2 6 Tab. 3. Clock signal represenaion in Fig. 4. sion gae warrans a rail o rail operaion as long as V DD V SS > V TN + V TP. The sizing of nmos and pmos ransisor is done appropriaely for smaller on-resisance o limi he harmonic disorion of Σ M. The Σ M employs hree non-invering, parasiic insensiive delaying swiched capacior inegraors (SCI), for he reducion of double seling problem. The wo SCIs used in he firs loop of he Σ M are embedded ino uni SCI using he echnique of opamp sharing, hus reducing overall area and power. As shown in Fig. 4, he firs and second inegraors are represened by he upper and lower sides of he shared inegraor. The use of shared opamp affecs he lineariy of Σ M due o he residual charge sorage a he inpu parasiics a he OTA [9]. However, due o he high performance of he shared opamp, i does no suffer from he residual charge. The inegraors used in he proposed Σ M employ sampling capaciors (C i,a/b, where i = 1,2,3...) and swiches o perform he double sampling (DS) of inpu analog signal, as shown in Fig. 4. The sampling and inegraion operaions are performed by using slow ime-inerleaved clock signals of ɸ 1 and ɸ 2 (ɸ S1 = ɸ 1 /2 and ɸ S2 = ɸ 2 /2). However, he DAC circui employed in he feedback pah consiss of single sampling capaciors and swiches operaing a nominal sampling frequency (ɸ 1 ). As he mos criical blocks of Σ M operae a ɸ 1 /2, he GBW produc and gain requiremens of OTAs are relaxed compared o convenional OTAs, herefore reducing he power consumpion. For higher lineariy of Σ M, a memory-less reurn-o-zero scheme is used for 1-bi feedback DAC [21]. The differen clock signals along wih heir non-overlapping signals represened in Fig. 4 correspond o he signals given in Tab. 3. Insead of using convenional opamps for A2 and A3, a pseudo differenial class C inverer wih gain boosed echnology is realized as an amplifier in SC circuis. In comparison o convenional opamps, no virual ground is provided by he PDI because of is only inpu. Insead, he inpu node of inverer is kep near he offse volage (V off ) by forming a closed loop as follows: A V V V V inv C1 inv off off 1 Ai nv 1 Ainv where V inv is he inpu volage of inverer, A inv is he inverer dc gain, and V C1 is he volage a capacior C 1. During phase ɸ 2, he charge ransferred hrough C 1 is C 1 (V 1 V off ), where V 1 is he inpu signal. An auo-zeroing echnique can be employed o cancel he offses by forming a virual ground. The gain boosed PDI configuraion of SCI avoids he requiremen of common-feedback (CMFB) (6)

6 524 M. BASHIR, S. RAO PATRI, K.S.R. KRISHNAPRASAD, A 159 µw, 4TH ORDER, FEEDFORWARD, MUTLI-BIT Ʃ MODULATOR Fig. 4. Schemaic of he FF Σ M. circuis a low supply volages [26]. During phase ɸ 1, he CMFB capacior (C M ) ges discharged o signal ground level whereas in phase ɸ 2, he C M ges charged o commonmode volage (V CM ). The CMFB loop is realized by applying he difference beween V CM and signal ground o he inegraor. 3. Circui Level Implemenaion The Σ M is generally inegraed on a chip surrounded by housands of ransisors, resuling in leakage issues, increased power consumpion and harmonic disorion [27]. A low-leakage wih high hreshold volage (LL_HVT) ransisor echnology is used insead of ransisors wih sandard performance (SP). The LL_HVT resuls in less leakage curren as compared o he SP 65 nm CMOS package. From Tab. 2, a convenien opology for each sub-circui, i.e., OTA, comparaor, swiches and passive elemens are chosen o mee he specificaions a circui level. The seleced circui opologies are analyzed and he impac of emperaure variaions, echnology corners and supply volage are aken ino consideraion. For he correc operaion of he Σ M circui, he wors case performances of differen sub-blocks are considered. The operaion of sub-circuis of proposed Σ M is discussed as follows. 3.1 Opamps The oal in-band error power conribued by A2 is aenuaed in he signal band by he gain of fron end inegraor (A0) [21]. Therefore, he performance of A0 is more

7 RADIOENGINEERING, VOL. 27, NO. 2, JUNE demanding han A1. Thus, he power consumpion can be reduced by designing A2 wih relaxed specificaions. The A0 is implemened using a fully differenial, hree sage opamp [28] for low power supply (1-V), as he noise consrains are easily me by is oupu swing (>70% of V DD ) wih swiched capacior common mode feedback (SCCMFB) circui. The schemaic of hree sage opamp (A0) is shown in Fig. 5. The common-source amplifier used a he second and he hird sage does no limi he oupu curren by bias curren, and provide high slew rae (SR) wih low saic power consumpion. The sizing of compensaion devices R C1, R C2 and C C1, C C2 are done so ha a phase margin of a leas 70 is achieved during inegraion phase. During he second phase he loop gain ges increased by (1 + C 1a /C I ) imes and he load capaciance increases from During ɸ 1 Beginning of ɸ 2 Operaion Transisor condiion Boh he ransisors are in weak inversion region. V i 0 PMOS is in srong inversion region and NMOS is cuoff in region. Fig. 5. A fully differenial 3-sage opamp wih SCCMFB circuiry used a he firs sage. V i 0 PMOS is in cu-off region and NMOS is in srong inversion region. During ɸ 2 Boh he ransisors are in weak inversion region. Tab. 4. Operaion of class-c inverer a differen clock phase. Fig. 6. AC performance of A0. C L = C I C 1a /(C I + C 1a ) o C L = C I + C 1a o resuling in improvemen in gain bandwidh (GBW) produc. The robusness of A0 o mismach and process variaions is analyzed by doing Mone Carlo simulaion over 1000 runs (3 sigma inerval). The A0 has a DC gain of 76 db, 72 phase margin, 202 MHz GBW produc and consumes a power of 85 µw. Figure 6 shows he AC performance of A0 wih a capaciive load of 1 pf. Due o he relaxed specificaions, he res of OTAs (A2 and A3) are realized using gain boosed PDIs. For he sake of simpliciy, he gain boosed circuis are no discussed [16]. For a higher dc gain and GBW produc, he

8 526 M. BASHIR, S. RAO PATRI, K.S.R. KRISHNAPRASAD, A 159 µw, 4TH ORDER, FEEDFORWARD, MUTLI-BIT Ʃ MODULATOR inverer is operaed a he boundary of riode and sauraion region, which are realized by using LL_HVT ransisors having heir collecive hreshold volage (V TN + V TP ) equal o supply volage [29]. The operaion of class-c inverer is divided ino hree sages, shown in Tab. 4. In phase ɸ 1, boh he ransisors are operaing in deep riode region, forming a feedback loop wih inpu offse volage (V X ). A he beginning of phase ɸ 2, V X changes o (V OFF V 1 ) and one of he ransisors of inverer operaes in sauraion region while he oher in deep riode region, depending on V DD. Due o he negaive feedback, he charge is ransferred hrough C 1 making V X = V OFF again. A he compleion of phase ɸ 2, boh he ransisors operae in deep riode region. The inverer provides a large dc gain when operaed in deep riode region and a higher slew rae wih small saic curren is achieved wih eiher of he ransisors is working in inversion region. As he class-c inverer has low shor circui curren, he seling ime ges miigaed by ~70%, wihou increasing he saic curren. The AC performance of A2, including process variaion and componen mismaches, is shown in Fig. 7. The A2 has an average DC gain of 48 db, a phase margin of 87 and GBW of 78 MHz. The overall ransisor sizing and elecrical performances of boh A0 and A2 are summarized in Tab. 5 and Tab. 6, respecively. The minimum lengh ransisors are avoided o reduce he flicker noise and mismach effecs. A0 Transisors W/L [µm/ µm] Componen Value M 1 = M 2 9.2/0.3 C C 750 ff M 3 = M 4 0.3/0.3 C ff M 5 2/0.3 C ff M 6 5/0.3 5 R C1 2.4 MΩ M 7 13/0.3 S MΩ M 8 7/0.3 2 S MΩ M 9 15/0.3 2 I bias 30 µa A2/A3 Transisors W/L W/L Transisors [µm/ µm] [µm/ µm] M 1 7/0.3 M 2 16/ Tab. 5. Sizing of OTAs. A0 A2/A3 Parameer Worscascase Wors- Typical Typical DC gain [db] Phase Margin [deg] GBW [MHz] Slew Rae [V/µsec] Oupu swing [V] 0.98 ~ Oupu capaciance [pf] Eq. inpu noise [ nv / Hz khz Power consumpion [µw] Tab. 6. Simulaion resuls for he A0 and A Comparaor Mos of he non-idealiies associaed wih comparaors are deal during he noise shaping by loop filers. The design specificaions of comparaor are obained from Tab. 1. The hyseresis and offse can be oleraed bu he comparison ime mus be a leas 1/4 of he clock speed, i.e. 6.4 MHz [21]. In order o aain he required resoluion ime and hyseresis, a single bi quanizer, shown in Fig. 8, is realized using convenional dynamic comparaor. The comparaor resuls in small saic power dissipaion, high inpu impedance and is immune o noise and mismach effecs [30]. The operaion of comparaor depiced in Tab. 7. The oal delay ( delay ) of he comparaor is given by he expression [30]: Fig. 7. AC performance of gain boosed class-c inverer. 2C V C V I L TP L DD ail delay ln Iail g m-eff 4 VTP Vin 1,2 where C L is he load capacior, I ail is ail curren flowing hrough ransisor M 2, g m-eff is he effecive ransconducance of back o back inverers, ΔV in is he inpu difference volage and β 1,2 is he curren facor of inpu ransisors (M 1 (7)

9 RADIOENGINEERING, VOL. 27, NO. 2, JUNE CLK OUT - M 7 V DD M 5 M 6 M 8 OUT + CLK and M 2 ). The ransien response of he comparaor is shown in Fig. 9. The ransisor sizing and he elecrical resuls of he comparaor are summarized in Tab. 8 and Tab. 9, respecively. C L M 3 M 4 C L 3.3 Clock Generaor V IN + V IN - M 1 M 2 CLK M Tail Fig. 8. Schemaic of convenional dynamic comparaor. Phase CLK signal Operaion Resuls Rese phase CLK = 0 Comparison phase CLK = V DD M Tail = OFF M 7 and M 5 are ON M Tail = ON M 7 and M 5 are OFF Boh oupu nodes are precharged o V DD, i.e. OUT + = OUT = V DD Oupu nodes sar discharging. For V IN+ > V IN- : OUT + = V DD and OUT = 0 For V IN+ < V IN : OUT + = 0 and OUT = V DD The non-overlapping clocks ɸ 1 and ɸ 2 are imporan for he opimal operaion of SC Σ M. In order o reduce he effec of clock feedhrough signals, delayed clock signals of ɸ 1 and ɸ 2 (ɸ 1d and ɸ 2d ) are given o he swiches a he inpu erminals of modulaors [20]. The schemaic of clock generaor wih he clock phase schemes are shown in Fig. 10. To avoid he capaciive loading of he differen signals, all clock signals are buffered. Figure 11 shows he swiching characerisics of generaed clock signals. The phase delay and non-overlapping ime are 497 psecs and 240 psecs, respecively bi Quanizer A he end of he hird sage of modulaor, a 3-bi quanizer is implemened for digiizaion of A3 oupu and hen conversion o analog domain. The 3-bi quanizer, shown in Fig. 11, uses a differenial flash quanizer wih resisor ladder DAC [21]. The differenial flash ADC com- Tab. 7. Operaion of dynamic comparaor a differen clock phase. Fig. 9. Transien response of convenional dynamic comparaor. Transisors W/L W/L Transisors [µm/ µm] [µm/ µm] M 1 = M 2 0.3/0.3 M 7 = M 8 6/0.3 M 3 = M 4 2/0.3 M Tail 18/0.3 M 5 = M 6 10/0.3 C L 300 ff Tab. 8. Sizing of comparaor. Parameer Typical Wors-case Hyseresis [µv] Offse [µv] Low-high resoluion ime [psecs] High-low resoluion ime [psecs] Power consumpion [µw] Tab. 9. Simulaion resuls for he comparaor. 1 (V) d no d no d (ime) Fig. 10. Schemaic of clock generaor wih he clock phase schemes.

10 528 M. BASHIR, S. RAO PATRI, K.S.R. KRISHNAPRASAD, A 159 µw, 4TH ORDER, FEEDFORWARD, MUTLI-BIT Ʃ MODULATOR Fig bi quanizer. pares he inegraor (A2) oupu wih he volages generaed a differen resisors in he resisor ladder. The quanizers employ he same comparaors discussed above. The hermomeer code from he comparaor oupu is convered ino a 1-of-8 code (d 0-7 ), which conrols he resisor ladder DAC. The resisor ladder uses 8 resisors conneced beween V DD and gnd, hus giving a full-scale of 1-V wih a curren consumpion of 35 µa. Fig. 12. Layou of 2-1-1, 3-bi Σ M. 4. Resuls and Discussion The 2-1-1, 3-bi Σ M is implemened in 65 nm CMOS sandard process, having an esimaed area of mm 2, excluding inpu/oupu pads, as shown in Fig. 12. The chip layou has separae analog, digial and mixed supplies, where every secion is surrounded by guard rings. Major aenion is given o he area of SCI, digial cells and oher auxiliary circuis. Alhough, he Σ M chip is fully differenial, opimizaion echniques like common-cenroid, symmery and dummy ransisors were used o reduce he common-mode inerferences. Boh digial signals (DAC conrol and clock signals) and analog supplies are roued using buses ha surround he criical analog blocks for shielding hem from noise inerferences. The Σ M has a power consumpion of 159 µw, including band gap reference (BGR) and clock generaors. The disribuion of power and area consumed by he major pars of Σ M is shown in Fig. 13 and Fig. 14, respecively. The performance of Σ M is evaluaed a wors-case hrough muliple pos-layou simulaions a ransisor level in CADENCE environmen. The poin fas Fourier ransform (FFT) specrum for he ƩΔM wih a pre-amplifier of 10 db gain and he resul summary are given in Fig. 15 and Tab. 10, respecively. Figure 16 shows he SNR and SNDR versus he normalized inpu ampliude. To measure SNDR and SNR of he modulaor effecively, he inpu ampliude was increased by 10 db from 85 db o 10 db, hen by 1 db from 10 o 0 db o obain more deailed daa. Wih an inpu sinusoidal signal of 51.1 khz for a signal bandwidh of 100 khz, he Σ M offers and SNR and SNDR of 92 db and 89 db, respecively. The Fig. 13. Disribuion of power consumpion. Fig. 14. Disribuion of area consumpion. Fig. 15. Dynamic performance of Σ M. effecive number of bis (ENOB) is equal o 14.49, given by (SNDR 1.76)/6.02. The clock frequencies of 3.1 MHz and 6.4 MHz are supplied using on-chip clock generaors.

11 RADIOENGINEERING, VOL. 27, NO. 2, JUNE Fig. 16. SNR and SNDR vs. inpu signal ampliude a 51.1 khz. Parameer Value Technology [nm] 65 (LL_HVT) Supply Volage [V] 1 OSR 32 Signal Bandwidh [khz] 100 Sampling frequency [MHz] 6.4 SNDR [db] 89 SNR [db] 92 ENOB Area [mm 2 ] Power Consumpion [µw] 159 FOM 1 [fj/conv. sep] 34.5 Tab. 10. Performance summary. Fig. 18. Performance comparison of bandwidh versus FOM 1. A performance comparison of presened Σ M wih oher sae of ar Σ Ms is given in Tab. 11. The figure of meri (FOM) for Σ M is defined as: Power _ Consumpion FOM1. (8) ENOB 2 2BW From Tab. 11, he variaion of DR wih BW, BW wih FOM 1 are shown in Fig. 17 and Fig. 18, respecively. I is concluded ha he presened Σ M has an overall FOM higher han he relaed recen Σ Ms. Fig. 17. Performance comparison of bandwidh vs. dynamic range. 5. Conclusions In his paper, a 2-1-1, 3-bi FF Σ M employing DIS a he firs sage is realized using 65 nm CMOS sandard process wih a power supply of 1-V for CIS applicaions. The Σ M oversamples an inpu signal of 100 khz bandwidh a 32 imes. Due o he OTA sharing in he firs loop and he usage of gain boosed, pseudo-differenial class-c inverers for he res of OTAs, he Σ M resuls in low power and area consumpion. The Σ M resuls in an ENOB of 14.49, SNR of 92 db and SNDR of 89 db, while consuming an area and power of mm 2 and 159 µw, respecively. The pos-layou resuls confirm ha he presened Σ M can be used in various low-power, high resoluion CIS applicaions. Specificaions This Work* [10] [12] [13] [14] [15] [16] [17]* Year Process [nm] Supply Volage [V] Signal Bandwidh [khz] ENOB SNDR [db] Power [µw] Core Area [mm 2 ] FOM 1 [fj/conv. Sep] * Pos-layou simulaed resuls. Tab. 11. Performance comparison wih relaed works.

12 530 M. BASHIR, S. RAO PATRI, K.S.R. KRISHNAPRASAD, A 159 µw, 4TH ORDER, FEEDFORWARD, MUTLI-BIT Ʃ MODULATOR Acknowledgmens This work has been performed using he resources of he Mixed Signal Design Laboraory a he Dep. of Elecronics and Communicaion Engineering, Naional Ins. of Technology Warangal, Telangana under Special Manpower Developmen Program Chip o Sysem for VLSI design and relaed sofware (SMDP-C2S) projec funded by he Dep. of Informaion Technology, Minisry of Elecronics and Informaion Technology, Governmen of India. References [1] OHTA, J. Smar CMOS Image Sensors and Applicaions. 1 s ed. CRC Press, Sep. 2007, p ISBN: [2] ANNEMA, J., NAUTA, B., VAN LANGEVELDE, R., e al. Analog circuis in ulra-deep-submicron CMOS. IEEE Journal of Solid-Sae Circuis, Jan 2005, vol. 40, no. 1, p DOI: /JSSC [3] WANG, A., CALHOUN, B. H., CHANDRAKASAN, A. P. Sub- Threshold Design for Ulra Low-Power Sysems. New York (NY, USA): Springer, ISBN: [4] HASLER, P., LANDE, T. S. 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13 RADIOENGINEERING, VOL. 27, NO. 2, JUNE Circuis, 2002, vol. 37, no. 12, p DOI: /JSSC [28] SUADET, A., KASEMSUWAN, V. A CMOS inverer-based class AB pseudo-differenial amplifier wih curren-mode commonmode feedback (CMFB). Analog Inegraed Circuis and Signal Processing, 2013, vol. 74, no. 2, p DOI: /s [29] WICHT, B., NIRSCHL, T., SCHMITT-LANDSIEDEL, D. Yield and speed opimizaion of a lach-ype volage sense amplifier. IEEE Journal of Solid-Sae Circuis, July 2004, vol. 39, no. 7, p DOI: /JSSC [30] GOLL, B., ZIMMERMANN, H. Comparaors in Nano CMOS Technology. New York (USA): Springer, ISBN: [31] CARUSONE, T. C., JOHNS, D., MARTIN, K. Analog Inegraed Circui Design. 2 nd ed. New York (USA): Wiley, ISBN: Abou he Auhors Mudasir BASHIR received his bachelor s degree B.Tech in Elecronics and Communicaion Engineering from Punjab Technical Universiy in he year 2012 and maser s degree M.Tech in Elecronics and Communicaion Engineering from Shri Maa Vaishno Devi Universiy Kara, J&K in He is currenly working owards his Ph.D degree a Chips Design Cenre, Dep. of Elecronics and Communicaion Engineering, Naional Ins. of Technology Warangal. His research ineress include on-chip compressed sensors, sensor inerfaces and daa-converers. Sreehari RAO PATRI obained his bachelor s degree B.Tech in Elecronics and Communicaion Engineering from Nagarjuna Universiy in he year He received his maser s degree in Communicaion Sysems from he Indian Ins. of Technology Roorkee in he year 1995, Ph.D from he Naional Ins. of Technology Warangal in 2008 and is currenly working as an associae professor a he Dep. of Elecronics and Communicaion Engineering, Naional Ins. of Technology Warangal. Mr. Rao research areas are design of power managemen ICs under low power and low volage environmens and on-chip sensor inerfaces. He is a senior IEEE member. K. S. R. KRISHNA PRASAD received B.Sc degree from Andhra Universiy, DMIT in Elecronics from MIT, M.Tech in Elecronics and Insrumenaion from he Regional Engineering College, Warangal and Ph.D from he Indian Ins. of Technology, Bombay. He is currenly working as a Professor a he Dep. of Elecronics and Communicaion Engineering, Naional Ins. of Technology, Warangal. Prof. Prasad s research ineress include analog and mixed signal IC design, biomedical signal processing and image processing.