Fully Integrated DC-DC Buck Converter

Transcription

1 1 Fully Inegraed DC-DC Buck Converer Carlos Eldio Azevedo, João Caldinhas Vaz and Pedro Sanos Insiuo Superior Técnico, Av. Rovisco Pais 1, , isbon, Porugal Absrac - This disseraion presens he design and Index Terms Buck converer, compensaor, fully-inegraed, high-frequency, efficiency, PSS, PAC, PSTB. I. INTRODUCTION T The inegraion of a dc-dc converer operaing a very high frequency brings several challenges o power managemen inegraed circuis. The main goal of his disseraion is o explore, design and implemen a fully inegraed inducorbased buck converer using sandard CMOS 0.13µm echnology from UMC, operaing a very high frequency, wihou resoring o exra processing seps or expensive posfabricaion process like hick film inducors, sacked chips and bond-wires inducors. As sabiliy analysis is imporan for swiching converers and any sysem wih negaive feedback, a careful invesigaion in he converer loop gain and compensaor will be done using Specre Periodic Seady Sae Analysis o design he conroller. This ype of analysis is suiable for swiching converers because of heir ime-varying naure and because i is possible o ener ino accoun wih all parasiic effecs on he circui (parasiic capaciance, bonding-wires, rack and inerconnecions resisances), unlike he radiional average models, like sae-space-modelling ha ignores some of hem. A special aenion will be given also o he power sage, including he driver secion, power devices and inducor, because hey are a key secion, which deermines he efficiency, ripple and noise of he converer. Vin Q1 Conrol implemenaion of a fully inegraed inducor-based dc-dc converer operaing a very high frequency. The sysem is implemened wih a synchronous buck converer opology, using sandard CMOS 0.13µm echnology from UMC, wihou resoring o any exra processing seps or expensive pos-fabricaion process such as hick film inducors, sacked chips and bond-wires inducors. The implemened sysem is capable of convering an inpu volage from 2.8V o 3.6V ino an oupu volage of 1.2V a 518MHz. The buck converer can supply an oupu power of 90mW up o 150mW wih an efficiency of 30%. An oupu ripple of 85mV was achieved I Vlx Vou O Q2 CO RO Figure 1: Schemaic of he implemened buck converer II. STEADY-STATE ANAYSIS The seady-sae analysis is done for he operaion in he CCM. For he seady-sae analysis he principles of inducor volsecond balance and capacior charge balance applies. These are used so ha he soluion for he inducor currens and capacior volages of he converer can be derived. Anoher useful approximaion is he linear ripple approximaion ha faciliaes he seady sae analysis. From his poin on i will be possible o derive he filer elemens of he converer. Seady-sae means ha he inpu volage, oupu volage and duy-cycle are no varying wih ime. For he ime being i is assumed ha he power swiches are ideal and here are no losses in he converer as well no parasiic effecs. Therefore, he duy-cycle and consequenly he oupu volage, is given by: (1) Clearly one can see ha he oupu volage varies linearly wih he duy-cycle of he power devices. ooking a he buck converer, we can ge he differenial equaion ha describes he curren in he inducor for he on-sae 0 < < on: (2) A same ime if we analyze he waveforms in figure 2, assuming seady sae, we can realize ha he curren a i(δtsw) = imax, meaning ha i suffers an incremen of Δi, relaively o he curren a i (0) = Imin wih Δi = Imax Imin. Neverheless, inegraing boh sides of equaion (2), in ha ime inerval, he soluion can be given as:

2 2 Because he average curren ha flows ino he inducor is he same as he one ha goes o he load, we can calculae he average curren inducor as: (3) v() Vin - Vou (9) On Sae Off Sae δtsw (1-δ)Tsw Vin - Vou (a) - Vou Tsw - Vou i() The expression for he maximum and minimum currens ha flows in he inducor can be now esablished. The minimum curren a he inducor, Imin=i (0), can be found by subracing half of he oal variaion of he curren ΔI o he average curren of he inducor, which leads o: Imax (10) Δ I Imin I=Io δtsw (1-δ)Tsw And in he analogous way, Imax=i(δTsw), can be found by summing half of he oal variaion of he curren ΔI o he average curren of he inducor: (b) Figure 2: Deailed CCM operaion of he synchronous buck converer. Where i(0) is he iniial curren a he sar of he inerval. The inducor curren will be maximum as = on. A ha ime, Imax is: (4) Now, considering he off-sae, where on < < off, when he high-side swich is off, he curren in he inducor complees is pah hrough he low-side swich. Therefore, he equaion ha describes he curren in he inducor is: (11) For an addiional undersanding refer again o figure 2. As menioned before, he buck converer can operae in he DCM under cerain condiions. A brief descripion of he origins of his conducion mode are explained and he duycycle conversion raio is derived. v() δsw2tsw Vin - Vou δsw1tsw - Vou (5) δdtsw Inegraing boh sides of equaion (5), in ha ime inerval, he soluion is given as: (6) Where i(0) is he iniial curren a he sar of he inerval. The inducor curren will be minimum as = off. A ha ime, imin is: (7) From (3) and (8) he incremenal (curren ripple) expression can be found o be: (8) i() Imax Vin - Vou (a) - Vou Δ I (b) Figure 3: Deailed DCM operaion of he synchronous buck converer. While in he CCM he inducor curren never goes o zero, he DCM is characerized by he inducor curren going o zero during one porion of he swiching cycle. This affecs grealy he properies of he converer, as for an example, he conversion raio becomes load dependen. Some issues regarding he converer dynamics are also alered bu i is a opic ou of he scope of his work. Typically his mode occurs

3 3 when we are in presence of large inducor curren ripple and operaing a ligh load, ha is, he converer is supplying a low oupu curren. Since i is usually required ha converer operae wih heir load removed is normal o find hem working under his condiion. As illusraed in figure 3, here are now hree sub-inervals during he swiching period Tsw. In he sub-inerval δsw1tsw, he high-side swich conducs, charging he inducor and he capacior while feeding he load a same ime. The curren increases from zero up o his maximum value Imax. In he nex sub-inerval δsw2tsw, he low side-swich conducs. This ime he elecromagneic energy sored in he inducor is discharged ino he oupu capacior and he load, causing he inducor curren o decrease from is maximum value o zero. Finally, he remainder of he swiching period, δdtsw, neiher he high-side nor he low-side swiches conduc, prevening I o become negaive as can be shown in he figure below. I SW2 (16) v() Vin - Vou On Sae Off Sae δtsw (1-δ)Tsw Tsw - Vou V Supposing ha he oupu capacior is assumed o be large enough and consan, ΔVo << Vo, as well as all he ripple componen in he inducor curren flows hrough he capacior, we ge: (15) This means ha he minimum filer capaciance required o reduce he ripple volage bellow he specified value is: (a) IO i() C Imax R ΔQ ΔI/2 Imin Figure 4: Equivalen circui for he dead-ime sub-inerval conducion. I=Io Tsw/2 δtsw (1-δ)Tsw (b) Afer his sub-inerval, every sep will be repeaed. Wih a few modificaions, he same echniques and approximaions developed for he seady-sae analysis of he CCM can be applied for his case, where he new dc volage ransfer funcion is given by: vc() Vo ΔVo δtsw (1-δ)Tsw (c) (12) Inroducing a new degree of freedom, ye wih high inducor curren ripple. In his relaion i is possible o verify ha Vo/Vin<1. Assuming he CCM, from (5) we can find he inducor value ha guaranees a cerain inducor curren variaion equals o ΔI: (13) As one can realize from figure 5, when he high-side swich is closed, ha is, from 0 < < on, he charge variaion ΔQ supplied o he capacior corresponds o he area of he riangle wih base Tsw and heigh Δi/2: (14) Figure 5: A represenaive view of he buck converer oupu volage ripple and inducor curren ripple, for he calculaion of he oupu capacior. Regarding he efficiency and he power losses in a dc-dc converer is of grea imporance when designing a converer, which means ha a poor efficiency will be ranslaed ino an excessive power dissipaion and consequenly a considerable power wase. In a dc-dc converer he mos imporan losses are relaed o he saic and dynamic losses. Saic power losses include he inducor, power swiches, bonding-wire sray resisance, ec. The dynamic losses basically comprise he swiching losses because of he charge and discharge of parasiic capaciances in he power devices. This phenomenon occurs due o he hard swiching even, where he curren flows ino he device, in is urn on even, before he volage across him collapses, as is roughly illusraed in figure 6. This ype of losses is proporional o he swiching frequency.

4 4 IDS VDS (22) Figure 6: MOSFET hard-swiching represenaion The firs source of losses o be analyzed is he conducion loss. The conducion losses basically occur when he high-side and low-side swiches are in he conducion mode. They are calculaed as he produc beween he square of he ransisor RMS curren value and is equivalen on-resisance. The expression ha models his resisance is obained by he quadraic-model of he MOSFET ransisor considering ha i is operaing in he riode region wih a low VDS volage: III. DC-DC CONVERTER SYSTEMIC DESIGN A. Power-Sage Design The implemened synchronous buck converer consiss on he volage-mode conrol using he pulse-widh echnique since he load curren will be high enough o make he inducor curren operae in he CCM. (17) Figure 7: Represenaion of he overall power sage block. And (18) Wih βn=knw/ and βp=kpw/ respecably and kn,p=µ n,pcox. However, i is imporan o ell ha hese equaions are more suiable o describe long channel MOSFETs. For shor channel ransisors, he models are far more complex o make hand calculaions and find only applicaion in compuaional simulaions. When he high-side swich is conducing he associaed conducion loss is given by: (19) Anoher source of losses is he parasiic resisance of he inducor, ESR. This loss can be calculaed as: (38) Where (20) Now regarding he swiching losses, hese comprise he I-V overlap losses in he swich and he fcv2 losses, which is direcly proporional o he swiching frequency. These losses are dominan a low load condiions. Moreover, hese losses accouns wih he urn-on and urn-off process. For sake of simpliciy he deailed mahemaical reamen will no be presened. Assuming ha he urn-on and urn-off imes are he same, he swiching losses can be represened as: (21) The global efficiency of he converer is found o be: In figure 7 i is presened he power sage of he buck converer implemened in his work. Based on he sysem specificaion given bellow, a firs approach for is design in made. Symbol Vin Vou Vou Iou I Fsw Parameer Inpu Volage Oupu Volage Oupu Volage Ripple Oupu Curren Inducor Curren Ripple Swiching Frequency Min Typ Max Unis V V mv ma ma MHz Table 1: Main specificaions for he implemened dc-dc buck converer. Regarding he oupu filer of he buck converer, a capacior of 5.1nF and an inducor of 13nH were deermined. Concerning he power swiches, hose can be designed for an opimal power loss making he conducion losses and swiching losses approximaely he same. The on-resisance of he power swiches consiues he major porion of he conducion losses along wih he inducor series resisance due o he fac ha he load curren passes in boh resisances each swiching cycle. For his reason i is imporan o minimize he on-resisance of he power swiches. However his implies large areas for boh high-side and low-side swiches and, a same ime, larger gae driver power consumpion. Due o his consrain, he decision fall upon he lowes on-resisance ha one could ge aking ino accoun he minimum area as possible This was deermined hrough a small-signal simulaion and he resul is depiced in figure 8, where i is shown he onresisance of boh swiches versus is widh.

5 5 Figure 1: Simulaion showing he power swiches on-resisance funcion of heir widh. The crieria o selec he appropriae power swiches widhs were based on simulaion and rading off is size wih he bes on-resisance achievable. The widhs for he high-side and low-side swiches were chosen o be 6000µm and 2000µm, respecively. This way we have he same on-resisance for boh swiches wih he NMOS swich being 3 imes smaller han he PMOS due o he higher elecron mobiliy. The lengh used for boh power swiches was he minimum acceped by he echnology. Table 1 summarizes he main specificaions for he power sage of he buck converer. Due o he large sizes of he power swiches, heir gae capaciances are very large and herefore a buffer sage made of inverers is needed o charge he parasiic capaciances of he ransisors. Thus, a chain of N inverers is used and can be scaled wih a consan apering facor u, such ha he raio of he average dynamic curren o load capaciance is equal for each inverer in he chain. Figure 3: The non-overlapping block consising in a wo NOR gaes and wo NOT gaes. This block is necessary o spli he PWM signal ino wo nonoverlapping signals ha drive he buffers of each power swiches. A same ime i generaes a fixed delay ensuring ha here is some dead-ime period beween each power swiches urn-on and urn-off period. Figure 4: The wo non-overlapped signals o be applied a he inpu of he drivers Figure 2: Power drivers consising on a chain of inverers. Finally, he non-overlap block was implemened using wo NOR gaes and wo NOT gaes as depiced in figure 10. B. Small-signal Analysis Modeling correcly he buck converer dynamic behavior is an imporan sep o analyze and design properly he closed-loop conrol especially o know how he oupu volage of he converer will respond o perurbaions in he inpu volage and load curren. A well-compensaed buck converer is crucial o mee he performance specificaion. However his is a difficul ask due o he non-linear ime-varying naure of he PWM which is working in a large signal mode. Neverheless, by using some modeling echniques i is possible o derive a coninuous ime-invarian linear model o represen he swiching converer and wih his overcame he problem. Being he sysem now a linear nework, i is possible o apply all he conrol heory o design he feedback conrol loop. For his work Specre simulaor was used o access he open loop frequency response of he converer and he loop sabiliy

6 6 analysis. This is possible due o o he Periodic Seady-Sae (PSS) analysis, in combinaion wih he Periodic Small-Signal AC analysis (PAC) or he Periodic Sabiliy Analysis (PSTB). This general mehod is suiable for any dc-dc swiching converer and he resuls are accurae comparing wih he average modeling echniques, even a high frequencies. The PSS analysis is a large-signal analysis, which direcly compues he periodic seady-sae response of he circui in he ime domain using he ieraive Shooing Newon mehod. This kind of analysis is frequenly used in RF simulaions, where he carrier is a periodic signal. For he case of he dc-dc converer, we have a similar siuaion. Thinking on he PWM block wih a fixed duy-cycle, he swiching frequency is consan, so he seady sae is periodic as well. Afer PSS analysis has finished, he small-signal perurbaions are applied using PAC or PSTB analysis o perform he frequency response of he converer and hen deermine openloop gain, closed loop gain, gain margin, phase margin and crossover frequency, also known as he closed loop sysem bandwidh. The inpu perurbaion is applied o he PWM duy-cycle and he oupu is he oupu volage perurbaion. This ype of analysis belongs o he large-signal / small-signal mehods and is very efficien for non-linear or swiched circuis excied by a large-signal plus a small-signal. A paricular case of his analysis is, for example, he incremenal sudy of an amplifier circui around a DC bias poin. In his case he large signal is he consan bias signal. Wih his kind of analysis all he relevan physical effecs in he power sage, like nonlineariies and reacive effecs, are aken ino accoun allowing a full assessmen of he loop sabiliy. C. Open-loop Frequency Response and Compensaor Design The PSS and PAC analysis are applied o he synchronous buck converer o deermine he open-loop frequency response of he buck converer. In order o design he feedback conrol loop, one mus know he conrol-o-oupu ransfer funcion of he power sage, ha is, he open loop gain of he buck converer. An ideal sawooh generaor was implemened using an ideal pulse generaor. The pulse widh modulaor was implemened using an ideal comparaor done wih a volageconroller volage source. The wo inpus of his comparaor are he sawooh generaor oupu and an ideal volage source ha simulaes he error volage ha comes from he compensaor. The circui is operaing a 500MHz and for an oupu volage around 1.2V he volage error was se o 1.24V. The oupu load of 16Ω gives an oupu load curren around 75mA. The open loop frequency response resul is presened below. Figure 12: Open loop frequency response of he implemened buck converer. In fac i may seem awkward his kind of resul because we are no seeing any effec of he ypical wo resonan poles from he oupu resonan ank filer, composed by he inducor and oupu capacior. This can be explained making reference o he inducor series resisance and he on-resisance from he power devices. This problem lowers down he Q value of he resonan ank. Afer he power-sage design and he open-loop frequency response evaluaed, he compensaor was designed. The objecive of he design of he compensaion nework is o shape he compensaor frequency response so ha in he closed-loop operaion he frequency response of he converer can be correc so ha when he loop gain cross he 0dB axis here is sufficien phase difference beween he error and he oupu signal. A same ime he compensaor mus provide high gain value in he dc frequency o reduce he saic error. This frequency difference referred above is normally called phase margin and i is usually chosen beween 45º and 60º as i was menioned in chaper 2, allowing good sabiliy and fas ransien response. Anoher equivalen parameer is he gain margin in which a value beween 10 o 15dB is a good arge. To design he compensaor a sabilizaion ool called k-facor was used. This approach consiss in deriving a number k based on he observaion of he open-loop Bode plo of he swiching converer o be sabilized. This k number will indicae he necessary disance beween he frequency posiion of he poles and zeros implemened by he compensaion nework. The frequency response of he obained compensaor is illusraed in figure 13.

7 7 Figure 13: Frequency response of he designed compensaor. The loop gain response of he designed converer in illusraed in he figure 14. Figure 14: Closed oop frequency response of he buck converer. The resuls from he loop gain analysis shows ha he closed loop sysem has a 62º of phase margin bu wih a uniy gain bandwidh of 13MHz. The ransien load response capabiliy of he oupu sage mus be made o assess he converer performance. The buck converer mus be able o respond o he load curren changes from a lower value o a higher value and vice-versa. When he load curren goes from a lower value o a higher value he oupu volage of he converer will emporarily decrease unil he converer is ready o adjus he duy cycle o bring he oupu volage o is reference value. When he load goes from a higher value o a lower value hen we have he opposie effec, he oupu volage ends o increase and recovers. I is imporan ha he buck converer can respond quickly o his changes in he oupu load. The same applies for he inpu volage variaions. Thus, a small sep load was performed for he nominal and boh baery inpu volage exremes o check he overall sabiliy of he sysem. The resuls are shown below. Figure 15: A 50mA sep load response wih exremes and nominal baery volage. From he analysis of he oupu volage ransien response for he load sep i is possible o conclude ha he buck converer is regulaing correcly and i is able o coninue regulaing he oupu volage afer a load sep. One can noice ha he value of undershoo varies approximaely beween 85mV and 100mV whereas he overshoo varies beween 80mV o 90mV. The converer presen a fas ransien response when he inpu volage is 3,7V and a wors ransien response a he minimum inpu volage. One can say ha he closed loop sysem is correcly designed and mees he specificaions. The ype II compensaion nework can give a good phase margin o ensure he sysem sabiliy and provide fas ransien response. Afer he converer sabilizaion he efficiency was evaluaed. The simulaions revealed ha he overall efficiency of he buck converer lies around 30% for a 16Ω load wih an oupu volage of 1.2V. The power loss in he non-overlapping circui is almos negligible. The power loss is more accenuaed in he power swiches and in he inducor represening almos 50% of he overall power losses. The main reason for his migh be relaed o he inducor series resisances, which has a value around 6Ω, since he power swiches has an on-resisance en imes smaller. The driver secion alhough conribues significanly for he power less is likely o be improved. IV. POST-AYOUT SIMUATION In his secion he pos-layou simulaions of he overall dc-dc buck converer is presened. For he pos-layou simulaions he bonding wires and PAD connecions were considered. I conains an inducances and a capaciance o he exernal ground erminal. The PAD model is supplied by he echnology design ki. Some of he used PADs are implemened wih ESD proecion (mosfe conneced as diodes) o proec he circui from any elecric discharge. The parasiic resisance and capaciances were exraced wih ASSURA resuling in a new circui conemplaing he effec of hose elemens. The parasiic inducance of 1.1nH/mm for he bond-wire connecion o ground was considered whereas for he power supply a parasiic inducance of 1.6nH/mm was considered. The reason o consider a small value of he parasiic inducance for he ground connecion is because he PCB es-board below he die will have a ground plane ha permis smaller bond-wires. The es bench o perform he

8 8 pos-layou simulaion is presened below. Besides he nominal operaion of he buck converer and heir respecive load sep, he corners analysis was performed for emperaures of -40ºC, +25ºC and +125ºC and ff, ss, snfp and fnsp corners for he ransisors. B. Transien Response for a oad Sep Figure 18: Pos-layou ransien response of he buck converer for a load sep of 50mA, from 75mA o 125mA. Figure 16: Pos-layou es bench used o perform he poslayou simulaion, including he pad connecion as well as he bonding wires. A. Nominal Condiion of Operaion Figure 19: Pos-layou ransien response of he buck converer for a load sep of 50mA, from 125mA o 75mA. Figure 17: Pos-layou buck converer operaing a 75mA nominal oupu curren wih. In he nominal operaion of he buck converer wih he RC exraced performed, one can noice ha here is a larger volage ripple when compared o he resuls before layou. Here a ripple of 85mV is visible, which corresponds o a 6% of he oupu volage. This oupu volage ripple can be relaed o he oupu capacior ha was implemened hrough an array of mosfes conneced as a capacior (MOSCAP). The pos-layou simulaion shows an undershoo of 161.3mV wih a ransien response of 131.1ns. This undershoo is almos wice he value obained for he load sep in he resuls before layou whereas for he ransien response he difference is 31.1ns. Regarding he overshoo, we can say ha is value is around 155mV wih a ransien response of 148.7ns. The resuls difference obained here migh be relaed o he parasiic effecs of he RC exracion. Despie he differences, he conroller is able o recover from he load sep wih a very accepable performance. C. Final Resuls Technology Analog Core Area Parameer Operaing Juncion Temperaure Supply Volage Oupu Volage Oupu Volage Ripple Oupu Curren Maximum Oupu Curren oad Transien Response UMC 130nm MM/RF 2.46mm2 Symbol Min Typ Max Unis Tj ºC Vin Vou V V Vo 85 mv Io 75 ma Iomax 125 ma Trlo < 150 ns Commens For a load sep of 50mA.

9 9 ine Transien Response Swiching Frequency Inegraed Inducor Inegraed Capacior Nominal Efficiency Trli Fsw DCR Cou ESR ηnom < µs For a line sep from 2.8V up o 4.2V. MHz nh Ω nf Ω % Efficiency a he nominal oupu volage 1.21V and curren 75mA. Table 1: Final characerisics Summary of he designed dc-dc buck converer. V. CONCUSION To he knowledge of he auhor, his is he firs fully inegraed dc-dc buck converer operaing a 500MHz employing volage-mode pwm conrol. A fully inegraed dc-dc buck converer operaing a very-high frequency in a volage mode conrol, o regulae he oupu volage, was presened and invesigaed for a CMOS 130nm echnology. The conrol sysem has proven o operae and regulae he oupu volage of he converer wih load variaion from 90mW up o 150mW over a power supply volage from 2.8V o 3.6. The full inegraion of he inducor was accomplished and i was demonsraed ha i is possible o fully inegrae such converer. An efficiency of 28.6% was achieved a nominal operaing condiion for a conversion raio from 3.3V o 1.2V aking ino accoun he non-idealiies of he swiches on-resisance and he parasiic resisance of he inducor. A considerable share of he converer power losses occur mosly in he driver secion of he power rain and in he series resisance of he oupu inducor filer. The bond-wire played an imporan role in he circui performance since hey influence he swiching behavior of he converer in a way ha he swiching nodes presen a superimposed resonance. A more accurae value for he meals resisiviy could cerainly lead o beer simulaed resuls for he efficiency, due o a lower value ha would be obained for he inducor DC resisance. A differen approach o he sudy of he sabiliy has been presened, using periodic seady sae simulaions from Cadence Specre simulaor. The obained resuls wih PSS plus PSTB analysis has proven o be accurae by successfully modeling he frequency response of he converer and compensaing he closed-loop feedback, insead of consrucing i equivalen linear circui. This mehod has he advanage o assess all he conrol loop parameers ha someimes are difficul o model, and because of ha negleced, like for example he on-resisance of he power swiches, he parasiic capaciances from each block, he oal delay of he sysem, ec. Some problems have arisen during he progress of his work. e s consider he sawooh generaor example. Afer he exracion of is layou parasiic elemens, he swiching frequency has seen is value decreased by 30%. This was due o he parasiic capaciances and resisance in he ransisors and inerconnecions. Afer idenifying his problem, several ieraions were performed, based on he esimaion of he parasiic capaciances, unil he desired swiching frequency was achieved. This value was slighly above from wha i has been projeced alhough wihou affecing he sysem performance (3.6%). Also a minor problem was found during he compensaor implemenaion. The bandwidh of he operaional ransconducance amplifier influences he overall frequency response of he compensaor when high conrol crossover frequencies are desired. I was idenified in his work ha he seleced opology for he amplifier was almos a is limis o provide a good performance in closed loop crossover frequency. Wha his means is ha he frequency response of he compensaion circui goes beyond he limi of he error amplifier gain-bandwidh produc implying ha is inernal GBW produc ses he maximum closed-loop crossover frequency of he sysem. The only way o avoid his problem are o say below he GBW of he error amplifier or o re-design he amplifier ha consiues he compensaor in order o achieve a higher GBW produc. This comes wih an expense of more power consumpion, which means ha wih a carefully rade-off beween he closed loop crossover frequency and he amplifier power consumpion, he necessary amplifier performance can be achieved, aking full advanage of he bes deermined closed-loop crossover frequency wih any of he wo presened compensaors. The fully inegraion and high frequency operaion of dc-dc converer will become a rend in he following years for modern power elecronics. The research has proven ha his is an endless opic in power elecronics. REFERENCES [1] S. Musunuri, P.. Chapman, J. Zou, and C. iu, Design issues for monolihic dc dc converers, IEEE Trans. Power Elecron., vol. 20, no. 3, pp , May [2] Seyaer M., Van Breussegem T., Meyvaer H., Callemeyn P., Wens M., DC-DC converers: From discree owards fully inegraed CMOS, in Proceedings of he European SolidSae Circuis Conference, pp , Sep [3] S.R. Sanders, E. Alon, Hanh-Phuc e, M.D. Seeman, M. John, V.W. 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