A Navigation-Grade MEMS Accelerometer based on a Versatile Front End

Transcription

1 A Navigaion-Grade MEMS Acceleromeer based on a Versaile Fron End Marc Pasre, Maher Kayal STI IEL ELab EPFL Lausanne, Swizerland Hanspeer Schmid IME FHNW Windisch, Swizerland Pascal Zwahlen, Yufeng Dong, Anne-Marie Nguyen Colibrys SA Neuchâel, Swizerland Absrac This paper presens a MEMS-based 5 h -order ΔΣ capaciive acceleromeer. The ΔΣ loop is implemened in mixed signal, he global 5 h -order filer having a 2 nd -order analog and a 3 rd -order digial par. The sysem can be used wih a wide range of sensors, because he mixed-signal fron-end is programmable. The developed ASIC comprises a volage-mode preamplifier, wo parallel demodulaors implemening CDS, and a 7-bi inernally non-linear flash ADC. The laer drives a 3 rd -order digial filer which can be configured for differen sensor parameers in order o ensure overall loop sabiliy and o opimize he noise performance. Wih a low-noise MEMS sensor, he sysem achieves a 19-bi DR and a 16-bi SNR, boh over a 3-Hz bandwidh. I. INTRODUCTION The marke for inerial high-performance acceleromeers can be segmened ino several caegories: acical grade, navigaion grade and miliary grade, each characerized by an order-of-magniude improvemen on bias sabiliy, lineariy and noise. Peneraing he inerial-navigaion-grade marke requires compeing from esablished echnologies like macro-elecromechanical servo acceleromeers and quarz-resonaing acceleromeers. While he macro-elecro-mechanical acceleromeers reach high performances, hey are expensive and fragile [1]. Quarz resonaors have excellen dynamic range bu exhibi degraded sabiliy performance and verylow-g shock olerance. MEMS have he poenial of low-cos high-volume producion hanks o is bach-processing manufacuring. They can also be made very-high-g shock oleran, wihou pos-shock performance degradaion. Mid- o high-performance open-loop MEMS acceleromeers are commercially available oday and reach acical-grade performances wih a sabiliy of 1.5mg or 15ppm, a oal harmonic disorion of 5dB and an SNR of 97dB [2]. The ulimae evoluion of he open loop MEMS sensor is seen a a sabiliy of 1ppm, a THD of 6dB and an SNR of 14dB [1]. Bringing MEMS acceleromeer one sep furher owards higher-performance navigaion grade requires operaing he MEMS acceleromeer in a servo mode. MEMS servo acceleromeers have already demonsraed high performance in low-g applicaions for earhquake monioring or geoseismic imaging. Noise floors as low as -145dBg/ Hz, wih a working range of ±.3g including 1g graviy compensaion have already been repored [3]. The challenge o bring his echnology owards inerial navigaion is abou significanly improving he bias sabiliy. Compared o oher previously repored works [4], [5], our design akes advanage of he exremely good mechanical characerisics of he sensor and herefore allows for relaxed requiremens on he elecronics side. The sensor s mechanical bias sabiliy has been demonsraed o be a key conribuor o he overall biassabiliy budge even in servo-loop operaion. This paper presens a versaile acceleromeer sysem based on a reconfigurable fron-end and a ΔΣ loop. I consiss of an applicaion-specific inegraed circui (ASIC) conaining a versaile analog fron end, a low-precision inernally nonlinear ADC, and an exernal digial filer. The versaile elecronics can be inerfaced wih a large variey of sensors for differen applicaions. Secion II presens he sysem archiecure. The differen blocks are deailed in secion III, while secion IV presens measuremen resuls and secion V concludes. II. SYSTEM ARCHITECTURE Figure 1 presens he archiecure of he acceleromeer sysem [6]. The capaciive MEMS acceleromeer sensor is a moving mass in he middle beween wo fixed plaes. These hree elecrodes are conneced o a se of high-volage (HV) swiches ha apply acuaion and posiion-sensing pulses. An addiional HV swich connecs he middle elecrode o he /11/$ IEEE 438

2 HV & Analog fron end ASIC Sensor 7-bi ADC 3 rd order digial filer Digial oupu bisream High volage Preamplifier Demodulaors (CDS) Buffer A/D conversion HV swich conrol Figure 1. Sysem archiecure. low-volage (LV) preamplifier in he analog fron end during posiion sensing, and proecs he LV circui during HV acuaion of he middle elecrode. The analog fron-end ASIC is a high-speed low-precision posiion measuremen inerface consising of a low-noise volage-mode preamplifier, demodulaors for correlaed double sampling (CDS), and an inernally non-linear 7-bi flash analog-o-digial converer (ADC). The gain of each block is configurable o fi he sensor characerisics. Since he sensor already inegraes he inpu and feedback signals of he ΔΣ loop wice, he precision requiremen on he analog fron end is relaxed: 7-bi precision gives sufficienly good noise and disorion performance for all he differen sensors o be used wih he sysem. The digiized oupu is fed ino a 3 rd -order digial filer ha increases he loop order o five, giving he sysem a high resoluion. Finally, he sign of he oupu of he digial filer, which is he oupu bisream, also deermines he direcion in which he acuaion force is applied o he sensor. III. SYSTEM BLOCKS This secion presens he differen blocks consiuing he acceleromeer sysem. A. Sensor and Fron End The sensor and is inerface comprising he HV swiches and he preamplifier from Figure 1 are deailed in Figure 2. V rese sense acuaion The HV-swich conrol signals are shown for a ypical operaing cycle. The 1-μs cycle period is subdivided ino one posiion-sensing phase and one acuaion phase which are equal in lengh (.5μs each). The elecrosaic acuaion force is generaed by connecing he moving mass and one plae o one of he HV supplies, and he second plae o he opposie HV supply. The posiion-sensing phase sars by shor-circuiing he hree sensor elecrodes o ground in order o discharge he sensor capaciances (rese). Then he wo fixed elecrodes are conneced o he posiive and negaive HV supplies, and he moving-mass elecrode is conneced o he high-impedance inpu of he preamplifier. Since he sensor capaciance values reflec he posiion of he moving mass, he middle poin of he sensor capaciive bridge displays a corresponding volage variaion. If C (x) is he capaciance beween he op plae and he middle elecrode, C b (x) beween he boom plae and he middle elecrode, and x is he disance of he moving mass o is equilibrium poin in he middle beween he elecrodes, he middle-elecrode volage V mid during he sense phase depiced in Figure 2 is: V ( ) ( x C x mid ) = HV + 2 HV C ( x ) + C ( x ) Since he feedback conrol loop ries o keep he moving mass in he middle beween he op and boom plaes, he displacemen of he mass is so small ha C (x) and C b (x) vary linearly and symmerically around a nominal value C wih sensiiviy C Δ : b (1) Hi-Z C ( x) = C + C x ; C ( x) = C C x (2) Δ b Δ φ rese V pre Equaion (1) hen simplifies o: [μs] Figure 2. Sensor and analog fron end. CΔ Vmid ( x) = HV x (3) C 439

3 This volage is amplified by he volage-mode preamplifier wih a capaciive feedback, which is rese prior o amplificaion. The sign of he oupu signal can be reversed by exchanging he posiive and negaive HV supply connecions o he op and boom plaes (+sense and -sense in Figure 3), which hen allows o perform CDS as discussed in he nex secion. The gain of he volage-mode preamplifier sage is fixed by a capacior raio and does no depend on he sensor capaciance value, as i does in charge-mode amplifier opologies [7]. This allows seing he gain of he preamplifier precisely. A low gain value of 1 is chosen o achieve accurae seling wihin 25ns. A second advanage of he volage amplifier is ha he noise performance is increased [8]. B. Demodulaion & CDS Figure 3 shows one demodulaor circui implemening he CDS, as well as he corresponding swich conrol signals. φ +sense φ rese phases needed for CDS can be par of wo successive cycles. There is hen only one rese and sense phase per cycle, he +sense and sense being alernaed from cycle o cycle. However, he demodulaion oupu can hen be calculaed only every second cycle, which reduces he effecive ΔΣ loop frequency and decreases performance. I is also possible o implemen he scheme of Figure 4, which uses wo demodulaors in a ime-inerleaved fashion. Then each cycle conains eiher a +sense or a sense phase. When he firs demodulaor is performing is firs demodulaion operaion, he second demodulaor already finishes he second one and he value compued is fed ou. During he nex cycle, he roles are reversed and so on. In his way, here is one oupu value for each cycle wihou needing wo sense phases per cycle or increasing he cycle lengh. Compared o Figure 3, only one cycle of excess loop delay remains. The opimum choice of he CDS scheme o use depends on he sensor used, he required signal bandwidh, and he required noise performance. φ rese;1 C sum C sum φ -sense V in + V in φ -sense V ou φ rese;2 C sum V ou rese +sense rese -sense acuaion φ rese φ +sense V in + φ -sense rese +sense acuaion rese -sense acuaion cycle #i Figure 3. Demodulaor and CDS implemenaion. The circui subracs he pre-amplified signals resuling from wo successive +sense and -sense phases during he same cycle, which has he effec of cancelling he offse and 1/f noise of he preamplifier. The signal is sampled direcly on he inpu capaciors a he end of each sense phase. The charge is hen ransferred o he summing capacior during he acuaion phase, allowing 5ns for he amplifier o sele and hus relaxing is gainbandwidh (GBW) design consrains. To accommodae for differen sensor characerisics, he gain of he demodulaor can be programmed by adjusing he feedback capacior (C sum ). The disadvanage of he scheme presened in Figure 3 is ha because here are wo rese and sense phases, he cycle becomes longer. To overcome his limiaion, he wo sense φ rese;1 φ rese;2 cycle #i cycle #i+1 Figure 4. Time-inerleaved CDS using 2 demodulaors. C. Analog-o-Digial Conversion The oupu of he analog fron end is digiized by a lowprecision ADC, which is also inegraed in he ASIC. The speed and precision requiremens are he same as for he analog circui, i.e. 1MS/s wih 7-bi precision. An inernally non-linear flash implemenaion is used [9]. Inside our ΔΣ loop i is no necessary o build a linear 7-bi ADC. The probabiliy disribuion a he inpu of he ADC is no uniform, in mos cases here are more values o process in 44

4 he cenre of he ADC range han owards he exremes. This fac has been used before in muli-bi ΔΣ converers by using complex μ-law ADCs [1] or easier o implemen semiuniform quanizers [11]. According o [12], a quanizer can be made opimum if he probabiliy densiy of is inpu values is known. The quesion is: which probabiliy disribuion shall we choose if we do no know much? Simulaions and measuremens of an acceleraion sensor loop have shown ha he specific disribuion depends on he signal a he inpu, he sensor, and he parasiic effecs like offse and elecronic noise. A ΔΣ acceleromeer loop like mos oher ΔΣ sensor loops oo uses high-gain feedback o keep he sensor mass a a given cenre posiion. The sensor displacemen is hen small compared o he maximum possible displacemen before he sensor mass ouches he op or boom plae. However, since he disribuions look so differen for differen inpu signals, we have no furher knowledge abou he probabiliy disribuion excep ha we measure a locaion parameer wih hard bounds far away from he operaing range. Therefore, he disribuion o assume is he one which makes no implici assumpions oher han ha we measure a locaion parameer. This is he so-called maximum-enropy disribuion for locaion parameers, which is he Gaussian disribuion [13]. So we do no choose he Gaussian disribuion because we know ha he values o be measured will have ha disribuion hey ofen have no bu because i i is he bes represenaion of our prior knowledge: he user of our sysem can aach differen sensors, do differen applicaions, have differen inpu signals, and we do no know wha probabiliy disribuions o expec, jus ha we measure is a locaion parameer. In he remainder of his secion, we focus on he presened acceleraion sensor, bu our reasoning exends o oher ΔΣ sysems as well because he oupu of he second (or even he firs) inegraor always are of locaionparameer naure. The smalles quanizaion inerval of our ADC has a widh of 15.4mV (i is locaed in he cenre of he inpu range). This is even larger han he inerval of a linear 7-bi quanizer, 1.8V / 27 = 14.1mV, as i would be needed o build a semi-uniform quanizer like he one in [11], and i is much larger han he very small quanizaion seps used in he cenre range of μ-law ADCs [1]. Noe ha his quanizer is buil for an inpu disribuion ha has a specific sandard deviaion. The sage preceding i mus herefore be a programmable-gain amplifier whose gain can be se differenly for differen applicaions and sensors. In our sysem, i is programmable in he range A Resisors & Comparaors hermomeric decoding non-linear decoding 64 bis 6 bis 16 bis Figure 5. Non-linear ADC block diagram. The schemaic of our ADC is shown in Figure 5. I consiss of a block conaining comparaors and a resisive divider, similar o a flash ADC, bu consruced wih nonlinearly disribued decision hresholds. The oupu is a hermomeric code from which he number of he quanizaion inerval is calculaed. Finally, a look-up able (in our es seup residing on an FPGA) compues he oupu wih a precision of 16 bis, which is he inpu forma required for he digial filer block. D. Digial Filer The ΔΣ loop furher includes an exernal 3 rd -order digial filer wih a fixed-poin implemenaion and configurable coefficiens. The laer can be adjused in order o preserve he overall loop sabiliy and opimize he noise specrum for a wide range of MEMS sensors. The funcion implemened is a 3 rd -order inegraor, combined wih a zero used o compensae for he phase shif due o he 2 nd -order inegraing funcion of he sensor in order o achieve loop sabiliy. The oupu of he digial filer deermines he direcion in which he acuaion force is applied. I is noeworhy ha he 1-bi quanizer used in his ΔΣ loop is a digial one. From he fixed-poin calculaion of he filer oupu, only he sign is kep o deermine he digial oupu of he sysem (bisream) and he direcion of he acuaion on he sensor (force). IV. MEASUREMENT RESULTS The complee mixed-signal fron end has been inegraed in a.6μm CMOS process wih HV opions. The ASIC includes he HV swiches, he analog fron end wih he preamplifier, he CDS demodulaors, and he 7-bi flash ADC. The digial filer was implemened in an FPGA, and a Colibrys low-noise MEMS sensor (mass: 3.5mg; noise:.8μg/ Hz) was conneced o he ASIC hrough shielded wires and a prined circui board (PCB). The sysem has a full scale of 11g and a bandwidh of 3Hz. Figure 6 shows he measured normalized oupu specrum of he ΔΣ loop wihou exciaion in an environmen wih a very low level of acceleraion noise. The noise floor is a 1.15μg/ Hz, which corresponds o a dynamic range (DR) of 19 bis over he 3-Hz bandwidh. Figure 7 shows he resul when an 8-g exciaion a 222Hz is applied. The shaker able used in his measuremen sood in a room wih higher graviaion noise in he frequency range 2-6Hz. The noise figure measured in ha room is idenical if no signal is applied by he shaker. The signal harmonics ha can be seen correspond o he non-lineariy of he shaker, which has been verified by measuremens using a differen high-precision low-noise reference acceleromeer. For he 8-g sinusoidal acceleraion a 222Hz, he measured whie-noise floor goes up o 7.1μg/ Hz in he signal band, corresponding o an SNR of 16 bis. The DR ha is 3 bis higher han he SNR is paricularly ineresing for inerial navigaion applicaions, where he noise performance a reduced signal level is imporan. Furher characerisics and measuremen resuls are presened in Table I. The sysem feaures 2.3b higher SNR and 5.2b higher DR han [14] when normalized o he same bandwidh. 441

5 Normalized oupu noise [dbfs/ Hz] Normalized oupu [dbfs/ Hz] f [Hz] Figure 6. Normalized oupu noise specrum wihou exciaion f [Hz] Figure 7. Normalized oupu noise specrum wih an 8g sinusoidal exciaion a 222Hz. TABLE I. SYSTEM CHARACTERISTICS AND PERFORMANCES Parameer Value Uni Supply volage (LV) 3.3 V Supply volage (HV) ± 9 V Power consumpion 4 mw Sampling frequency 1 MHz Loop order 2 (sensor) + 3 (digial) = 5 Analog fron-end gain Preamplifier inpu noise 1 nv/ Hz Signal bandwidh 3 Hz Full scale 11.7 g Inpu noise (no signal) 1.7 μg/ Hz Dynamic range (3Hz BW) 19 bis Inpu noise (full-scale signal) 7.1 μg/ Hz Signal-o-noise raio (3Hz BW) 16 bis Chip area 9.7 mm 2 TABLE II. PERFORMANCE REVIEW Parameer This work QA 23 Uni Full scale g Noise μg/ Hz Dynamic range (1Hz BW) bis Bandwidh 3 5 Hz Bias sabiliy (24h).1.1 mg Non-lineariy (K2) <1 <2 μg/g 2 Bias emperaure coefficien Scale-facor emperaure coefficien 1 <3 μg/ C ppm/ C - Table II furher compares he performance wih an indusry sandard, he Honeywell Q-Flex 2-3 [16]. For inerial applicaions, he bias sabiliy, non-lineariy and emperaure sabiliy are essenial feaures [15]. Bias sabiliy performance is presened in Figure 8, along wih he emperaure evoluion during he measuremen, which explains par of he drif observed. The measuremen over one hour shows a bias drif of less han ±12μg over a 1g dynamics, i.e. well below ±1ppm. This makes his sensor well suiable for navigaion grade inerial sensing applicaions. The bias shif induced by vibraion and shifed o DC hrough sensor nonlineariy (dominaed by second harmonic K2), called vibraion recificaion error (VRE), is an imporan parameer for inerial navigaion. Exremely low K2 non-lineariy values <1μg/g 2 are measured [15]. However, due o he servo-loop operaion and excellen linearizaion capabiliy of he elecrosaic forces hrough ΔΣ conrol, K2 is expeced o be below 1μg/g 2. Repored values are sill limied by measuremen capabiliies and no sysem performance. Finally, preliminary emperaure characerizaions from -3 C o +8 C show a emperaure dependence of he bias as low as 1μg/ C, and a ypical K1 scale facor <75ppm/ C. Figure 9 presens a micrograph of he ASIC. The oal area is 9.7mm 2. The HV swiches occupy 1.1mm 2, he analog circui.6mm 2, and he ADC.4mm 2. The area occupied by he digial configuraion and conrol block is needed only for esing his prooype. The ASIC power consumpion (preamplifier, CDS, ADC and swich conrol logic) is 4mW. 442

6 Powered by TCPDF ( ACKNOWLEDGMENT The auhors hank he Swiss CTI for funding. Sabiliy [ μg] Time [minues] Figure 8. Bias sabiliy measuremen. Figure 9. Circui micrograph. V. CONCLUSION The acceleromeer fron-end presened in his paper is generic and allows inerfacing a wide range of sensors. I consiss of HV swiches for driving he MEMS, a low-noise preamplifier, a se of demodulaors for CDS, and a 7-bi flash ADC. The gain of he circui can be programmed o accommodae for sensor characerisics. An exernal reconfigurable 3 rd -order digial filer is used o raise he oal loop order o 5 and hus improve he sysem resoluion. This mixed-signal ΔΣ loop implemenaion and is programmable filer can inerface MEMS sensors o realize acceleromeers in he sub-g o 1g range wih high lineariy and very good noise performance. Wih a Colibrys low-noise MEMS sensor, he sysem exhibis a 19-bi dynamic range and 16-bi SNR over he 3Hz signal bandwidh. Temperaure [ C] REFERENCES [1] F. Rudolf, P. Zwahlen, Y. Dong, MEMS acceleromeers for highes performance applicaions 9h SEGJ Inernaional Symposium [2] Colibrys Acceleromeer RS91 Daashee, hp:// [3] J. Gannon, H. Pham, K. Speller, A Robus Low Noise MEMS Acceleromeer Proc. of he ISA Emerging Technologies Conference, Houson, TX, Sep. 1-12, 21. [4] J.M. Tsai, G.K. Fedder, Mechanical Noise-Limied CMOS-MEMS Acceleromeers, Tech. Diges MEMS 25, Miami Beach, pp [5] M. Lemkin, B.E. Boser, A Three-Axis Micromachined Acceleromeer wih a CMOS Posiion-Sense Inerface and Digial Offse-Trim Elecronics IEEE J. of Solid-Sae Circuis, Vol. 34, No. 4, pp , April 1999 [6] M. Pasre, M. Kayal, H. Schmid, A. Huber, P. Zwahlen, A.-M. Nguyen, Y. Dong, A 3 Hz 19b DR Capaciive Acceleromeer based on a Versaile Fron End in a 5h-order Dela-Sigma Loop, ESSCIRC, Ahens, Greece, Sep , 29 [7] J. Wu, G. K. Fedder, L. R. Carley, A Low-Noise Low-Offse Chopper-Sabilized Capaciive-Readou Amplifier for CMOS MEMS Acceleromeers, ISSCC Dig. Tech. Papers, pp , 478, Feb. 22 [8] J. Wu, G. K. Fedder, L. R. Carley, A Low-Noise Low-Offse Capaciive Sensing Amplifier for a 5-μg/ Hz Monolihic CMOS MEMS Acceleromeer, IEEE J. Solid-Sae Circuis, Vol. 39, pp , May 24 [9] H. Schmid, S. Sigel, M. Pasre, M. Kayal, P. Zwahlen, A.-M. Nguyen, An Inernally Non-Linear ADC for a ΔΣ Acceleromeer Loop, IEEE Inernaional Symposium on Circuis and Sysems (ISCAS), Vol. 1, pp , May 21 [1] Z. Zhang and G. Temes, Mulibi oversampled ΣΔ A/D converor wih nonuniform quanisaion, Elecronics Leers, vol. 27, no. 6, pp , Mar [11] B. Li and H. Tenhunen, Sigma dela modulaors using semi-uniform quanizers, in Proc. ISCAS, vol. 1, Sydney, May 21, pp [12] S. P. Lloyd, Leas squares quanizaion in PCM, IEEE Trans. Inf. Theory, vol. 28, no. 2, pp , Mar [13] E. T. Jaynes, Probabiliy Theory: The Logic of Science. Cambridge Universiy Press, 23. [14] C. Condemine, N. Delorme, J. Soen, J. Durup, J.-P. Blanc, M. Belleville, and A.Besanc on-voda, A.8mA 5 Hz 15b SNDR ΔΣ closed-loop 1g acceleromeer using an 8h-order digial compensaor, in Proc. ISSCC, San Francisco, 25, pp [15] P. Zwahlen, A.-M. Nguyen, Y. Dong, F. Rudolf, M. Pasre, H. Schmid, Navigaion Grade MEMS Acceleromeer, IEEE Inernaional Conference on Micro Elecro Mechanical Sysems (MEMS), pp , January 21 [16] Honeywell, QA2 Q-Flex Acceleromeer, hp:// 443