LD7830H 06/27/2012. High Power Factor Flyback LED Controller with HV Start-up. Features. General Description. Applications. Typical Application

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1 06/27/2012 High Power Facor Flyback LED Conroller wih HV Sar-up Rev: 00 General Descripion The LD7830H is a HV sar-up Flyback PFC conroller, specially designed for LED lighing appliances. I operaes in ransiion(tm) mode and inegraes wih complee proecions required for safey and herefore i s an excellen soluion o minimize he componens couns. Those make i ideal for cos- effecive applicaions. Wih HV sar-up echnology, high power facor and TM conrol, i s capable o reduce he sar-up ime and resisor loss grealy. The circui can easily achieve PF>0.90 o mee mos inernal sandard requiremens. Wih compleed proecion buil inside his IC, such as over volage proecion (OVP), over curren proecion (OCP), over load proecion (OLP), over emperaure proecion (OTP), and shor circui proecion (SCP), I enable he circui o mee mos safey requiremens eiher in normal and abnormal es. Feaures High volage (600V) sarup circui High Power Facor Flyback PFC conroller High-Efficiency Transiion mode operaion Wide UVLO (16V ON and 7.5 V OFF) VCC OVP (Over Volage Proecion) OLP(Over Load Proecion) OCP (Cycle by Cycle Curren Limiing) Vcs=0.5V Inernal OTP (Over Temperaure Proecion) 500/-800mA Driving Capabiliy Inernal OTP funcion Applicaions LED Power Supply Flyback PFC Power Supply Typical Applicaion LF1 AC Inpu EMI C1 Filer LED+ LED- 6 VCC 8 HV GATE 5 1 ZCD LD7830H CS 3 2 COMP VSEN GND ISEN 1.25V 0.1V LD8105 GND 4 IREF OUT VCC LED+ 1

2 ZCD COMP CS GND ZCD COMP CS GND HV VCC OUT HV NC VCC OUT LD7830H Pin Configuraion SOP-7 (TOP VIEW) SOP-8 / DIP-8 (TOP VIEW) TOP MARK YYWWPP TOP MARK YYWWPP YY: WW: PP: Year code Week code Producion code Ordering Informaion Par number Package Top Mark Shipping LD7830H GR SOP-7 LD7830HGR 2500 /ape & reel LD7830H GS SOP-8 LD7830HGS 2500 /ape & reel LD7830H GN DIP-8 LD7830HGN 3600 /ube /Caron The LD7830H is RoHs complian/ Green Packaged. Proecion Mode Pin Descripions Par number VCC OVP OLP LD7830H Lach Lach Pin NAME FUNCTION 1 ZCD Quasi resonance deecor and programmable maximum ON-ime. COMP Feedback pin. Connec wih a phoo-coupler o close he conrol loop and achieve regulaion. 3 CS Curren sense pin, o sense he MOSFET curren for OCP 4 GND Ground 5 OUT Gae drive oupu o drive he exernal MOSFET 6 VCC Power source VCC pin 7 NC No conneced. 8 HV Connec his pin o posiive erminal of main bulk cap o provide sarup curren for conroller. Once Vcc is UVLO on, he HV loop will open and urn off inernal curren source o minimize he power loss. 2

3 Block Diagram HV VCC HV Regulaor 6.5V PDR UVLO 26V VCC OVP 16V/7.5V VCC OK inernal bias & Vref Vref OK PG All Block VCC OVP PDR S R Q OLP Zero ON Time Driver Sage OUT Sar Timer 0.1V/0.2V Fmax limi ZCD Blanking S Q ZCD PWM Comparaor R Vref Ramp generaor OCP Comparaor Leading Edge Blanking CS COMP ZCD 0.5V Zero ON Time Zero ON Time 0.80V PDR OLP delay S Q OLP 4.8V PDR R GND 3

4 Absolue Maximum Raings Supply Volage VCC -0.3 ~30V High volage pin, HV -0.3~600V OUT -0.3 ~VCC +0.3V COMP, CS, ZCD -0.3 ~6V Maximum Juncion Temperaure 150 C Operaing Juncion Temperaure Range -40 C o 125 C Operaing Ambien Temperaure Range -40 C o 85 C Sorage Temperaure Range -65 C o 150 C Package Thermal Resisance (SOP-8, SOP-7 JA) 160 C/W Package Thermal Resisance (DIP-8, JA) 100 C/W Power Dissipaion (SOP-8, SOP-7, a Ambien Temperaure = 85 C) 250mW Power Dissipaion (DIP-8, a Ambien Temperaure = 85 C) 400mW Lead emperaure (Soldering, 10sec) 260 C ESD Volage Proecion, Human Body Model (excep HV pin) 2.5KV ESD Volage Proecion, Machine Model 250 V Cauion: Sress exceeding Maximum Raings may damage he device. Maximum Raings are sress raings only. Funcional operaion above he Recommended Operaing Condiions is no implied. Exended exposure o sress above Recommended Operaing Condiions may affec device reliabiliy. Recommended Operaing Condiions Iem Min. Max. Uni Vcc pin capacior F Comp pin capacior 1 10 F 4

5 Elecrical Characerisics LD7830H (V CC =15.0V, T A = 25 C unless oherwise specified.) PARAMETER CONDITIONS MIN TYP MAX UNITS High volage Supply (HV Pin) High-volage curren Source V CC =4V, HV=80V ma V CC =9V,HV=80V ma Off-sae Leakage curren V CC >UVLO (ON), HV=500V 0 35 A Supply Volage (VCC Pin) Sarup Curren V CC <UVLO ON A V COMP =0V, ZCD=0 1 ma Operaing Curren V COMP =3V, ZCD= ma (wih 1nF load on OUT pin) V CC OVP 0.3 ma OLP 0.3 ma UVLO (OFF) V UVLO (ON) V HV Self Bias (Linear Regulaor) V De-Lach VCC Volage PDR (Power Down Rese) V VCC OVP Level V Volage Feedback(Comp Pin) Shor circui curren V COMP= ma Open loop volage V OLP Trip Level V Zero ON-ime Threshold 0.8 V Zero ON-ime Hyseresis 25 mv OLP Delay Time ms Curren Sensing (CS Pin) Curren Sense Inpu Threshold Volage I ZCD<110 A V I ZCD>490 A V Sof Sar Time * 8 ms Inpu bias curren V CS=0V~0.5V A LEB ime ns 5

6 PARAMETER CONDITIONS MIN TYP MAX UNITS Zero Curren Deecor (ZCD Pin) Upper Clamp Volage I DET=100 A V Lower Clamp Volage I DET=-2mA V Inpu Volage Threshold V Hyseresis V Inpu bias curren V ZCD=1V~4V, OUT=OFF A Programming Maximum ON-Time, Ton-max (ZCD Pin) Programming Maximum ON-ime ZCD R ZCD=6k, s Maximum ON-ime ZCD R ZCD 34k, s Minimum (ON+OFF)-Time Minimum (ON+OFF)-Time F MAX(250kHz), s Minimum OFF-Time s Gae Drive Oupu (OUT Pin) Oupu Low Level V CC =15V, I SINK=20mA V Oupu High Level V CC =15V, I SOURCE=20mA 10 VCC V Oupu High Clamp Level V CC =16V 13 V Rising Time V CC =15V, CL=1000pF ns Falling Time V CC =15V, CL=1000pF ns Sarer Sar Timer Period s Inernal OTP (Over Temp. Proecion) OTP Trip level * 140 C OTP Hyseresis * 30 C *: These parameers are guaraneed by design. 6

7 Applicaion Informaion Operaion Overview The LD7830H is an excellen single-sage Flyback PFC conroller for LED lighing applicaions. Wih several funcions inegraed, i s an ideal soluion o minimize exernal componens couns and he size. In addiion, he LD7830H is a volage-mode TM PFC conroller. The urn-on ime of swich is fixed while he urn-off ime is varied in he seady condiion. Therefore, he swiching frequency changes in accordance wih he inpu volage variaion. The LD7830H provides funcions of over-load proecion, over-volage proecion, over-curren proecion, under-volage lockou and inegraed LEB of he curren sensing. Also, he LD7830H requires no main-volage sensing, superior o wha he oher radiional curren mode PFC conrollers behave for power saving. he Vcc capacior. In using such configuraion, he urn-on delay ime will be almos no difference eiher in low-line or high-line condiions. Once he Vcc volage rises over UVLO(on), i will power on he LD7830H and furher o deliver he gae drive signal. Then he high-volage curren source will be disabled and he supply curren is provided from he auxiliary winding of he ransformer. Therefore, he power loss is eliminaed and power saving is enhanced. An UVLO comparaor is embedded o deec he volage on Vcc pin o ensure he supply volage enough o power on he LD7830H PWM conroller and in addiion o drive he power MOSFET. As shown in Fig. 14, a hyseresis is provided o preven he shudown from volage dip during sarup. AC inpu EMI Filer Inernal High-Volage Sarup Circui and Under Volage Lockou (UVLO) The radiional circui provides sarup curren hrough a sarup resisor o power on he PWM conroller. However, i consumes significan power for i. In mos cases, sarup resisors carry large resisance. And, larger resisance spends more sarup ime. To achieve he opimized opology, as shown in figure 13, LD7830H is implemened wih a high-volage sarup circui for such requiremen. During sarup, a high-volage curren source sinks from he full-bridge recifier o provide sarup curren o charge Vcc capacior C1. On condiion of VCC below PDR, i consumes only 1.3mA for charge curren. This proecs he IC from damage in case he VCC pin is shored o ground. In shor sar-up ime, he charge curren will increases o 3.1mA once VCC rises above PDR volage hreshold during sar up. Meanwhile, i consumes only 75 A for Vcc supply curren, so mos of he HV curren is reserved o charge HV VCC OUT LD7830H Fig. 13 CS GND D1 C1 7

8 Vcc The Zero Curren Deecion block will deec auxiliary UVLO(on) UVLO(off) PDR winding signal o drive MOSFET as ZCD pin volage drops o 0.1V. As ZCD pin volage drops o 0.1V, he curren hrough he ransformer is below zero. This feaure enables ransiion-mode operaion. The ZCD comparaor would no operae if ZCD pin volage remains HV Curren a above 0.2V. Once i drops below 0.1V, he zero curren deecor will ac o urn on he MOSFET. 1.3mA 3.1mA Vcc curren ~ 0mA (off) Operaing Curren (Supply from Auxiliary Winding) Naux RZ1 RZ2 ZCD 0.1V/0.2V Sar Timer Fmax limi ZCD Blanking PWM Comparaor Turn-On S Turn-Off R Q Sarup Curren Vref Ramp generaor OCP Comparaor Fig. 14 COMP ZCD 0.5V Ramp Generaor Block and Zero Curren 0.8V Zero ON Time Burs Mode Deecion (ZCD) Fig. 15 Fig. 15 shows ypical ramp generaor block and ZCD block. The COMP pin volage and he oupu of he ramp generaor block are compared o deermine he MOSFET ON-ime, as shown in Fig. 16. A greaer COMP volage produces more ON-ime. Using an exernal resisor o connec wih ZCD pin o se he desired slope of he inernal ramp, he user may program he maximum ON-ime. Alernaively, he ON-ime will also achieve is maximum when COMP pin volage rip OLP rigger poin. The maximum ON-ime should be se according o he condiion of he ransformer, lowes AC line volage, and maximum oupu power. A choice of opimum resisor value would resul in bes performance. The 150 s imer generaes a MOSFET urn-on signal if he driver oupu drops o low level for more han 150 s from he falling edge of he driver oupu. Fig. 16 shows ypical ZCD-relaed waveforms. Since ZCD pin carries some capaciance, i produces some delay o he urn-on ime caused from Rz1. During delay ime, he juncion capacior of he MOSFET resonaes wih he primary inducor of he ransformer and he drain-source volage (V DS) decreases accordingly. So, he MOSFET consumes less volage o urn on and i herefore minimizes he power dissipaion. I shus down he drive oupu if COMP pin volage falls below zero ON-ime hreshold. This opimizes he efficiency for power saving in mos condiions. 8

9 OUT The following able is a suggesion for maximum ON-ime RAMP V COMP seing. Primary Curren I PEAK 0A R ZCD Max. Ton (Typ.) Suggesion Secondary Curren T on T dis -n aux/n s V OUT 0A 32k<R ZCD 16 s 36k 28k<R ZCD<32k 12.8 s 30k 24k<R ZCD<28k 10.7 s 26k AUX Volage -naux/np VIN Delay Time -n aux/n s V OUT R Z1/(R Z1+R Z2) 0V 20k<R ZCD<24k 9.1 s 22k 16k<R ZCD<20k 8.0 s 18k 12k<R ZCD<16k 7.1 s 14k ZCD Volage V OUT -0.3V-Clamp 0.1V 8k<R ZCD<12k 6.4 s 10k R ZCD<8k 5.8 s 6k V DS Fig. 16 Programming Maximum ON-ime Minimum Volage Turn-on LD7830H feaures adjusable maximum ON-ime o limi power oupu in abnormal operaion. The selecion of maximum ON-ime is subjec o ZCD resisance as shown in Fig. 17. ZCD resisance can be obained from below. 0V High/ Low Line OCP Compensaion LD7830H suppors high/low line OCP compensaion hrough aux-winding o reflec he magniude of inpu volage. When gae urns on, ZCD pin will source he curren I ZCD o clamp he volage o zero as shown in Fig.18. According o his curren informaion, OCP rigger level V CS-OFF will be deermined by R Z1 and inpu volage. In order o avoid ZCD pin over raing, I ZCD mus be se less han 2mA. I ZCD-max can be calculaed as below: VIN PK IZCD MAX 2mA NP /NVCC RZ1 R Z1 N Vcc R Z2 ZCD N Vcc R Z1 I ZCD ZCD RZ1 RZ2 RZCD RZ1 RZ2 Fig. 17 R Z2 Fig. 18 9

10 The relaion (ypical) of V CS-OFF and I ZCD is shown in Table 1. I ZCD ( A) V CS-OFF (V) < ~ ~ ~ ~ ~ ~ > Table 1 Oupu Drive Sage Wih ypical 500mA/-800mA driving capabiliy, an oupu sage of a CMOS buffer is incorporaed o drive a power MOSFET direcly. The oupu volage is clamped a 13V o proec he MOSFET gae even when he VCC volage is larger han 13V. R-C filer for hose large power applicaions o avoid CS pin being damaged from negaive urn-on spike. Over Load Proecion (OLP) - Lach mode The LD7830H feaures lach mode of smar OLP proecion. Figure 19 shows he waveform under faul condiion. The feedback sysem will force he volage loop ener oward he sauraion and hus pull he volage high on COMP pin (VCOMP). When he VCOMP ramps up o he OLP hreshold and says here for more han OLP delay ime, i will acivae he proecion o lach off he gae oupu and sop swiching of he power circui. The delay ime is o preven he false-riggering during power-on, urn-off ransien or in peak load condiion. Unless he over load condiion is removed, he conroller will remain lached unil he Vcc drops below PDR. I is necessary o sar anoher AC power-on recycling o resume he oupu. COMP OLP Delay Time OLP OLP rip Level Curren Sensing and Leading-edge Blanking VCC The LD7830H deecs he primary MOSFET curren over CS pin for pulse-by-pulse curren limi. The maximum volage hreshold of he curren sensing pin is se a 0.5V. From above, he MOSFET peak curren can be obained UVLO(on) UVLO( off) PDR AC inpu Volage AC Off Lach Released AC On ( Recycle) from below. 0.5V IPEAK (MAX) RS A leading-edge blanking (LEB) ime is imbedded in he inpu of CS pin o preven false-riggering from he curren spike. In hose low power applicaions, if he oal pulse widh of he urn-on spikes is less han LEB and he negaive spike on he CS pin isn over -0.3V, i is free o eliminae he R-C filer. OUT Swiching Non- Swiching Fig. 19 Swiching However, he oal pulse widh of he urn-on spike is deermined by he oupu power, circui design and PCB layou. I is srongly recommended o adop a smaller 10

11 OVP (Over Volage Proecion) on Vcc- Lached Mode Proecion The V GS raings of he nowadays power MOSFETs is mosly for 29V maximum. To proec he V GS from faul condiions, LD7830H is implemened wih OVP funcion on Vcc. If Vcc volage is over he OVP hreshold, he oupu gae drive circui will be shu down simulaneously o sop swiching of he power MOSFET. The Vcc OVP funcion in LD7830H is a lach-off ype proecion. If he OVP condiion occurs (usually caused by he feedback loop opened), Vcc will no recover unil AC power urns off. Figure 20 shows is operaion. The Vcc drops since here s no AC power presen. The de-lach level of OVP is defined by inernal PDR. Over volage proecion could be acivaed afer Vcc is below PDR level. l. OVP Level UVLO (on) UVLO(off ) PDR VCC OUT Swiching AC inpu Volage Faul Proecion OVP Tripped Non- Swiching Fig. 20 Lach Released AC Off AC On ( Recycle ) Swiching There are several criical proecions were inegraed in he LD7830H o preven he power supply or adaper from being damaged. Those damages usually come from open or shor condiion caused o LD7830H. Once i happens in below condiions, he gae oupu will urn off immediaely o proec he power circui. 1. Comp pin floaing 2. CS pin floaing 11

12 Reference Applicaion Circui --- LED -24V/700mA (90~264V AC ) Fuse L AC Inpu N NVcc L1 D3 R6 R8 C11 R9 C14 C1 R7 L2 C13 BD 6 VCC 1 ZCD VDC V1 R1 R2 8 HV LD7830H GND 4 R17 L3 C2 C3 GATE 5 CS 3 COMP 2 R18 C4 R20 R19 D4 D5 R21 R22 R23 R24 C20 C18 C19 R28 NP Q1 IC2 C7 T1 C8 R25 CY1 R29 D6 C5 C6 LED+ LED+ R43 R34 LED- R35 VSEN GND ISEN 1.25V 0.1V LD8105 IREF OUT VCC 12

13 Package Informaion SOP-7 Symbols Dimensions in Millimeers Dimensions in Inch MIN MAX MIN MAX A B C D F H I J M θ

14 Package Informaion SOP-8 Symbols Dimensions in Millimeers Dimensions in Inch MIN MAX MIN MAX A B C D F H I J M θ

15 Package Informaion DIP-8 Symbol Dimension in Millimeers Dimensions in Inches Min Max Min Max A B C D E F I J L Imporan Noice Leadrend Technology Corp. reserves he righ o make changes or correcions o is producs a any ime wihou noice. Cusomers should verify he daashees are curren and complee before placing order. 15

16 Revision Hisory Rev. Dae Change Noice 00 6/27/2012 Original Specificaion 16

LD7830 VSEN GND ISEN COMP

LD7830 VSEN GND ISEN COMP 8/17/2012 High Power Factor Flyback LED Controller with HV Start-up REV: 01a General Description The LD7830 is a HV start-up Flyback PFC controller, specially designed for LED lighting appliances. It operates