LD5760A 12/15/2016. High Voltage Green-Mode PWM Controller with BNO Function. Features. General Description. Applications. Typical Application REV.

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Eugene Sparks
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1 High Volage Green-Mode PWM Conroller wih BNO Funcion REV. 06 General Descripion The is a Green Mode PWM IC buil-in wih brown-in/ ou funcions in a SOP-7 or SOP-8 package. I minimizes he componen couns, circui space, and reduces he overall maerial cos for he power applicaions. The feaures HV sar, green-mode power-saving operaion, and inernal slope compensaion, sof-sar funcions o minimize he power loss and enhance he sysem performance. Wih complee proecion in i, as OLP (Over Load Proecion), OVP (Over Volage Proecion), fas SCP (shor circui proecion) and brown-in/ou proecion, prevens he circui from being damaged under abnormal condiions. Furhermore, he feaures frequency swapping and sof driving funcion o reduce he noise and improve EMI. Feaures High-Volage (650V) Sarup Circui Buil-in Brown-in/ou Funcion on HV pin Buil- in X-Cap Discharge on HV pin Frequency Swapping for EMI improvemen Non-Audible-Noise Green Mode Conrol LEB (Leading-Edge Blanking) on CS Pin Inernal Slope Compensaion Inernal OCP Compensaion OVP (Over Volage Proecion) on /CS OLP (Over Load Proecion) OTP (Over Temperaure Proecion) SCP(Shor Circui Proecion) Sof Sar Sof Driving 300mA/-800mA Driving Capabiliy Applicaions Swiching AC/DC Adapor and Baery Charger Open Frame Swiching Power Supply LCD Monior/TV Power Typical Applicaion AC Inpu EMI Filer ~ ~ DC Oupu OTP HV * GND COMP CS 1

2 OTP COMP CS GND OTP COMP CS GND HV NC HV Pin Configuraion SOP-8 (TOP VIEW) SOP-7 (TOP VIEW) TOP MARK YYWWPP TOP MARK YYWWPP YY: WW: PP: Year code Week code Producion code Ordering Informaion Par number Package Top Mark Shipping GS SOP-8 GS 2500 /ape & reel GR SOP-7 GR 2500 /ape & reel The is ROHS complian/green Packaged. Proecion Mode Par number _OVP OSCP CS_OVP OLP OTP Pin Descripions Lach Auo-Resar Lach Auo-Resar Lach PIN NAME FUNCTION 1 OTP 2 COMP Pulling his pin below 0.95V will force he conroller ener ino lach mode and i will no resume unil he AC power recycles. Connec a NTC beween his pin and ground o achieve OTP proecion funcion. Le his pin floa o disable he lach proecion. Volage feedback pin. Connec a phoo-coupler wih i o close he conrol loop and achieve he regulaion. 3 CS Curren sense pin, connec i o sense he MOSFET curren 4 GND Ground 5 Gae drive oupu o drive he exernal MOSFET 6 Supply volage pin 7 NC Unconneced Pin 8 HV Connec his pin o Line/ Neural of AC main volage hrough a resisor o provide he sarup curren for he conroller. If volage increase o rip he poin of UVLO(on), his HV loop will be urned off o reduce he power loss on he sarup circui. An inernal resisor divider beween HV o GND pin will monior AC line volage o acivae Brown-in/ou funcion. 2

3 Block Diagram HV HV CC Vcc OVP Comparaor UVLO 28.8V - OVP 31V UVLO On/off PG - Vcc OK Vref OK Inernal Bias&Ref Proecion Lach UVLO OFF -1.4V Discharge - Vcc Sof -Drive PDR COMP RFB Bias Green Mode OSC Conrol Vf 3R R - Discharge PWM Comparaor S R SET CLR Q Q Bias CS LEB Σ V CS_MAX Slope Com. OCP Comparaor - OLP Comparaor Ex. OTP 100uA V/0.95 OTP Sample COMP 4.6V - Delay Time Delay OSCP Delay Time S SET Q Proecion Vref CS-OVP COMP PG ½ Couner R CLR Q HV RBH - BNO Comparaor Debounce and Delay Time BNO Ex. OTP PDR S R SET CLR Q Q Lach RBL X-cap discharge Delay Time S SET Q Discharge RBH:RBL =125:1 PG R CLR Q - In. OTP GND 3

4 Absolue Maximum Raings Supply Volage HV COMP, OTP, CS Maximum Juncion Temperaure Sorage Temperaure Range Package Thermal Resisance (SOP-8/SOP-7, JA) Power Dissipaion (SOP-8/SOP-7, a Ambien Temperaure = 85 C) Lead emperaure (Soldering, 10sec) ESD Volage Proecion, Human Body Model (excep HV Pin) ESD Volage Proecion, Machine Model (excep HV Pin) ESD Volage Proecion, Human Body Model (HV Pin) ESD Volage Proecion, Machine Model (HV pin) Gae Oupu Curren -0.3V ~ 30V -0.3V ~ 650V -0.3V ~ 6V -0.3V ~ 0.3V 150 C -65 C ~ 150 C 160 C/W 250mW 260 C 2.5KV 250V 1KV 200V 300mA/-800mA Cauion: Sress exceeding Maximum Raings may damage he device. Maximum Raings are sress raings only. Funcional operaion above he Recommended Operaing Condiions is no implied. Exended exposure o sress above Recommended Operaing Condiions may affec device reliabiliy. Recommended Operaing Condiions Iem Min. Max. Uni Operaing Juncion Temperaure C Supply Volage V HV resisor Value (AC Side) K HV o GND Capacior Value pf COMP Pin Capacior 1 10 nf CS Pin Capacior Value pf OTP Pin Capacior Value nf 4

5 Elecrical Characerisics (T A = 25 C unless oherwise saed, =15.0V) PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS High-Volage Supply (HV Pin) High-Volage Curren Source < V CC_ON, HV=500V I HV ma HV Discharge capabiliy HV=500V I HV_DIS ma HV Pin Toal Inpu Curren > V CC_ON, HV=500 V DC I HV_LEAK 35 A HV Pin Brown-In Level V HVBO V DC HV Pin Brown-ou Level V HVBI V DC HV Pin BNO Hyseresis V HVBI - V HVBO ΔV HV 15 V DC Brown-in De-bounce Time V COMP > V ZDCH T D_HVBI 170 S Brown-ou Deecion Delay ime T D_HVBO 68 ms HV Pin Min. Operaion Volage V HV_MIN 45 V X-Cap discharge Deecion Delay ime V COMP > V ZDCH T D_XCAP 68 ms Supply Volage ( Pin) Sarup Curren HV=500V I CC_ST A V COMP =3V I CC_OP1 1.5 ma Operaing Curren V COMP =0V I CC_OP2 0.3 ma (wih 1nF load on pin) Auo recover mode I CC_OPA 0.43 ma Lach mode I CC_OPL 0.43 ma UVLO(OFF) V CC_OFF V UVLO(ON) V CC_ON V PDR V CC_PDR V CC_OFF -1.4V V V CC_OFF HVBI Level HV> V HVBI (Fig. 1) V CC_HVBI 3.8V OVP Level V CC_OVP V OVP De-bounce Time T D_OVP 80 S V 5

6 PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS Oscillaor for Swiching Frequency Frequency F SW khz Swapping Frequency F SW_SWA ±8 % Green Mode Frequency F SW_GREEN khz Modulaion Frequency F SW_MOD 200 Hz F SW Temp. Sabiliy *, -40 C ~105 C F SW_TS % F SW Volage Sabiliy * F SW_VS 0 1 % Maximum On Time MXD % OSCP (Oupu Shor Circui Proecion) V CC-OFF OSCP Trip Level * V CC_OSCP 3.8V OSCP Delay Time *, Exclude sof sar ime. T D_OSCP 10 ms Volage Feedback (COMP Pin) Inpu Volage o Curren-Sense Aenuaion * A V 1/4 V/V Comp Impedance V COMP =3V Z COMP 42 k Open Loop Volage V COMP_OPEN V OLP Tripped Level V OLP V PWM Mode Threshold VCOMP F SW_SW X 0.9 (Fig. 2) V P V Green Mode Threshold VCOMP F SW_GREEN X1.1 (Fig. 2) V G V Zero Duy Threshold Zero Duy V ZDC 1.9 V VCOMP on Burs mode Hyseresis V ZDCH 100 mv Curren Sensing (CS Pin) Maximum Inpu Volage V CS_MAX V Leading Edge Blanking Time T LEB 300 ns Delay o Oupu T PD 70 ns Slope Compensaion Level *, 0%-85% Linearly V SLP_L V Slope Compensaion Posiion *, 0%-85% Linearly VSLP 0 85 % V 6

7 PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS OVP CS Pin OVP Trip Curren Level DC V CSOVP V AC(High o Low) V CSOVP V De-bounce Cycle T D_CSOVP 160 S Sample Delay Time * T S_CSOVP 2 S Gae Drive Oupu ( Pin) Oupu Low Level =15V, Io=20mA V OL 0-1 V Oupu High Level =15V, Io=20mA V OH 8 - V Rising Time Load Capaciance= 1000pF T r - 50 ns Falling Time Load Capaciance= 1000pF T f - 20 ns Pin Clamping Volage = 21V,1nF on pin V O_CLAMP 12 V Source capabiliy *, Load Capaciance= 33nF I SOURCE 300 ma Sink capabiliy *, Load Capaciance=33nF I SINK 800 ma OLP (Over Load Proecion) OLP Delay Time T D_OLP ms Sof Sar Sof Sar Duraion * T SS 6 ms Inernal OTP OTP Tripped Level * T INOTP 150 C OTP Hyseresis * T INOTP_HYS 30 C OTP De-bounce Time * T D_INOTP 160 S Over Temperaure Proecion(OTP Pin) OTP Pin Source Curren I OTP A Turn-On Trip Level V OTP_ON V Turn-Off Trip Level V OTP_OFF V OTP pin de-bounce ime V COMP > V ZDCH T D_OTP 300 s *: Guaraneed by design. 7

8 UVLO(ON) _HVBI UVLO(ON) _HVBI UVLO(OFF) UVLO(OFF) AC recovery level AC recovery level AC AC > _HVBI AC recovery < _HVBI AC recovery Fig. 1 V CC_HVBI & AC recovery Frequency wih Swapping 70KHz 60KHz 26KHz 20KHz V ZDC V ZDCH V G V P Vcomp Fig. 2 V COMP vs. PWM Frequency 8

9 Typical Performance Characerisics 9

10 Typical Performance Characerisics 10

11 Applicaion Informaion Operaion Overview As long as he requiremen for green power becomes a rend and he power saving is geing more and more AC Inpu EMI Filer ~ ~ imporan for he swiching power supplies and swiching adapors, he radiional PWM conrollers are no able o suppor such new requiremens. Due o he cos and size limi, he PWM conroller designer is bound o HV inegrae wih more funcions o reduce he exernal par OTP couns. The is ideal for hese applicaions. Is GND CS deailed feaures are described as below. Inernal High-Volage Sarup Circui and Under Volage Lockou (UVLO) The radiional circui provides he sarup curren hrough a sarup resisor o power up he PWM conroller. However, i consumes much significan power o mee he curren power saving requiremen. In mos cases, sarup resisors carry larger resisance and spend more ime o sar up. To achieve he opimized opology, as shown in Fig. 11, is implemened wih a high-volage sarup circui for such requiremen. A sarup, he high-volage curren source sinks curren of AC Line/or Neural o provide sarup curren and charge he capacior C1 conneced o. A he sarup ransien, he HV curren will supply around 2.8mA o Vcc capacior unil his volage reaches he UVLO hreshold. By using such configuraion, he urn-on delay ime will be almos same no maer under low-line or high-line condiions. Fig. 11 As rips UVLO(OFF), HV pin will recharge capacior ill volage rises back o UVLO(ON) again. Since hen, HV pin would no longer charge he capacior and insead, send a gae drive signal o draw supply curren for from he auxiliary winding of he ransformer. Tha minimizes he power loss on he sar-up circui successfully. An UVLO comparaor is embedded o deec he volage across he pin o ensure he supply volage enough o power on he and in addiion, o drive he power MOSFET. As shown in Fig. 12, a hyseresis is provided o preven shudown from he volage dip during sarup. The urn-on and urn-off hreshold level are se a 16V and 7V, respecively. 11

12 Line Volage V CC_ON V CC_OFF HV Curren VHV(peak) VHVBI 2.8mA VHVBO curren ~ 0mA (off) Operaing Curren (Supply from Auxiliary Winding) _ON AC OK area Sarup Curren _OFF Fig. 12 Brown in/ou Proecion Non-Swiching Swiching Non- Swiching The feaures Burn-in/ou funcion on HV pin. As he buil-in comparaor deecs he half wave recify line volage condiion, i will shu off he conroller o preven from any damage. Fig. 13 shows he operaion. When V HV < HVBO, he gae oupu will remain off even when he already reaches UVLO(ON). I herefore forces he hiccup beween UVLO(ON) and UVLO(OFF). Unless he line volage rises over HVBI V AC, he gae oupu will no sar swiching even as he nex UVLO(ON) is ripped. A hyseresis is implemened o preven he false-riggering during urn-on and urn-off. Fig. 13 Curren Sensing, Leading-Edge Blanking and he Negaive Spike on CS Pin The ypical curren mode PWM conroller feedbacks boh curren signal and volage signal o close he conrol loop and achieve regulaion. The deecs he primary MOSFET curren across CS pin o conrol in peak curren mode and also limi he pulse-by-pulse curren. The maximum volage hreshold of he curren sensing pin is se a 0.7V. Thus he MOSFET peak curren can be calculaed as: 0.7V IPEAK (MAX ) RS A 300nS leading-edge blanking (LEB) ime is designed in he inpu of CS pin o preven false-riggering from he curren spike. In he low power applicaions, if he oal pulse widh of he urn-on spikes is less han 150nS and he negaive spike on he CS pin does no exceed -0.3V, he R-C filer (as shown in Fig. 14) is free o eliminae. 12

13 However, he oal pulse widh of he urn-on spike is relaed o he oupu power, circui design and PCB layou. I is srongly recommended o add a small R-C filer (as shown in Fig. 15) for larger power applicaion o avoid he CS pin from being damaged by he negaive urn-on spike. Oupu Sage and Maximum Duy-Cycle A CMOS buffer wih oupu sage of ypical 300mA driving capabiliy is incorporaed o drive a power MOSFET direcly. And he maximum duy-cycle of is limied o 85% o avoid he ransformer sauraion. CS GND 150ns blanking ime Can be removed if he negaive spike is no over spec. (-0.3V). Fig. 14 Volage Feedback Loop The volage feedback signal is provided from he TL431 on he secondary side hrough he phoo-coupler o he COMP pin of. Similar o UC384X, is inpu sage is wih a diode volage offse o feed he volage divider wih 1/4 raio, ha is, Vcs(PWM COMPARATOR 1 ) (VCOMP 4 VF ) A pull-high resisor is embedded inernally o opimize he exernal circui. Inernal Slope Compensaion A fundamenal issue of curren mode conrol is he sabiliy problem when is duy-cycle is operaed for more han 50%. To sabilize he conrol loop, he slope compensaion is required in he radiional UC384X design by injecing he ramp signal from he RT/CT pin hrough a coupling capacior. has inernal slope compensaion circui o simplify he exernal circui design. Oscillaor and Swiching Frequency GND CS R-C filer is required when he negaive spike exceeds -0.3V or he oal spike widh is over 300nS LEB period. Fig. 15 The fixes he swiching frequency a 65kHz inernally o opimize is performance in EMI, hermal reamen, componen sizes and ransformer design. Dual-Oscillaor Green-Mode Operaion There are many differen opologies has been implemened in differen chips for he green-mode or power saving requiremens such as burs-mode conrol, skipping-cycle mode, variable off-ime conrol ec. The basic operaion heory of all hese approaches inended o reduce he swiching cycles under ligh-load or no-load condiion eiher by skipping 13

14 some swiching pulses or reduce he swiching frequency. By using LD proprieary dual-oscillaor echnique, he green-mode frequency can be well conrolled and furher o avoid he generaion of audible noise. mechanism, he average inpu power will be minimized, so ha he componen emperaure and sress can be conrolled wihin he safe operaing area. BNO Deecing Frequency Swapping The is buil in wih frequency swapping funcion, which makes i easy for he power supply designers o opimize EMI performance and sysem cos. The frequency swapping is inernally se for 8%. V CC_ON V CC_OFF COMP OLP 2nd UVLO(OFF) OLP Couner Rese OLP Delay Time On/Off Conrol VOLP Pulling COMP pin below VFB_B will immediaely disable he gae oupu of. Remove he pull-low signal OLP rip Level o rese i. Over Load Proecion (OLP) - Auo Recovery Swiching Non-Swiching Swiching To proec he circui from being damaged during over load condiion and shor or open loop condiion, he is implemened wih smar OLP funcion. feaures auo recovery funcion of i, see Fig. 16 for he waveform. In he example of he faul condiion, he feedback sysem will force he volage loop ener oward he sauraion and hen pull he volage high on COMP pin (VCOMP). As he V COMP ramps up o he OLP ripped level (4.6V) and says for more han he OLP delay ime, he proecion will be acivaed and hen urn off he gae oupu o sop he swiching of power circui. The OLP delay ime is se by inernal high frequency couner. I is o preven he false riggering from he power-on and urn-off ransien. A divide-2 couner is implemened o reduce he average power under OLP behavior. As soon as OLP is acivaed, he oupu will be lached off and he divide-2 couner will sar o coun he number of UVLO(OFF). The lach will no be released unil he 3rd UVLO(OFF) poin is couned, afer ha he oupu will resume o swich again. Wih he proecion Fig. 16 OVP (Over Volage Proecion) on Lached Mode The V GS raings of he nowadays power MOSFETs are mosly wih 30.5V maximum. To proec he V GS from he faul condiion, LD5761 is implemened wih OVP funcion on. As he volage is larger han he OVP hreshold volage, i will shu off he oupu gae drive circui simulaneously and sop swiching he power MOSFET. The OVP is lach-off ype of proecion. Once he rips OVP level (which is usually caused by he feedback loop opened), i will be lached off. Turn off AC power o le fall below PDR level o release overvolage proecion. And hen resar he power o resume he operaion. The de-lach level is defined by inernal PDR. See Fig. 17 for is operaion. 14

15 OVP Level OVP Tripped ha he NTC resisance will increase and o raise VOTP above 0.95V. Then, recycle he AC main power. The deailed operaion is show in Fig. 18. UVLO(ON) UVLO(OFF) PDR Lach Released 1.05V V(-)Lach OTP Release 0.95V OTP Swiching Non- Swiching Swiching -ON -OFF PDR AC inpu Volage AC Off AC On ( Recycle) AC inpu Volage AC Off Lach Released AC On (Recycle) Fig. 17 On-Chip OTP - Auo Recovery An inernal OTP circui is embedded inside he o provide he wors-case proecion for his conroller. When he chip emperaure rises higher han he rip OTP level, he oupu will be disabled unil he chip is cooled down below he hyseresis window. Exernal OTP - Lached Mode The OTP circui is implemened o sense wheher here is any ho-spo of power circui like power MOSFET or oupu recifier. Typically, an NTC is recommended o connec wih OTP pin. The NTC resisance will decrease as he device or ambien is in high emperaure. The relaionship is described as below. VOTP 100μA R NTC When V OTP<V OTP-OFF (ypical1.05v), i will rigger he proecion o shu down he gae oupu and lach off he power supply. The conroller will remain lached unless he drops below 7V (power down rese) and says on UVLO condiion. Two condiions are required o resar he IC successfully, o cool down he circui so Swiching Non-Swiching Swiching Fig. 18 Pull-Low Resisor on he Gae Pin of MOSFET The consiss of an ani-floaing resisor wih pin o proec he oupu from damage in abnormally operaion or condiion due o false riggering of MOSFET. Even so, we sill recommend adding an exernal one a he MOSFET gae erminal o provide more proecion in case of disconnecion of gae resisor R G during power-on. In such single-faul condiion, as shown in Fig. 19, he resisor R8 can provide a discharge pah o avoid he MOSFET from being false-riggered by he curren hrough he gae-o-drain capacior C GD. Therefore, he MOSFET should be always pulled low and placed in he off-sae as he gae resisor is disconneced or opened in any case. 15

16 V BULK Negaive-riggered Parasiic SCR. Small negaive spike on HV pin will cause he lachup beween and GND. 0V dv i Cgd bulk d HV Rg C GD Oher HV process wih parasiic SCR R8 GND Fig. 20 GND CS 0V Curren limi resisor for Prevening damage from Negaive volage (recommended) This resisor would proec he MOSFET from being false riggered by he curren hrough C GD, if R G is disconneced. Fig. 19 HV Proecion Resisor on he Hi-V Pah In some oher Hi-V process and design, here may be a parasiic SCR caused around HV pin, Vcc and GND. As shown in Fig. 20, a small negaive spike on he HV pin may rigger his parasiic SCR and cause lach-up beween and GND. I may damage he chip because of he equivalen shor-circui induced by such lach-up behavior. Leadrend s proprieary of Hi-V echnology will eliminae parasiic SCR in. Fig. 21 shows he equivalen Hi-V srucure circui of. So ha is more capable o susain negaive volage han similar producs. However, a 10K resisor is recommended o add in he Hi-V pah o play as a curren limi resisor as a negaive volage is applied. GND Parasiic effec beween HV, Vcc and GND Fig. 21 Oupu Over Volage Proecion (CS Pin) Lached Mode Proecion An oupu overvolage proecion is implemened in he, as shown in Fig. 22 and 23. The auxiliary winding volage is refleced o secondary winding and herefore he fla volage on he CS pin is proporional o he oupu volage. By sensing he auxiliary volage via he divided resisors, can sample his fla volage level afer some delay ime o perform oupu over volage proecion. This delay ime is used o ignore he volage ringing from leakage inducance of PWM ransformer. The sampling volage level is compared wih inernal hreshold volage 0.2V. If he sampling volage exceeds he OVP rip level, an inernal couner sars couning subsequen OVP evens. The couner has been added o preven incorrec OVP deecion which migh occur during ESD or lighning evens. 16

17 However, if ypically 10 cycles of subsequen OVP evens are deeced, he OVP circui swiches he power MOSFET off. Besides, he choices beween D1 and C1 paricularly need o be noiced. When power MOSFET gae urns off, he speed of CS pin volage decreasing affec he OVP proecion as shown in Fig. 23. The red line shows he siuaion ha CS discharge oo slow o seady sae, i will cause misrigger of OVP proecion. The recommended range of C1 is 47~390pF, D1 rr 50nS(EX: BAV21W, BAV103 ). As he proecion is lached, he converer resars only afer he inernal lach is rese. Thus he oupu over volage can be calculaed as: R1 ( VAUX VF ) 0.2V R1 R2 1.5us 1us Delay Sample D1 AUX OVP Debouce 10 cycle 0.2V CS C1 R2 R1 R S Fig. 22 Ou AUX Winding Delay Sample CS/OVP Fig

18 Package Informaion SOP-7 Symbols Dimensions in Millimeers Dimensions in Inch MIN MAX MIN MAX A B C D F H I J M θ

19 SOP-8 Symbols Dimensions in Millimeers Dimensions in Inch MIN MAX MIN MAX A B C D F H I J M θ Imporan Noice Leadrend Technology Corp. reserves he righ o make changes or correcions o is producs a any ime wihou noice. Cusomers should verify he daashees are curren and complee before placing order. 19

20 Revision Hisory REV. Dae Change Noice 00 01/27/2014 Original Specificaion /22/2014 Updae 02 12/29/2014 Modify V HVBI, F SW, F SW_GREEN, V CS_MAX, V CS_MIN, T S_CSOVP 03 03/26/2015 Modify curren limi and add no-load power consumpion 230Vac, Modify V CC_OSCP 04 10/05/ Modify V CSOVP-2 2. Add Recommended Operaing Condiions: OTP Pin Capacior Value 05 03/17/2016 Add Recommended Operaing Condiion: C HV o GND 06 Add CS_OVP descripion 20

LD5761B 04/27/2015. High Voltage with Two-Level Frequency. Green-Mode PWM Controller. General Description. Features. Applications. Typical Application

LD5761B 04/27/2015. High Voltage with Two-Level Frequency. Green-Mode PWM Controller. General Description. Features. Applications. Typical Application REV: 00 General Descripion High Volage wih Two-Level Frequency The is a Green Mode PWM IC which is buil-in wih brown-in/ou funcions in a SOP-7/SOP-8 package. The device could minimize he componen couns,