AN UVLO (Under Voltage Lock Out) FUNCTION Calculation of Minimum Value of IGBT external Gate Resistance RG. Table 2-1.

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1 A p p l i c a i o n Noe AN318 IGBT/Power MOSFET Gae Drive Phoocoupler Technical Markeing Deparmen Compound Semiconducor Devices Business Division Analog & Power Devices Business Uni Renesas Elecronics Corporaion 1. Inroducion The recen rise in awareness of environmenal issues and he corresponding demand for energy savings has seen an increase in he use of inverer echnology in a wide range of fields, including indusrial machinery, power equipmen, and home appliances. The demand for indusrial inverers such as general-purpose inverers and AC servos is growing srongly in he radiional European and Norh American markes and is also aking off in emerging markes. Demand for inverer echnology is also expeced o grow in he expanding clean energy fields of solar and wind power generaion. One of he mos common semiconducor devices used in hese inverers is an IGBT (Insulaed Gae Bipolar Transisor). This applicaion noe describes he feaures and applicaions of PS955/PS935 as an example o describe is characerisics, is inernal gae driving circui and describe he exernal gae resisance requiremen and he deails of gae driver phoocoupler power dissipaion in relaion o MOSFET / IGBT gae charge based on desired swiching frequency o urn-on and urn-off he MOSFET / IGBT. Table 1-1. Specificaion Ouline of PS955/PS935 BV (kvr.m.s.) VCC (V) IO (PEAK) Par No. Package MAX. MAX (A) MAX. PS955 Noe 1 PS935 Noe 1 8-pin DIP -pin SDIP Noe: 1. Buil-in UVLO funcion. Produc overview ICCH/ICCL (ma) MAX. IFLH (ma) MAX. Figure -1 shows he equivalen circui of he PS955/ PS935. The PS955 is an 8-pin DIP and he PS935 is an 8-pin SDIP high-speed phoocoupler. These conain a GaAIAs ligh emiing diode () on he inpu side and phoo deecor IC ha inegraes a phoodiode (PD), signal processing circui, large-curren circui and UVLO is configured on he side ha oupus signals o he IGBT. The phoo deecor IC is fabricaed wih he Bi-CMOS NC 1 ANODE CATHODE 3 NC PLH/PHL (µs) MAX. process proven in oher Renesas Elecronics IGBT-driving phoocouplers, enabling boh a high oupu curren (IO =.5 A MAX.) and low circui curren (ICC = ma TYP.), which enables high-emperaure operaion (TA = 11 C MAX.). Figure -1. PS955/PS935 Equivalen Circui PD Signal processing circui SHIELD UVLO PS /3 5.5/.5.1 5/ /3 5.5/.5.1 5/5 Oupu drive circui 8 Vcc 7 Vo Vo 5 VEE ANODE 1 CATHODE CATHODE 3 NC PD Signal processing circui SHIELD UVLO PS935 Noe: NC (No Connecion) should be open or connec o ground of side and should no connec o any bias volage. The feaures of he PS955/PS935 are lised below. Table -1 shows he ruh able. For more feaure deails, refer o he daa shee. 8 Vcc 7 Vo VEE 5 VEE Feaures Large oupu peak curren (IO =.5 A max.) High-speed swiching (PLH/PHL = CMH/CML PWD (µs) (kv/µs).5μs max.) MAX. MIN. Large operaing volage range (VCC-VEE = 15 o 3 V) Buil-in UVLO(Under Volage Lock Ou) funcion Low power consumpion: ICCH, ICCL = 3 ma MAX. Long creepage disance (8 mm MIN.: PS955L1, PS955L, PS935L) Complies wih inernaional safey sandards: UL, VDE, CSA, SEMKO High insananeous common mode rejecion volage (CMH, CML =±5 kv/μs min.) Operaing Ambien Temperaure ( TA = - o +11 C) Oupu drive circui 1

2 Table -1. Truh Table VCC-VEE Volage Rise (TURN-ON) VCC-VEE Volage Drop (TURN-OFF) Oupu (VO) OFF o 3 V o 3 V L ON o 1.8 V o 9.5 V L ON 1.8 o 13. V 9.5 o 1.5 V TRANSITON ON 13. o 3 V 1.5 o 3 V H 3. UVLO (Under Volage Lock Ou) FUNCTION The UVLO circui holds VO a low level when he PS955/ PS935 power supply volage is insufficien. If he IGBT s gae volage (VO in he PS955/PS935) drops during on sae, he VCE (sa) of he IGBT becomes larger and i migh cause a large amoun of power o dissipae, leading o overheaing and failure of he IGBT. To preven his, if he PS955/PS935 deecs ha is power supply volage (VCC VE) is insufficien, i holds VO a low level o proec he IGBT. As shown in Figure 3-1, when he PS955/PS935 power supply volage (VCC VE) is low (when he power supply volage is rising from V), he PS955/PS935 holds he VO oupu a low level unil he volage rises o VUVLO+, even if he is on. Conversely, when he PS955/PS935 power supply volage (VCC VE) is falling (changing o a negaive volage) he VO oupu is high level unil he volage reaches VUVLO, bu if he volage falls below VUVLO, he PS955/PS935 pulls he VO oupu down o low level even if he is on. Therefore, if he PS955/PS935 power supply volage (VCC VE) falls below VUVLO (9.5 o 1.5 V) due o some error, he VO oupu of he PS955/PS935 will go low even if he is on. When he power supply volage (VCC VE) subsequenly rises o above VUVLO+ (1.8 o 13. V), he VO oupu goes high again (wih he on). +5V H L Figure 3-1. Oupu Volage vs. Power Supply Volage Oupu Volage vs. Power Supply Volage Oupu volage Vo (V) VO (V) Vo vs. VCC-VEE VCC-VEE (V) Power supply volage VCC-VEE (V). DESIGN OF IGBT GATE DRIVE CIRCUIT PS955.1uF Vcc=15V RG VEE=-5V UVLO - (11V) UVLO + (1.3V) +HV DC (P line) 3-phase oupu -HV DC (N line) Figure -1 shows an example of an IGBT drive circui using he PS955. The gae resisance seings described in secions.1 and. are implemened. PS935 can be used wih same circui o change pin o VEE, pin 1 o H and pin o L..1. Calculaion of Minimum Value of IGBT exernal Gae Resisance RG (1) Calculaion from he phoocoupler side The exernal gae resisor (RG) mus be seleced so ha he peak oupu curren of he PS955/PS935 (IOL(PEAK)) does no exceed is maximum raing. The minimum value of he gae resisor (RG) can be approximaed by using he following expression: RG {(VCC VEE) VOL}/IOL(PEAK) (.1) VCC VEE: PS955/PS935 power supply difference (VEE = when no using a negaive power supply) VOL: PS955/PS935 low-level oupu volage. Calculae he minimum value of he exernal gae resisor (RG) under he following condiions: IOL(PEAK) =.5 A VCC VEE = V Volage drops o VOL = 3.5 V a TA = - C (as a wors case) while IOL =.5 A. Characerisics curves showing he relaionship beween he low-level oupu volage (VOL) and low-level

3 oupu curren (IOL) are provided in Figure. for reference. These seings make allowances for operaion under low emperaures ( C). Noe ha because he low-side MOSFET volage drops more han he high-side MOSFET volage in he PS955/PS935, he minimum value of he exernal gae resisor (RG) is calculaed based on he low-side MOSFET. From equaion (.1): RG {(VCC VEE) VOL}/IOL(PEAK) = ( 3.5)/.5 =. Ω Low Level Oupu Volage VOL (V) 8 LOW LEVEL OUTPUT VOLTAGE vs. LOW LEVEL OUTPUT CURRENT Low Level Oupu Curren IOL (A) Figure -. VOL vs. IOL Characerisics () Calculaion from he IGBT side The charge characerisics of he IGBT s gae are described in he IGBT s daa shee, bu in general, he characerisics curve is as shown in Figure -3. VGS Gae-Source Volage (V) VCC= 3V, VEE= GND, IF= ma Qgs Qgd Qg Qg, Charge (nc) Figure -3. VGS vs. Qg Characerisics Ta= +11 C Ta= - C V(DR) =Peak drive volage Ta= +5 C In his graph: Qge is he charge beween he gae and he emier Qcg is he charge beween he collecor and he gae Qg is he oal gae charge The gae charge is expressed as follows: Q = C x V, wih Q indicaing he oal charge. The relaionship beween he gae capaciance, he swiching ime, and he gae driving curren is as follows: dq/d = C x dv/d = I In his case, if s represens he swiching ime required by he sysem, he curren ha mus be supplied o he gae (IG) is indicaed by: IG = QG/s Because a consan driving volage V(DR) is used, he relaionship beween he gae peak curren and he oal gae resisance (Rg) is as follows: Rg = V(DR)/IG, wih Rg indicaing he sum of he driver s oupu impedance, he exernal gae resisance, and he gae s own series resisance. Therefore, in order o saisfy he swiching ime required by he sysem, he exernal gae resisance calculaed from he phoocoupler side (RG) mus be smaller han he oal gae resisance calculaed from he IGBT side (Rg). If s is unable o be saisfied, you will have o consider selecing a phoocoupler ha can drive a larger curren, or aaching an exernal curren amplifier (buffer).. Checking he allowable dissipaion of he PS955/PS935 and adjusing RG The power consumpion of he PS955/PS935 (PT) is a oal of he power consumpion of he on he inpu side (primary side) (PD) and he power consumpion of he phoo deecor IC on he oupu side (secondary side) conneced o he IGBT (PO). PT = PD + PO (..1) (1) power consumpion The power consumpion of he on he inpu side (primary side) (PD) is calculaed as follows: PD = IF x VF x Duy raio (..) () Phoo deecor IC power consumpion The power consumpion of he phoo deecor IC on he oupu side (secondary side) (PO) is calculaed as follows: PO = PO(Circui) + PO(Swiching) (..3) PO(Circui) is he circui power consumpion of he phoo deecor IC (he power consumed by ICC). PO(Swiching) is he power consumpion of he phoo deecor IC required o charge and discharge he gae capacior (he power consumed by IO). 1. Circui power consumpion of phoo deecor IC: Po(Circui) PO(Circui) = ICC x (VCC VEE) (..) ICC is he circui curren supplied o he phoo deecor IC. VCC VEE is he power supply difference of he phoo deecor IC.. Power consumpion of phoo deecor IC required o charge and discharge he IGBT gae capacior PO(Swiching) = Esw(RG, QG) x fsw (..5) ESW(RG, QG) is he per-cycle power consumed when charging he IGBT gae capacior (see Figure. and Figure.5). fsw is he swiching frequency. 3

4 Figure -. Power Consumpion Waveform During Swiching of PS955/PS935 8 Q 7 g = 1nC Q g = 5nC Q g = 1nC Energy Per Swiching Cycle Esw [μj] Vo Io Po (= Io x Vo) Esw (on) Esw (off) Esw (Qg, RG) = Esw (on) + Esw (off) Gae Resisance RG [Ω] Figure -5. Swiching Loss per Cycle of PS955/PS Power consumpion of phoo deecor IC From he calculaions in (..3), (..) and (..5), he power consumpion of he phoo deecor IC is as follows: PO = PO(Circui) + PO(Swiching) = ICC x (VCC VEE) + Esw(RG, QG) x fsw (..) (3) Checking he allowable dissipaion of he PS955/ PS935 and adjusing RG When used in he circui shown in Figure -1, he power consumpion of he PS955/PS935 is as follows, calculaed under he condiions of RG =. Ω, Duy (MAX.) = 8%, QG = 5 nc, f = khz, IF (MAX.) = 1 ma, and TA = 85 C: 1. Power consumpion of inpu side (primary side, ) (PD) From he calculaion in (..): PD = IF x VF x Duy raio = 1mA x 1.8 V x.8 = 3 mw. Power consumpion of oupu side (secondary side, phoo deecor IC) (PO) From he calculaion in (..): PO = ICC x (VCC VEE) + Esw(RG, QG) x fsw = 3 ma x V +3.5µJ x khz = mw + 7 mw = 13 mw < 178 mw for PS955 = 13 mw < mw for PS935 (absolue maximum allowable dissipaion for phoo deecor IC when TA = 85 C) The exernal gae resisance RG has a significan effec on he performance of he IGBT, so be sure o selec he righ gae resisor for your gae driver design. A smaller gae resisance means faser swiching o charge and discharge he IGBT s inpu capacior, which leads o lower swiching dissipaion. However, a smaller gae resisance also leads o a larger volage variaion (dv/d) and curren variaion (di/ d) during swiching. I is herefore imporan o evaluae he acual operaion of he IGBT by referring o he relevan echnical documens before selecing he gae resisor. 5. PS955/PS935 PERIPHERAL CIRCUIT 5.1 Layou 1. To minimize floaing capaciance beween he primary side and he secondary side (he inpu and he oupu), be sure o place he circuis so ha hey are no oo close o he primary-side and secondary-side wiring paerns on he board, and ha here is no cross-wiring if muli-layer wiring is being used.. To preven ransien noise from he IGBT from affecing he PS955/PS935, keep he IGBT collecor/emier circui paern and DC lines (P and N lines) of he inverer circui hrough which a large curren flows as far away as possible from he PS955/PS935 driver and VCC and VO lines. 3. Design he layou of he bypass capacior (.1 μf or higher) beween VCC VEE on he secondary side (oupu side) of he PS955/PS935 so as o be as close as possible o he VCC (pin 8) and VEE (pin 5) of he PS955/PS935 (so ha he PS955/PS935 pins and capacior pins are as close as possible).

5 5. driver Design he driver so ha he recommended curren (IF) and volage (VF) are applied o he. Table 5-1 shows he recommended operaing condiions for he. Iem Symbol MIN. TYP. MAX. Uni Inpu volage (OFF) VF (OFF) -.8 V Inpu curren (ON) IF (ON) ma Table 5-1. Recommended Operaing Condiions for PS955/PS935 of he PS955/PS935 and he IGBT (off oal MAX.) and he minimum value of he oal urn-on ime of he PS955/PS935 and he IGBT (on oal MIN.),or higher. dead off oal MAX. on oal MIN. = (PHL MAX.(PC) + off MAX.(IGBT)) (PLH MIN.(PC) + on MIN.(IGBT)) = (PHL MAX.(PC) PLH MIN.(PC)) + (off MAX.(IGBT) on MIN.(IGBT)) = PDD (PC) + (off MAX. on MIN.) (IGBT) In he above equaion, (PC) is he response ime of he PS955/ PS935 phoocoupler and (IGBT) is he response ime of he IGBT. To ensure ha he is urned off properly, even if common mode noise (CML) occurs, we recommend applying a reverse bias o he wihin he range indicaed by he recommended operaing condiions in Table 5-1. Similarly, o ensure ha he is urned on properly, even if common mode noise (CMH) occurs, we recommend specifying as large a curren (IF) as possible, wihin he range indicaed by he recommended operaing condiions in Table 5-1. PS955 No1 (Upper arm) PS955 No (Lower arm) IGBT 1 (Upper arm) IGBT (Lower arm) Figure -3. Deadime (dead) IF IF Io Io dead } } Phoocoupler inpu signal ( inpu signal) IGBT oupu curren. Specifying dead ime As shown in Figure.1, in he inverer circui, IGBT 1 and IGBT on he upper and lower arms alernaely swich on and off, oupuing a signal o he moor or oher load. If here is insufficien dead ime, IGBT 1 and IGBT on he upper and lower arms swich on a he same ime, causing a shor-circui curren o flow, damaging he IGBTs (see Figure., example of PS955). PS955 No1 PS955 No +HV DC (P line) IGBT1 ON IGBT OFF Upper arm Oupu Lower arm -HV DC (N line) Figure.1 Inverer Circui Operaing Normally PS955 No1 +HV DC (P line) IGBT1 ON Upper arm In he PS955/PS935, he ransmission delay ime difference beween any wo pars has been prescribed o make specifying dead ime easy (his ime is PDD = PHL PLH = ±1 ns). See he PS955/PS935 daa shee for deails. Noe ha PDD in he PS955/PS935 mus be measured under he same emperaure and measuremen condiions as PHL and PLH. The board mus herefore be laid ou so ha he ambien condiions of he upper and lower arms of he phoocoupler are he same. Also be sure o horoughly evaluae he dead ime using he acual device, and allow a sufficien margin in your design. 7. CALCULATION OF JUNCTION TEMPERATURE 1. PS955/PS935 hermal resisance model TJE Phoo deecor IC TJD PS955 No IGBT ON Oupu Lower arm 1 3 -HV DC (N line) Figure. Inverer Circui When Shor-Circui Occurs Dead ime (dead) (see Figure.3, example of PS955) is specified in order o preven IGBT1 (upper arm) and IGBT (lower arm) urning on a he same ime, and is usually he difference beween he maximum value of he oal urn-off ime Ta Figure 7-1. Thermal Resisance Model of PS955/PS935 5

6 Figure 7.1 shows he hermal resisance model of he PS955/PS935. The model used has wo hea sources: he and he phoo deecor IC. TJE juncion emperaure TJD Ligh receiving IC juncion emperaure Ta Ambien emperaure θ1 Thermal resisance beween -ambien emperaure θ Thermal resisance beween -ligh receiving IC θ3 Thermal resisance beween ligh receiving IC-ambien emperaure. Juncion emperaure calculaion In he above model, he juncion emperaure of and phoo deecor IC is calculaed as follows: Also an example of PS935, calculaing he juncion emperaure using (7.1) and (7.), wih PE = 7mW, PO (=PD) = 1 mw, and TA = 85 C: TJE TJD = R11 x PE + R1 x PD + TA = 93 C/W x 7 mw + 1 C/W x 1 mw + 85 C = 18.3 C = R1 x PE + R x PD +TA = 1 C/W x 7 mw + 1 C/W x 1 mw + 85 C = 18.9 C Se juncion emperaures TJE and TJD o values lower han 15 C. TJE = R11 x PE + R1 x PD + TA (7.1) TJD = R1 x PE + R x PD + TA (7.) PE Power consumpion of PD Power consumpion of ligh receiving IC R11 -ambien emperaure hermal resisance parameer (R11 = θ1 (θ + θ3)) R1, R1 -ligh receiving IC hermal resisance parameer (R1, R1 = (θ1 x θ3)/(θ1 + θ + θ3)) R Ligh receiving IC-ambien emperaure hermal resisance parameer (R = θ3 (θ1 + θ)) Table 7-1. Thermal Resisance Parameer Thermal Resisance Parameer ( C/W) R11 R1, R1 R PS955 TYP PS935 TYP Summary This applicaion noe describes he feaures and applicaions of he PS955/PS935 phoocoupler, which is an IGBT-driving phoocoupler wih buil-in IGBT proecion circuis. Please use his documen when designing your sysem. The PS955/PS935 aims o faciliae he design of inverer equipmen a marke ha is expeced o grow significanly in he fuure and conribue o reducing sysem scale. In addiion o aggressively markeing he PS955/ PS935, Renesas Elecronics also plans o coninue developing phoocouplers ha suppor high-emperaure operaion and high-oupu devices. The following is an example of PS955, calculaing he juncion emperaure using (7.1) and (7.), wih PE = 7mW, PO ( =PD) = 1 mw, and TA = 85 C: TJE TJD = R11 x PE + R1 x PD + TA = C/W x 7 mw + 13 C/W x 1 mw + 85 C = 18.5 C = R1 x PE + R x PD +TA = 13 C/W x 7 mw + 18 C/W x 1 mw + 85 C = 111. C Informaion and daa presened here is subjec o change wihou noice. California Easern Laboraories assumes no responsibiliy for he use of any circuis described herein and makes no represenaions or warranies, expressed or implied, ha such circuis are free from paen infringemen. California Easern Laboraories 1/1/11 59 Parick Henry Drive, Sana Clara, CA 955 Tel FAX

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