LD5761B 04/27/2015. High Voltage with Two-Level Frequency. Green-Mode PWM Controller. General Description. Features. Applications. Typical Application

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1 REV: 00 General Descripion High Volage wih Two-Level Frequency The is a Green Mode PWM IC which is buil-in wih brown-in/ou funcions in a SOP-7/SOP-8 package. The device could minimize he componen couns, circui space, and reduces he overall maerial cos of power applicaions. The wo-level frequency of operaion enables excellen performance and high efficiency a nominal line. While in low line, jus operae in high-level frequency o reduce B MAX. Wihou changing ransformer design, he energy loss is perfecly minimized. Wih complee proecions in i, like OLP (Over Load Proecion), OVP (Over Volage Proecion), fas OSCP (Oupu shor circui proecion) and brown-in/ou proecion, he proecs he circui from being damaged in abnormal condiions. Furhermore, he feaures frequency swapping and sof driving funcion o minimize he noise and enhance EMI. Typical Applicaion Green-Mode PWM Conroller Feaures High-Volage (650V) Sar-up Circui No-Load Power Consumpion<30mW@230Vac wih X-cap discharge Two-Level Frequency Operaion a H/L Line Buil- in Brown-in/ou Funcion on HV pin Buil- in X-Cap Discharge on HV pin Frequency Swapping for EMI Enhancemen Non-Audible-Noise Green Mode Conrol LEB (Leading-Edge Blanking) on CS Pin Inernal Slope Compensaion OVP (Over Volage Proecion) on OLP (Over Load Proecion) OTP (Over Temperaure Proecion) OSCP(Oupu Shor Circui Proecion) Sof Driving 300mA/-800mA Driving Capabiliy Applicaions Swiching AC/DC Adapor and Baery Charger Open Frame Swiching Power Supply LCD Monior/TV Power AC Inpu EMI Filer ~ ~ DC Oupu HV OTP * GND COMP CS 1

2 OTP COMP CS GND OTP COMP CS GND HV NC HV Pin Configuraion SOP-8 (TOP VIEW) SOP-7 (TOP VIEW) TOP MARK YYWWPP TOP MARK YYWWPP YY: WW: PP: Year code Week code Producion code Ordering Informaion Par number Package Top Mark Shipping GS SOP-8 GS 2500 /ape & reel GR SOP-7 GR 2500 /ape & reel The is RoHs complian/ Green Packaged. Proecion Mode Pin Descripions Par number _OVP OSCP OLP OTP Lach Auo Auo Lach PIN NAME FUNCTION 1 OTP Pulling his pin below 0.95V will force he conroller ener ino lach mode and i will no resume unil he AC power recycles. Connec a NTC beween his pin and ground o achieve OTP proecion funcion. Le his pin floa o disable he lach proecion. 2 COMP Volage feedback pin. Connec a phoo-coupler wih i o close he conrol loop and achieve he regulaion. 3 CS Curren sense pin, connec i o sense he MOSFET curren 4 GND Ground 5 Gae drive oupu o drive he exernal MOSFET 6 Supply volage pin 7 NC Unconneced Pin 8 HV Connec his pin o Line/ Neural of AC main volage hrough a resisor o provide he sar-up curren for he conroller. When volage increase o rip he poin of UVLO(on), his HV loop will be urned off o reduce he power loss on he sar-up circui. An inernal resisor divider of HV pin will modulae he maximum frequency by conrol circui. Afer AC disappear for few cycles, HV pin will sink curren o discharge X-cap. 2

3 Block Diagram HV 8 HV CC Vcc OVP Comparaor 6 UVLO 29V - OVP UVLO On/off PG - Vcc OK Vref OK Inernal Bias&Ref Proecion Lach UVLO OFF - 1.4V Discharge - Vcc Sof -Drive PDR 6 COMP 2 RFB Bias Green Mode& Max. OSC Conrol Vf 3R HV R - Discharge PWM Comparaor S R SET CLR Q Q Bias CS 3 LEB Σ COMP 4.7V Vref OSCP Slope Com. OCP Comparaor - - OLP Comparaor Delay Time Delay Time Ex. OTP S SET Q 100uA V/0.95 Proecion 1 OTP Comp PG ½ Couner R CLR Q HV RBH - Debounce & Delay Time OSC OVP Ex. OTP S SET Q Lach PDR R CLR Q RBL X-cap discharge Delay Time S SET Q Discharge RBH:RBL =125:1 PG R CLR Q - In. OTP 4 GND 3

4 Absolue Maximum Raings Supply Volage High-Volage Pin, HV COMP, OTP, CS Maximum Juncion Temperaure Sorage Temperaure Range Package Thermal Resisance (SOP-8/ SOP-7, JA) Power Dissipaion, C (SOP-8/ SOP-7) Lead emperaure (Soldering, 10sec) ESD Volage Proecion, Human Body Model (excep HV Pin) ESD Volage Proecion, Machine Model (excep HV Pin) ESD Volage Proecion, Human Body Model (HV Pin) ESD Volage Proecion, Machine Model (HV pin) Gae Oupu Curren -0.3V ~ 32V -0.3V ~ 650V -0.3V ~ 6V -0.3V ~ 0.3V 150 C -65 C ~ 150 C 160 C/W 250mW 260 C 2.5KV 250V 1KV 200V 300mA/800mA Cauion: Sress exceeding Maximum Raings may damage he device. Maximum Raings are sress raings only. Funcional operaion above he Recommended Operaing Condiions is no implied. Exended exposure o sress above Recommended Operaing Condiions may affec device reliabiliy. Recommended Operaing Condiions Iem Min. Max. Uni Operaing Juncion Temperaure C Supply pin Volage V HV Pin Series Resisor k HV pin Capacior -- 0 pf Comp Pin Capacior 1 10 nf CS Pin Capacior pf 4

5 Elecrical Characerisics (T A = 25 o C unless oherwise saed, V CC=15V) PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS High-Volage Supply (HV Pin) HV Pin Source Curren V CC <UVLO (ON), HV=500V I HV ma HV Pin Discharge Capabiliy HV=500V I HV_DIS ma HV Pin Leakage Curren V CC >UVLO (ON), HV=500V I HV_LEAK 35 A HV Pin Brown-In Level V HVBI V DC HV Pin Brown-Ou Level V HVBO V DC HV Pin Hyseresis V HVBI - V HVBO V HVB_HYS 13 V DC Brown-In De-bounce Time T D_HVBI 160 S Brown-Ou De-bounce Time T D_HVBO 67 ms Low Frequency Operaion Range High Frequency Operaion Range HV Pin Min. Operaion Volage X-Cap discharge Deecion Delay ime Supply Volage ( Pin) V LSW 265 V DC V HSW 195 V DC Vcc =15V V HV_Min 45 V V COMP =3V T D_XCAP 65 ms Sar-up Curren HV=500V I CC_ST A Operaing Curren (wih 1nF load on pin) V COMP =3V I CC_OP1 2 ma V COMP =0V I CC_OP ma OTP Lach mode I CC_OPLL 0.55 ma Lach mode I CC_OPL 0.65 ma UVLO (OFF) V CC_OFF V UVLO (ON) V CC_ON V PDR V CC_PDR UVLO OFF - 1.4V V 5

6 PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS HVBI Level V CC > V HVBI, see Fig.1 V CC_HVBI UVLO OFF OVP Level V CC_OVP V OVP De-bounce Time T D_OVP 120 S Oscillaor for Swiching Frequency Low Frequency V COMP=3.5V HV>265V F LSW KHz High Frequency V COMP=3.5V HV<195V F HSW KHz Green Mode Frequency V COMP= V ZDC F SW_GRN KHz Modulaion Frequency F SW_MOD 200 Hz F SW Temp. Sabiliy *-40 C ~105 C F SW_TS % F SW Volage Sabiliy * F SW_VS 0 1 % Maximum Duy D MAX % Volage Feedback (Comp Pin) Inpu Volage o Curren-Sense Aenuaion 4V * A V 1/4 V/V Comp Impedance V COMP =3V Z COMP k Open Loop Volage Comp pin open V COMP_OPEN V OLP Tripped Level V OLP V PWM Mode Threshold V COMP of Low Frequency Green Mode Threshold V COMP of Low Frequency PWM Mode Threshold V COMP of High Frequency Green Mode Threshold V COMP of High Frequency Zero Duy Threshold V COMP on Burs mode Frequency= 0.9*F LSW, see Fig.2 Frequency= 1.1*F LSW-GRN, see Fig.2 Frequency= 0.9*F HSW, see Fig.2 Frequency= 1.1*F HSW-GRN, see Fig.2 V P_LSW V V G_LSW V V P_HSW V V G_HSW V Zero Duy in, see Fig.2 V ZDC V Zero Duy ou, see Fig.2 V ZDCH V ZDC 0.13V V V 6

7 PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS Curren Sensing (CS Pin) Maximum limi Volage V CS_MAX V Leading Edge Blanking Time T LEB 300 ns Delay o Oupu T PD 90 ns Slope Compensaion Level *0%-85% Linearly V SLP_L V Slope Compensaion Posiion *0%-85% Linearly SLP 0 85 % Gae Drive Oupu ( Pin) Oupu Low Level V CC=15V, Io=20mA V OL 0-1 V Oupu High Level V CC=15V, Io=20mA V OH 9 - V CC V Rising Time Load Capaciance=1nF T r 50 ns Falling Time Load Capaciance=1nF T f - 20 ns Pin Clamping Volage Load Capaciance=1nF, V CC= 21V V O_CLAMP 12 V Source capabiliy *Load Capaciance=33nF I SOURCE 300 ma Sink capabiliy *Load Capaciance=33nF I SINK 800 ma OLP (Over Load Proecion) OLP Delay Time T D_OLP ms Sof Sar Sof Sar Duraion T SS 6 ms Inernal OTP OTP Tripped Level(T OTP) * T INOTP 140 C OTP Hyseresis * T INOTP_HYS T INOT-30 C OTP De-bounce Time * T D_INOTP 160 S Over Temperaure Proecion(OTP Pin) OTP Pin Source Curren I OTP A Turn-On Trip Level V OTP_ON V Turn-Off Trip Level V OTP_OFF V OTP pin de-bounce ime T D_OTP 300 s *: Guaraneed by design 7

8 UVLO (ON) V CC-HVBI UVLO (ON) V CC-HVBI UVLO (OFF) UVLO (OFF) HV Pin Brown-In Level HV Pin Brown-In Level AC AC V CC > V CC-HVBI AC recovery V CC < V CC-HVBI AC recovery Fig. 1 V CC-HVBI & AC recovery Frequency wih Swapping 104KHz 88KHz 69KHz 61KHz High Frequency Low Frequency 26KHz 20KHz V ZDC V ZDCH V G V P Vcomp Fig. 2 V COMP vs. Operaion Frequency 8

9 Typical Performance Characerisics 9

10 Typical Performance Characerisics 10

11 Applicaion Informaion Operaion Overview As long as he green power requiremen becomes a rend and he power saving is geing more and more imporan AC Inpu EMI Filer ~ ~ for he swiching power supplies and swiching adapors, he radiional PWM conrollers are no able o suppor such new requiremens. Furhermore, he cos and size limiaion force he PWM conrollers o be more powerful HV and wih more funcions o reduce he exernal par couns. OTP The is ideal for hese applicaions. Is deailed GND CS feaures are described as below. Inernal High-Volage Sar-up Circui and Under Volage Lockou (UVLO) The radiional circui provides he sar-up curren hrough a sar-up resisor o power up he PWM conroller. However, i consumes much significan power o mee he curren power saving requiremen. In mos cases, sar-up resisors carry larger resisance and spend more ime o sar-up. To achieve he opimized opology, as shown in Fig. 11, is implemened wih a high-volage sar-up circui for such requiremen. A sar-up, he high-volage curren source sinks curren of AC Line or Neural o provide sar-up curren and charge he capacior C1 conneced o. Fig. 11 As rips UVLO(off), HV pin will recharge capacior ill volage rises back o UVLO(on) again. Since hen, HV pin would no longer charge he capacior and insead, send a gae drive signal o draw supply curren for from he auxiliary winding of he ransformer. Tha minimizes he power loss on he sar-up circui successfully. An UVLO comparaor is embedded o deec he volage across he pin o ensure he supply volage enough o power on he and in addiion, o drive he power MOSFET. As shown in Fig. 12, a hyseresis is provided o preven shudown from he volage dip during sar-up. The urn-on and urn-off hreshold level are se a 16V and 7V, respecively. A he sar-up ransien, he HV curren will supply around 2.9mA o capacior unil his volage reaches he UVLO(on). By using such configuraion, he urn-on delay ime will be almos same no maer under low-line or high-line condiions. 11

12 Vcc Line Volage UVLO(on) UVLO(off) VHV(peak) HV Curren VHVBI VHVBO 2.9mA ~ 0mA (off) Vcc curren Operaing Curren (Supply from Auxiliary Winding) UVLO(on) UVLO(off) Sar-up Curren Brown in/ou Proecion Fig. 12 The feaures Burn-in/ou funcion on HV pin. As he buil-in comparaor deecs he half wave recify line volage condiion, i will shu off he conroller o preven from any damage. Fig. 13 shows he operaion. When VHV < H VBO, pin will remain off even when he already reaches UVLO(ON). I herefore forces he hiccup beween UVLO(ON) and UVLO(OFF). Unless he line volage rises over HVBI, pin will no sar swiching even as he nex UVLO(ON) is ripped. A hyseresis is implemened o preven he false-riggering during urn-on and urn-off. Non-Swiching Fig. 13 Swiching Non- Swiching Curren Sensing, Leading-Edge Blanking and he Negaive Spike on CS Pin The ypical curren mode PWM conroller feedbacks boh curren signal and volage signal o close he conrol loop and achieve regulaion. The deecs he primary MOSFET curren across CS pin o conrol in peak curren mode and also limi he pulse-by-pulse curren. The maximum volage hreshold of he curren sensing pin is se a 0.72V. Thus he MOSFET peak curren can be calculaed as: I PEAK(MAX) 0.72V R A 300nS leading-edge blanking (LEB) ime is designed in he inpu of CS pin o preven false-riggering from he curren spike. In he low power applicaions, if he oal pulse widh of he urn-on spikes is less han 300nS and he negaive spike on he CS pin does no exceed -0.3V, he R-C filer (as shown in Fig. 14) is free o eliminae. S 12

13 However, he oal pulse widh of he urn-on spike is relaed o he oupu power, circui design and PCB layou. I is srongly recommended o add a small R-C filer (as shown in Fig. 15) for larger power applicaion o avoid he CS pin from being damaged by he negaive urn-on spike. Oupu Sage and Maximum Duy-Cycle An oupu sage of a CMOS buffer wih ypical 300mA driving capabiliy is incorporaed o drive a power MOSFET direcly. And he maximum duy-cycle of is limied o 85% o avoid he ransformer sauraion. CS GND 300ns blanking ime Can be removed if he negaive spike is no over spec. (-0.3V). Fig. 14 Volage Feedback Loop The volage feedback signal is provided from he TL431 on he secondary side hrough he phoo-coupler o he COMP pin of. Similar o UC384X, is inpu sage is wih a diode volage offse o feed he volage divider wih 1/4 raio, ha is, 1 VCS (VCOMP VF ) 4 A pull-high resisor is embedded inernally o opimize he exernal circui. CS GND R-C filer is required when he negaive spike exceeds -0.3V or he oal spike widh is over 300nS LEB period. Fig

14 Inernal Slope Compensaion On/Off Conrol A fundamenal issue of curren mode conrol is he sabiliy problem when is duy-cycle is operaed for more han 50%. To sabilize he conrol loop, he slope compensaion is required in he radiional UC384X design by injecing he ramp signal from he RT/CT pin hrough a coupling capacior. has inernal slope compensaion circui o simplify he exernal circui design. Oscillaor and Swiching Frequency The has wo levels of operaion frequency, 61~69 khz for high line and 88~104 khz for low line. Wih his design, i can solve B MAX issue and achieves beer efficiency easily. Dual-Oscillaor Green-Mode Operaion There are many differen opologies has been implemened in differen chips for he green-mode or power saving requiremens such as burs-mode conrol, skipping-cycle mode, variable off-ime conrol ec. The basic operaion heory of all hese approaches inended o reduce he swiching cycles under ligh-load or no-load condiion eiher by skipping some swiching pulses or reduce he swiching frequency. By using LD proprieary dual-oscillaor echnique, he green-mode frequency can be well conrolled and furher o avoid he generaion of audible noise. Frequency Swapping The is buil in a fixed modulaing frequency for rembling funcion which provides he power supply designers o choose he opimized EMI performance and lowes sysem cos. This Frequency Swapping funcion is Leadrend s paened echnology. CN , TWI377770, US , US Pulling COMP pin below V ZDC will immediaely disable he gae oupu of. Remove he pull-low signal o rese i. Over Load Proecion (OLP)- Auo Recovery Mode To proec he circui from being damaged a over-load condiion and shor or open loop condiion, he is implemened wih smar OLP funcion. feaures auo recovery mode funcion of i, see Fig. 16 for he waveform. In he example of faul condiion, he feedback sysem will force he volage loop ener oward he sauraion and hen pull he volage high on COMP pin (V COMP). When he V COMP ramps up o he OLP ripped level (4.7V) and says for more han he OLP delay ime, he proecion will be acivaed and hen urn off he gae oupu o sop he swiching of power circui. The OLP delay ime is se by inernal high frequency couner. I is o preven he false riggering from he urn-on and urn-off ransien. A divide-2 couner is implemened o reduce he average power under OLP behavior. As soon as OLP is acivaed, he oupu will be lached off and he divide-2 couner will sar o coun he number of UVLO(off). The lach will no be released unil he 2nd UVLO(off) poin is couned, afer ha he oupu will resume o swich again. Wih he proecion mechanism, he average inpu power will be minimized, so ha he componen emperaure and sress can be conrolled wihin he safe operaing area. 14

15 UVLO(on) UVLO(off) OVP Level OVP Tripped Comp OLP Level OLP delay ime Swiching UVLO(on) UVLO(off) PDR Lach Released Swiching Non- Swiching Swiching Swiching AC inpu Volage Non - Swiching Swiching AC inpu Volage AC Off AC On ( Recycle) Fig. 16 Fig. 17 OVP (Over Volage Proecion) on Lach Mode The V GS raings of he nowadays power MOSFETs are mosly wih 30.5V maximum. To proec he V GS from he faul condiion, is implemened wih OVP funcion on. As he volage is larger han he OVP hreshold volage, i will shu off he oupu gae drive circui simulaneously and sop swiching he power MOSFET. The OVP is lach-off ype of proecion. Once he rips OVP level (which is usually caused by he feedback loop opened), i will be lached off. Turn off AC power o le fall below PDR level o release overvolage proecion. And hen resar he power o resume he operaion. The de-lach level is defined by inernal PDR. See Fig. 17 for is operaion. On-Chip OTP - Auo Recovery An inernal OTP circui is embedded inside he o provide he wors-case proecion for his conroller. When he chip emperaure rises higher han he rip OTP level, he oupu will be disabled unil he chip is cooled down below he hyseresis window. Exernal OTP - Lach Mode The OTP circui is implemened o sense wheher here is any ho-spo of power circui like power MOSFET or oupu recifier. Typically, a NTC is recommended o connec wih OTP pin. The NTC resisance will decrease as he device or ambien in high emperaure. The relaionship is described as below. VOTP 100μA R NTC When V OTP < V OTP-OFF (ypical 0.95V), i will rigger he proecion o shu down he gae oupu and lach off he power supply. The conroller will remain lached unless he 15

16 drops below 7V (power down rese) and says on UVLO condiion. Two condiions are required o resar he IC successfully, cool down he circui so ha he NTC resisance increase and raise V OTP above 1.05V. Then, recycle he AC main power. The deailed operaion is show in Fig. 18. hrough he gae-o-drain capacior C GD. Therefore, he MOSFET should be always pulled low and placed in he off-sae as he gae resisor is disconneced or opened in any case. V BULK VOTP OTP Release 1.05V 0.95V OTP Tripped dv i Cgd bulk d C GD UVLO(on) UVLO(off) PDR Lach Released Rg R8 AC inpu Volage AC Off AC On (Recycle) CS GND Swiching Non-Swiching Swiching Fig. 18 Pull-Low Resisor on he Gae Pin of MOSFET The consiss of an ani-floaing resisor a pin o proec he oupu from damage in abnormally operaion or condiion due o false riggering of MOSFET. Even so, we sill recommend o add an exernal one a he MOSFET gae erminal o provide more proecion in case of disconnecion of gae resisor R G during power-on. In such single-faul condiion, as shown in Fig. 19, he resisor R8 can provide a discharge pah o avoid he MOSFET from being false-riggered by he curren This resisor would proec he MOSFET from being false riggered by he curren hrough C GD, if R G is disconneced. Fig. 19 Proecion Resisor on he Hi-V Pah In some oher Hi-V process and design, here may be a parasiic SCR caused around HV pin, and GND. As shown in Fig. 20, a small negaive spike on he HV pin may rigger his parasiic SCR and cause lach-up beween and GND. I may damage he chip because of he equivalen shor-circui induced by such lach-up behavior. Leadrend s proprieary of Hi-V echnology will eliminae parasiic SCR in. Fig. 21 shows he equivalen Hi-V srucure circui of. So ha is more capable o susain negaive volage han similar producs. However, a 10K resisor is recommended o 16

17 be placed in he Hi-V pah o play as a curren limi resisor whenever a negaive volage is applied. Negaive-riggered Parasiic SCR. Small negaive spike on HV pin will cause he lachup beween Vcc and GND. 0V HV Curren limi resisor for Prevening damage from Negaive volage (recommended) 0V HV Parasiic effec beween HV, Vcc and GND Oher HV process wih parasiic SCR GND Fig. 21 GND Fig.20 17

18 Package Informaion SOP-7 Symbols Dimensions in Millimeers Dimensions in Inch MIN MAX MIN MAX A B C D F H I J M θ

19 Package Informaion SOP-8 Symbols Dimensions in Millimeers Dimensions in Inch MIN MAX MIN MAX A B C D F H I J M θ Imporan Noice Leadrend Technology Corp. reserves he righ o make changes or correcions o is producs a any ime wihou noice. Cusomers should verify he daashees are curren and complee before placing order. 19

20 Revision Hisory Rev. Dae Change Noice 00 4/27/2015 Original Specificaion. 20

LD5760A 12/15/2016. High Voltage Green-Mode PWM Controller with BNO Function. Features. General Description. Applications. Typical Application REV.

LD5760A 12/15/2016. High Voltage Green-Mode PWM Controller with BNO Function. Features. General Description. Applications. Typical Application REV. High Volage Green-Mode PWM Conroller wih BNO Funcion REV. 06 General Descripion The is a Green Mode PWM IC buil-in wih brown-in/ ou funcions in a SOP-7 or SOP-8 package. I minimizes he componen couns,