CoolSET -F3 ICE3A1065ELJ. Off-Line SMPS Current Mode Controller with integrated 650V CoolMOS and Startup Cell (Latched and frequency jitter Mode)

Transcription

1 Version 2.3, 19 Nov 2012 CoolSET -F3 Off-Line SMPS Curren Conroller wih inegraed 650V CoolMOS and Sarup Cell (Lached and frequency jier ) Power Managemen & Supply Never sop hinking.

2 Revision Hisory: Daashee Previous Version: V2.2 Page Subjecs (major changes since las revision) 25 revised ouline dimension for PG-DIP-8 package For quesions on echnology, delivery and prices please conac he Infineon Technologies Offices in Germany or he Infineon Technologies Companies and Represenaives worldwide: see our webpage a hp:// CoolMOS, CoolSET are rademarks of Infineon Technologies AG. Ediion Published by Infineon Technologies AG, Munich, Germany, 2008 Infineon Technologies AG. All Righs Reserved. Legal disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac your neares Infineon Technologies Office ( Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac your neares Infineon Technologies Office. Infineon Technologies Componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.

3 Off-Line SMPS Curren Conroller wih inegraed 650V CoolMOS and Sarup Cell (Lached and frequency jier ) Produc Highlighs Acive Burs o reach he lowes Sandby Power Requiremens < 100mW Buil-in lached off mode and exernal lach enable funcion o increase robusness of he sysem Buil-in and exendable blanking window for high load jumps o increase sysem reliabiliy Buil-in sof sar Frequency jier for low EMI Robusness o sysem noise Pb-free lead plaing; RoHS complian Feaures 650V avalanche rugged CoolMOS wih buil-in Sarup Cell Acive Burs for lowes Sandby Power Fas load jump response in Acive Burs 100kHz inernally fixed swiching frequency Buil-in lached Off for Overemperaure, Overvolage & Shor Winding Deecion Auo Resar for Overload, Open Loop & VCC Undervolage Buil-in Sof Sar Buil-in and exendable blanking Window for shor duraion high curren Exernal lach enable funcion Max Duy Cycle 75% Overall olerance of Curren Limiing < ±5% Inernal PWM Leading Edge Blanking BiCMOS echnology provide wide VCC range Frequency jier and sof driving for low EMI Robusness o sysem noise such as ESD, lighning surge, ec. CoolSET -F3 es PG-DIP-8 Descripion The CoolSET F3 ELJ version is he enhanced LJ version for sysem noise. I reains all he feaures of LJ series such as BiCMOS echnologies, acive burs mode, frequency jier, propagaion delay compensaion, buil-in sof sar, auo-resar proecion for over load and open loop, lach off proecion for over volage, over emperaure and shor winding, exernal lach off enable, buil-in and exendable blanking ime for shor period of over power, ec. I is arge for low power SMPS applicaion such as Off-Line Baery Adapers, DVD player and recorder, se-op box, auxiliary power supply, ec. The ELJ version has implemened some noise resis echniques o he IC such ha i is more robus o he sysem noise which is generaed during sysem ESD es, lighning surge es, ransien es, ec. Typical Applicaion VAC CBulk Snubber + Converer DC Oupu - VCC CVCC Drain Power Managemen Sarup Cell GND PWM Conroller Curren Precise Low Tolerance Peak Curren Limiaion Conrol Uni Acive Burs Lached Off Auo Resar CS Depl. CoolMOS CoolSET -F3 ( Lach & Jier ) FB BL RSense Type Package Marking V DS F OSC 1) R DSon 230VAC ±15% 2) VAC 2) PG-DIP-8 3A1065ELJ 650V 100kHz W 16W 1) 2) T=25 C Calculaed maximum inpu power raing a T a =75 C, T j =125 C and wihou copper area as hea sink. Version Nov 2012

4 Table of Conens Page 1 Pin Configuraion and Funcionaliy Pin Configuraion wih PG-DIP Pin Funcionaliy Represenaive Blockdiagram Funcional Descripion Inroducion Power Managemen Improved Curren PWM-OP PWM-Comparaor Sarup Phase PWM Secion Oscillaor PWM-Lach FF Gae Driver Curren Limiing Leading Edge Blanking Propagaion Delay Compensaion Conrol Uni Basic and Exendable Blanking Acive Burs Enering Acive Burs Working in Acive Burs Leaving Acive Burs Proecion s Lached Off Auo Resar Elecrical Characerisics Absolue Maximum Raings Operaing Range Characerisics Supply Secion Inernal Volage Reference PWM Secion Sof Sar ime Conrol Uni Curren Limiing CoolMOS Secion Temperaure deraing curve Version Nov 2012

5 6 Ouline Dimension Marking Schemaic for recommended PCB layou Version Nov 2012

6 1 Pin Configuraion and Funcionaliy 1.1 Pin Configuraion wih PG-DIP-8 Pin Symbol Funcion 1 BL Blanking and Lach 2 FB Feedback 3 CS Curren Sense/ 650V 1) CoolMOS Source 4 Drain 650V 1) CoolMOS Drain 5 Drain 650V 1) CoolMOS Drain 6 n.c. No Conneced 7 VCC Conroller Supply Volage 8 GND Conroller Ground CoolSET -F3 Pin Configuraion and Funcionaliy 1.2 Pin Funcionaliy BL (Blanking and Lach) The BL pin combines he funcions of exendable blanking ime for enering he Auo Resar and he exernal lach enable. The exendable blanking ime funcion is o exend he buil-in 20ms blanking ime by adding an exernal capacior a BL o ground. The exernal lach enable funcion is an exernal access o lach off he IC. I is riggered by pulling down he BL pin o less han 0.1V. FB (Feedback) The informaion abou he regulaion is provided by he FB Pin o he inernal Proecion Uni and o he inernal PWM-Comparaor o conrol he duy cycle. The FB- Signal conrols in case of ligh load he Acive Burs of he conroller. 1) a T j = 110 C Package PG-DIP-8 CS (Curren Sense) The Curren Sense pin senses he volage developed on he series resisor insered in he source of he inegraed CoolMOS. If CS reaches he inernal hreshold of he Curren Limi Comparaor, he Driver oupu is immediaely swiched off. Furhermore he curren informaion is provided for he PWM- Comparaor o realize he Curren. BL 1 8 GND Drain (Drain of inegraed CoolMOS ) Pin Drain is he connecion o he Drain of he inernal CoolMOS. FB CS Drain VCC n.c. Drain VCC (Power supply) The VCC pin is he posiive supply of he IC. The operaing range is beween 10.5V and 26V. GND (Ground) The GND pin is he ground of he conroller. Figure 1 Pin Configuraion PG-DIP-8(op view) Noe: Pin 4 and 5 are shored wihin he DIP 8 package. Version Nov 2012

7 Represenaive Blockdiagram 2 Represenaive Blockdiagram Lach Enable Signal VAC BL #2 #1 CBK TLE FB CBulk 5.0V Power Managemen 3.25kΩ Inernal Bias Volage 5.0V Reference IBK Lached Off T2 Rese T3 0.6V VVCC < 6.23V Undervolage Lockou Power-Down T1 18V Rese 10.5V 0.9V S1 5.0V RFB 25kΩ VCC C1 & Spike 1 Blanking G3 24V Lached Off G1 8.0us 1 ms couner Thermal Shudown Sof Sar Tj >140 C 0.1V Block C2 8us Blanking Time 4.0V 4.5V C3 C4 G2 20ms Blanking Time & G5 Spike Blanking 8.0us Auo Resar Sof Sar Sof-Sar Comparaor C7 & G7 PWM Comparaor C8 Acive Burs C5 20ms Blanking & 0.6V 1.35V Time 2pF G6 x3.2 C6a PWM OP 3.61V & C6b G11 Curren 3.0V Conrol Uni ICE3Axx65ELJ / CoolSET -F3 ( Lach & Jier ) # : opional exernal componens; #1 : CBK is used o exand he Blanking Time #2 : TLE is used o enable he exernal Lach funcion Snubber CVCC VCC Drain CoolMOS Sarup Cell 0.72 PWM Oscillaor Secion Duy Cycle max Clock Freq. jier G8 Gae FF1 Driver S R Q & G9 Spike 1.66V Blanking C11 190ns Propagaion-Delay Compensaion Vcsh Leading 10kΩ C10 Edge Blanking 1pF D1 220ns & G10 C V Curren Limiing GND CS RSense + Conv DC O VO Figure 2 Represenaive Blockdiagram Version Nov 2012

8 Funcional Descripion 3 Funcional Descripion All values which are used in he funcional descripion are ypical values. For calculaing he wors cases he min/max values which can be found in secion 4 Elecrical Characerisics have o be considered. 3.1 Inroducion CoolSET -F3 ELJ series is he enhanced version of he LJ series. No only reains all he feaures of LJ series bu i also implemens wih special echnique o make he IC more robus o he sysem noise which is generaed during ransien es, sysem ESD es, lighning surge es, ec. In order o obain he bes-in class low sandby power, a new fully inegraed Sandby Power concep is implemened ino he IC. An inelligen Acive Burs is used for his Sandby. Afer enering his mode here is sill a full conrol of he power conversion by he secondary side via he same opocoupler ha is used for he normal PWM conrol. The response on load jumps is opimized. The volage ripple on V ou is minimized. V ou is on well conrolled in his mode. The usually exernal conneced RC-filer in he feedback line afer he opocoupler is inegraed in he IC o reduce he exernal par coun. Furhermore a high volage Sarup Cell is inegraed ino he IC which is swiched off once he Undervolage Lockou on-hreshold of 18V is exceeded. This Sarup Cell is par of he inegraed CoolMOS. The exernal sarup resisor is no longer necessary as his Sarup Cell is conneced o he Drain. Power losses are herefore reduced. This increases he efficiency under ligh load condiions drasically. This version is adoping he BiCMOS echnology and i can increase design flexibiliy as he Vcc volage range is increased o 26V. For his ELJ version, he sof sar is a buil-in funcion. I is se a 20ms. Then i can save exernal componen couns. There are 2 modes of blanking ime for high load jumps; he basic mode and he exendable mode. The blanking ime for he basic mode is se a 20ms while he exendable mode will increase he blanking ime from basic mode by adding exernal capacior a he BL pin. During his ime window he overload deecion is disabled. In order o increase he robusness and safey of he sysem, he IC provides 2 levels of proecion modes: Lached Off and Auo Resar. The Lached Off is only enered under dangerous condiions which can damage he SMPS if no swiched off immediaely. A resar of he sysem can only be done by recycling he AC line. In addiion, for his ELJ version, here is an exernal Lach Enable funcion provided o increase he flexibiliy in proecion. When he BL pin is pulled down o less han 0.1V, he Lach Off is riggered. The Auo Resar reduces he average power conversion o a minimum under unsafe operaing condiions. This is necessary for a prolonged faul condiion which could oherwise lead o a desrucion of he SMPS over ime. Once he malfuncion is removed, normal operaion is auomaically reained afer he nex Sar Up Phase. The inernal precise peak curren limiaion reduces he coss for he ransformer and he secondary diode. The influence of he change in he inpu volage on he power limiaion can be avoided ogeher wih he inegraed Propagaion Delay Compensaion. Therefore he maximum power is nearly independen on he inpu volage which is required for wide range SMPS. There is no need for an exra over-sizing of he SMPS, e.g. he ransformer or he secondary diode. Furhermore, his ELJ version implemens he frequency jier mode o he swiching clock such ha he EMI noise will be effecively reduced. 3.2 Power Managemen Drain Power Managemen Inernal Bias Lached Off Rese V VCC < 6.23V Power-Down Rese Sof Sar block Sarup Cell Undervolage Lockou 18V 10.5V Volage Reference Auo Resar Acive Burs Lached Off CoolMOS VCC 5.0V Figure 3 Power Managemen The Undervolage Lockou moniors he exernal supply volage V VCC. When he SMPS is plugged o he main line he inernal Sarup Cell is biased and sars o charge he exernal capacior C VCC which is Version Nov 2012

9 Funcional Descripion conneced o he VCC pin. This VCC charge curren is conrolled o 0.9mA by he Sarup Cell. When he V VCC exceeds he on-hreshold V CCon =18V, he bias circui are swiched on. Then he Sarup Cell is swiched off by he Undervolage Lockou and herefore no power losses presen due o he connecion of he Sarup Cell o he Drain volage. To avoid unconrolled ringing a swich-on a hyseresis sar up volage is implemened. The swich-off of he conroller can only ake place afer Acive was enered and V VCC falls below 10.5V. The maximum curren consumpion before he conroller is acivaed is abou 250μA. When V VCC falls below he off-hreshold V CCoff =10.5V, he bias circui swiched off and he sof sar couner is rese. Thus i is ensured ha a every sarup cycle he sof sar sars a zero. The inernal bias circui is swiched off if Lached Off or Auo Resar is enered. The curren consumpion is hen reduced o 250μA. Once he malfuncion condiion is removed, his block will hen urn back on. The recovery from Auo Resar does no require re-cycling he AC line. In case Lached Off is enered, VCC needs o be lowered below 6.23V o rese he Lached Off. This is done usually by re-cycling he AC line. When Acive Burs is enered, he inernal Bias is swiched off mos of he ime bu he Volage Reference is kep alive in order o reduce he curren consumpion below 450μA. 3.3 Improved Curren FB Figure 4 Sof-Sar Comparaor 0.6V C8 PWM OP x3.2 Improved Curren Curren PWM-Lach R S CS Q Q Driver Curren means he duy cycle is conrolled by he slope of he primary curren. This is done by comparing he FB signal wih he amplified curren sense signal. Amplified Curren Signal FB 0.6V Driver T on Figure 5 Pulse Widh Modulaion In case he amplified curren sense signal exceeds he FB signal he on-ime T on of he driver is finished by reseing he PWM-Lach (see Figure 5). The primary curren is sensed by he exernal series resisor R Sense insered in he source of he inegraed CoolMOS. By means of Curren regulaion, he secondary oupu volage is insensiive o he line variaions. The curren waveform slope will change wih he line variaion, which conrols he duy cycle. The exernal R Sense allows an individual adjusmen of he maximum source curren of he inegraed CoolMOS. To improve he Curren during ligh load condiions he amplified curren ramp of he PWM-OP is superimposed on a volage ramp, which is buil by he swich T2, he volage source V1 and a resisor R1 (see Figure 6). Every ime he oscillaor shus down for maximum duy cycle limiaion he swich T2 is closed by V OSC. When he oscillaor riggers he Gae Driver, T2 is opened so ha he volage ramp can sar. In case of ligh load he amplified curren ramp is oo small o ensure a sable regulaion. In ha case he Volage Ramp is a well defined signal for he comparison wih he FB-signal. The duy cycle is hen conrolled by he slope of he Volage Ramp. By means of he ime delay circui which is riggered by he invered V OSC signal, he Gae Driver is swiched-off unil i reaches approximaely 156ns delay ime (see Figure 7). I allows he duy cycle o be reduced coninuously ill 0% by decreasing V FB below ha hreshold. Version Nov 2012

10 Funcional Descripion FB Sof-Sar Comparaor Oscillaor V OSC T 2 R 1 C 1 PWM Comparaor C8 ime delay circui (156ns) 0.6V 10kΩ V 1 PWM-Lach Gae Driver X3.2 PWM OP PWM-OP The inpu of he PWM-OP is applied over he inernal leading edge blanking o he exernal sense resisor R Sense conneced o pin CS. R Sense convers he source curren ino a sense volage. The sense volage is amplified wih a gain of 3.2 by PWM OP. The oupu of he PWM-OP is conneced o he volage source V 1. The volage ramp wih he superimposed amplified curren signal is fed ino he posiive inpus of he PWM- Comparaor C8 and he Sof-Sar-Comparaor (see Figure 6) PWM-Comparaor The PWM-Comparaor compares he sensed curren signal of he inegraed CoolMOS wih he feedback signal V FB (see Figure 8). V FB is creaed by an exernal opocoupler or exernal ransisor in combinaion wih he inernal pull-up resisor R FB and provides he load informaion of he feedback circuiry. When he amplified curren signal of he inegraed CoolMOS exceeds he signal V FB he PWM-Comparaor swiches off he Gae Driver. Figure 6 Volage Ramp Improved Curren R FB 5V Sof-Sar Comparaor V OSC max. Duy Cycle FB C8 PWM-Lach PWM Comparaor Volage Ramp 0.6V FB Opocoupler 0.6V PWM OP X3.2 CS Gae Driver Improved Curren 156ns ime delay Figure 8 PWM Conrolling Figure 7 Ligh Load Condiions Version Nov 2012

11 Funcional Descripion 3.4 Sarup Phase Sof Sar couner Sof Sar finish SofS C7 Sof Sar Sof Sar Sof-Sar Comparaor & Gae Driver V SofS V SofS2 V SofS1 G7 Figure 10 Sof Sar Phase 0.6V PWM OP x3.2 CS SofS 5V R SofS Figure 9 Sof Sar In he Sarup Phase, he IC provides a Sof Sar period o conrol he maximum primary curren by means of a duy cycle limiaion. The Sof Sar funcion is a buil-in funcion and i is conrolled by an inernal couner. When he V VCC exceeds he on-hreshold volage, he IC sars he Sof Sar mode. The funcion is realized by an inernal Sof Sar resisor, a curren sink and a couner. And he ampliude of he curren sink is conrolled by he couner. Sof Sar Couner 32I 8I Figure 11 Sof Sar Circui Afer he IC is swiched on, he V SofS volage is conrolled such ha he volage is increased sepwisely (32 seps) wih he increase of he couns. The Sof Sar couner would send a signal o he curren sink conrol in every 600us such ha he curren sink decrease gradually and he duy raio of he gae drive increase gradually. The Sof Sar will be finished in 20ms afer he IC is swiched on. A he end of he Sof Sar period, he curren sink is swiched off. 4I 2I I Version Nov 2012

12 Funcional Descripion VSOFTS32 V SofS Sof-Sar The Sar-Up ime Sar-Up before he converer oupu volage V OUT is seled, mus be shorer han he Sof- Sar Phase Sof-Sar (see Figure 13). By means of Sof-Sar here is an effecive minimizaion of curren and volage sresses on he inegraed CoolMOS, he clamp circui and he oupu overshoo and i helps o preven sauraion of he ransformer during Sar-Up. 3.5 PWM Secion Gae Driver Oscillaor 0.75 PWM Secion Duy Cycle max Figure 12 Gae drive signal under Sof-Sar Phase Clock Frequency Jier Wihin he sof sar period, he duy cycle is increasing from zero o maximum gradually (see Figure 12). In addiion o Sar-Up, Sof-Sar is also acivaed a each resar aemp during Auo Resar. V SOFTS32 V SofS Sof-Sar Sof Sar Block Sof Sar Comparaor PWM Comparaor Curren Limiing 1 G8 FF1 S R Q Gae Driver & G9 CoolMOS Gae 4.0V V FB V OUT V OUT Sar-Up Figure 13 Sar Up Phase Figure 14 PWM Secion Block Oscillaor The oscillaor generaes a fixed frequency of 100KHz wih frequency jiering of ±4% (which is ±4KHz) a a jiering period of 4ms. A capacior, a curren source and a curren sink which deermine he frequency are inegraed. The charging and discharging curren of he implemened oscillaor capacior are inernally rimmed, in order o achieve a very accurae swiching frequency. The raio of conrolled charge o discharge curren is adjused o reach a maximum duy cycle limiaion of D max =0.75. Once he Sof Sar period is over and when he IC goes ino normal operaing mode, he swiching frequency of he clock is varied by he conrol signal from he Sof Sar block. Then he swiching frequency is varied in range of 100KHz ± 4KHz a period of 4ms. Version Nov 2012

13 Funcional Descripion PWM-Lach FF1 The oupu of he oscillaor block provides coninuous pulse o he PWM-Lach which urns on/off he inernal CoolMOS Afer he PWM-Lach is se, i is rese by he PWM comparaor, he Sof Sar comparaor or he Curren -Limi comparaor. When i is in rese mode, he oupu of he driver is shu down immediaely Gae Driver VCC PWM-Lach 1 Gae Driver Gae CoolMOS Figure 15 Gae Driver The driver-sage is opimized o minimize EMI and o provide high circui efficiency. This is done by reducing he swich on slope when exceeding he inernal CoolMOS hreshold. This is achieved by a slope conrol of he rising edge a he driver s oupu (see Figure 16). (inernal) V Gae 5V ca. = 130ns Figure 16 Gae Rising Slope Thus he leading swich on spike is minimized. Furhermore he driver circui is designed o eliminae cross conducion of he oupu sage. During power up, when VCC is below he undervolage lockou hreshold V VCCoff, he oupu of he Gae Driver is se o low in order o disable power ransfer o he secondary side. 3.6 Curren Limiing PWM Lach FF1 PWM-OP & G10 Acive Burs Lached Off Spike Blanking 190ns Propagaion-Delay Compensaion C10 C12 CS Curren Limiing C11 V csh 0.31V 10k D1 Leading Edge Blanking 220ns 1pF 1.66V Figure 17 Curren Limiing Block There is a cycle by cycle peak curren limiing operaion realized by he Curren-Limi comparaor C10. The source curren of he inegraed CoolMOS is sensed via an exernal sense resisor R Sense. By means of R Sense he source curren is ransformed o a sense volage V Sense which is fed ino he pin CS. If he volage V Sense exceeds he inernal hreshold volage V csh, he comparaor C10 immediaely urns off he gae drive by reseing he PWM Lach FF1. A Propagaion Delay Compensaion is added o suppor he immediae shu down of he inegraed CoolMOS wih very shor propagaion delay. Thus he influence of he AC inpu volage on he maximum oupu power can be reduced o minimal. In order o preven he curren limi from disorions caused by leading edge spikes, a Leading Edge Blanking is inegraed in he curren sense pah for he comparaors C10, C12 and he PWM-OP. The oupu of comparaor C12 is acivaed by he Gae G10 if Acive Burs is enered. When i is acivaed, he curren limiing is reduced o 0.31V. This Version Nov 2012

14 Funcional Descripion volage level deermines he maximum power level in Acive Burs. Furhermore, he comparaor C11 is implemened o deec dangerous curren levels which could occur if here is a shor winding in he ransformer or he secondary diode is shoren. To ensure ha here is no accidenally enering of he Lached by he comparaor C11, a 190ns spike blanking ime is inegraed in he oupu pah of comparaor C Leading Edge Blanking V csh V Sense LEB = 220ns The overshoo of Signal2 is larger han of Signal1 due o he seeper rising waveform. This change in he slope is depending on he AC inpu volage. Propagaion Delay Compensaion is inegraed o reduce he overshoo due o di/d of he rising primary curren. Thus he propagaion delay ime beween exceeding he curren sense hreshold V csh and he swiching off of he inegraed inernal CoolMOS is compensaed over emperaure wihin a wide range. Curren Limiing is hen very accurae. For example, I peak = 0.5A wih R Sense = 2. The curren sense hreshold is se o a saic volage level V csh =1V wihou Propagaion Delay Compensaion. A curren ramp of di/d = 0.4A/µs, or dv Sense /d = 0.8V/µs, and a propagaion delay ime of Propagaion Delay =180ns leads o an I peak overshoo of 14.4%. Wih he propagaion delay compensaion, he overshoo is only around 2% (see Figure 20). wih compensaion wihou compensaion Figure 18 Leading Edge Blanking Whenever he inernal CoolMOS is swiched on, a leading edge spike is generaed due o he primaryside capaciances and reverse recovery ime of he secondary-side recifier. This spike can cause he gae drive o swich off uninenionally. In order o avoid a premaure erminaion of he swiching pulse, his spike is blanked ou wih a ime consan of LEB = 220ns Propagaion Delay Compensaion In case of overcurren deecion, here is always propagaion delay o swich off he inernal CoolMOS. An overshoo of he peak curren I peak is induced o he delay, which depends on he raio of di/d of he peak curren (see Figure 19). I peak2 I Sense Signal2 I Overshoo2 Signal1 Propagaion Delay V Sense V 1,3 1,25 1,2 1,15 1,1 1,05 1 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 dv Sense d Figure 20 Overcurren Shudown The Propagaion Delay Compensaion is realized by means of a dynamic hreshold volage V csh (see Figure 21). In case of a seeper slope he swich off of he driver is earlier o compensae he delay. V OSC max. Duy Cycle off ime V μs I peak1 I Limi V Sense Propagaion Delay I Overshoo1 V csh Figure 19 Curren Limiing Signal1 Signal2 Figure 21 Dynamic Volage Threshold V csh Version Nov 2012

15 Funcional Descripion 3.7 Conrol Uni The Conrol Uni conains he funcions for Acive Burs, Auo Resar and Lached Off. The Acive Burs and he Auo Resar boh have 20ms inernal Blanking Time. For he Auo Resar, a furher exendable Blanking Time is achieved by adding exernal capacior a BL pin. By means of his Blanking Time, he IC avoids enering ino hese wo modes accidenally. Furhermore hose buffer ime for he overload deecion is very useful for he applicaion ha works in low curren bu requires a shor duraion of high curren occasionally Basic and Exendable Blanking BL # C BK I BK S1 0.9V 1 G2 5.0V Sof Sar block he 8.0us spike blanking ime, he Auo Resar is acivaed. For example, if C BK = 0.22uF, I BK = 8.4uA Blanking ime = 20ms + C BK x ( ) / I BK = 100ms The 20ms blanking ime circui afer C4 is disabled by he sof sa block such ha he conroller can sar up properly. The Acive Burs has basic blanking mode only while he Auo Resar has boh he basic and he exendable blanking mode Acive Burs The IC eners Acive Burs under low load condiions. Wih he Acive Burs, he efficiency increases significanly a ligh load condiions while sill mainaining a low ripple on V OUT and a fas response on load jumps. During Acive Burs, he IC is conrolled by he FB signal. Since he IC is always acive, i can be a very fas response o he quick change a he FB signal. The Sar up Cell is kep OFF in order o minimize he power loss. Inernal Bias 4.0V C3 & Spike Blanking 8.0us 20 ms Blanking Time Curren Limiing & G10 4.5V C4 20ms Blanking Time G5 Auo Resar 4.5V C4 FB 1.35V C5 20ms Blanking Time & G6 Acive Burs FB 1.35V C5 & G6 Acive Burs Conrol Uni Figure 22 Basic and Exendable Blanking There are 2 kinds of Blanking mode; basic mode and he exendable mode. The basic mode has an inernal pre-se 20ms blanking ime while he exendable mode has exended blanking ime o basic mode by connecing an exernal capacior o he BL pin. For he exendable mode, he gae G5 is blocked even hough he 20ms blanking ime is reached if an exernal capacior C BK is added o BL pin. While he 20ms blanking ime is passed, he swich S1 is opened by G2. Then he 0.9V clamped volage a BL pin is charged o 4.0V hrough he inernal I BK consan curren. Then G5 is enabled by comparaor C3. Afer Figure V 3.0V C6a C6b Conrol Uni Acive Burs & G11 The Acive Burs is locaed in he Conrol Uni. Figure 23 shows he relaed componens Enering Acive Burs The FB signal is kep monioring by he comparaor C4. During normal operaion, he inernal blanking ime couner is rese o 0. When FB signal falls below 1.35V, Version Nov 2012

16 Funcional Descripion i sars o coun. When he couner reach 20ms and FB signal is sill below 1.35V, he sysem eners he Acive Burs. This ime window prevens a sudden enering ino he Acive Burs due o large load jumps. Afer enering Acive Burs, a burs flag is se and he inernal bias is swiched off in order o reduce he curren consumpion of he IC o approx. 450uA. I needs he applicaion o enforce he VCC volage above he Undervolage Lockou level of 10.5V such ha he Sarup Cell will no be swiched on accidenally. Or oherwise he power loss will increase drasically. The minimum VCC level during Acive Burs depends on he load condiion and he applicaion. The lowes VCC level is reached a no load condiion. V FB 4.5V 3.61V 3.0V 1.35V Blanking Timer Enering Acive Burs 20ms Blanking Time Leaving Acive Burs Working in Acive Burs Afer enering he Acive Burs, he FB volage rises as V OUT sars o decrease, which is due o he inacive PWM secion. The comparaor C6a moniors he FB signal. If he volage level is larger han 3.61V, he inernal circui will be acivaed; he Inernal Bias circui resumes and sars o provide swiching pulse. In Acive Burs he gae G10 is released and he curren limi is reduced o 0.31V. In one hand, i can reduce he conducion loss and he oher hand, i can reduce he audible noise. If he load a V OUT is sill kep unchanged, he FB signal will drop o 3.0V. A his level he C6b deacivaes he inernal circui again by swiching off he inernal Bias. The gae G11 is acive again as he burs flag is se afer enering Acive Burs. In Acive Burs, he FB volage is changing like a saw ooh beween 3.0V and 3.61V (see Figure 24). V CS 1.06V 0.31V V VCC 10.5V Curren limi level during Acive Burs Leaving Acive Burs The FB volage will increase immediaely if here is a high load jump. This is observed by he comparaor C4. As he curren limi is ca. 31% during Acive Burs, a cerain load jump is needed so ha he FB signal can exceed 4.5V. A ha ime he comparaor C4 reses he Acive Burs conrol which in urn blocks he comparaor C12 by he gae G10. The maximum curren can hen be resumed o sabilize V OUT. I VCC 2.5mA 450uA V OUT Figure 24 Signals in Acive Burs Version Nov 2012

17 Funcional Descripion Proecion s The IC provides several proecion feaures which are separaed ino wo caegories. Some ener Lached Off and he ohers ener Auo Resar. Besides he pre-defined proecion feaure for he Lach off mode, here is also an exernal Lach off Enable pin for cusomer defined Lach off proecion feaures. The Lached Off can only be rese if VCC falls below 6.23V. Boh modes preven he SMPS from desrucive saes.the following able shows he relaionship beween possible sysem failures and he chosen proecion modes. VCC Overvolage Lached Off Overemperaure Lached Off Shor Winding/Shor Diode Lached Off Exernal lach enable Lached Off Overload Auo Resar Open Loop Auo Resar VCC Undervolage Auo Resar Shor Opocoupler Auo Resar Lached Off The VCC volage is observed by comparaor C1 while he FB volage is moniored by he comparaor C4. If he VCC volage is > 24V and he FB is > 4.5V, he overvolage deecion is acivaed. Tha means he overvolage deecion is only acivaed if he FB signal is ouside he operaing range > 4.5V, e.g. when Open Loop happens. The logic can eliminae he possible of enering Lach off mode if here is a small volage overshoos of V VCC during normal operaing. The inernal Volage Reference is swiched off mos of he ime once Lached Off is enered in order o minimize he curren consumpion of he IC. This Lached Off can only be rese if he V VCC < 6.23V. In his mode, only he UVLO is working which conrols he Sarup Cell by swiching on/off a V VCCon /V VCCoff. During his phase, he average curren consumpion is only 250μA. As here is no longer a self-supply by he auxiliary winding, he VCC drops. The Undervolage Lockou swiches on he inegraed Sarup Cell when VCC falls below 10.5V. The Sarup Cell is swiched off again when VCC has exceeded 18V. Once he Lached Off was enered, here is no Sar Up Phase whenever he VCC exceeds he swich-on level of he Undervolage Lockou. Therefore he VCC volage changes beween he swich-on and swich-off levels of he Undervolage Lockou wih a saw ooh shape (see Figure 26). CS 1.66V C11 Spike Blanking 190ns Lached Off Rese V VCC < 6.23V V VCC 18V UVLO 1 T LE # Lach Enable signal BL 0.1V 1ms couner VCC 24V C2 C1 8us Blanking Time & G1 G3 Spike Blanking 8.0us Lached Off 10.5V I VCCSar 0.9mA V OUT FB Figure V C4 Lached Off Thermal Shudown T j >140 C Conrol Uni Volage Reference Figure 26 Signals in Lached Off The Thermal Shudown block moniors he juncion emperaure of he IC. Afer deecing a juncion emperaure higher han lached hermal shudown emperaure; T jsd, he Lached Off is enered. The signals coming from he emperaure deecion and VCC overvolage deecion are fed ino a spike blanking wih a ime consan of 8.0μs in order o ensure he sysem reliabiliy. Version Nov 2012

18 Funcional Descripion Furhermore, a shor winding or shor diode on he secondary side can be deeced by he comparaor C11 which is in parallel o he propagaion delay compensaed curren limi comparaor C10. In normal operaing mode, comparaor C10 conrols he maximum level of he CS signal a 1.06V. If here is a failure such as shor winding or shor diode, C10 is no longer able o limi he CS signal a 1.06V. Insead he comparaor C11 deecs he peak curren volage > 1.66V and eners he Lached Off immediaely in order o keep he SMPS in a safe sage. In case he pre-defined Lach Off feaures are no sufficien, here is a cusomer defined exernal Lach Enable feaure. The Lach Off can be riggered by pulling down he BL pin o < 0.1V. I can simply add a rigger signal o he base of he exernally added ransisor, T LE a he BL pin. To ensure his lach funcion will no be mis-riggered during sar up, a 1ms delay ime is implemened o blank he unsable signal Auo Resar o charge he capacior C BK from 0.9V o 4.0V afer he swich S1 is released. The charging ime from 0.9V o 4.0V are he exendable blanking ime. If C BK is 0.22uF and I BK is 8.4uA, he exendable blanking ime is around 80ms and he oal blanking ime is 100ms. In combining he FB and blanking ime, here is a blanking window generaed which prevens he sysem o ener Auo Resar due o large load jumps. In case of VCC undervolage, he IC eners ino he Auo Resar and sars a new sarup cycle. Shor Opocoupler also leads o VCC undervolage as here is no self supply afer acivaing he inernal reference and bias. In conras o he Lached Off, here is always a Sarup Phase wih swiching cycles in Auo Resar. Afer his Sar Up Phase, he condiions are again checked wheher he failure mode is sill presen. Normal operaion is resumed once he failure mode is removed ha had caused he Auo Resar. BL 5.0V # C BK I BK S1 0.9V 1 G2 4.0V C3 Spike Blanking 8.0us & 4.5V FB C4 20ms Blanking Time G5 Auo Resar Conrol Uni Figure 27 Auo Resar In case of Overload or Open Loop, he FB exceeds 4.5V which will be observed by comparaor C4. Then he inernal blanking couner sars o coun. When i reaches 20ms, he swich S1 is released. Then he clamped volage 0.9V a V BL can increase. When here is no exernal capacior C BK conneced, he V BL will reach 4.0V immediaely. When boh he inpu signals a AND gae G5 is posiive, he Auo-Resar will be acivaed afer he exra spike blanking ime of 8.0us is elapsed. However, when an exra blanking ime is needed, i can be achieved by adding an exernal capacior, C BK. A consan curren source of I BK will sar Version Nov 2012

19 Elecrical Characerisics 4 Elecrical Characerisics Noe: All volages are measured wih respec o ground (Pin 8). The volage levels are valid if oher raings are no violaed. 4.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 7 (VCC) is discharged before assembling he applicaion circui.t a =25 C unless oherwise specified. Parameer Symbol Limi Values Uni Remarks min. max. Drain Source Volage V DS V T j =110 C Pulse drain curren, p limied by max. T j =150 C Avalanche energy, repeiive AR limied by max. T j =150 C 1) Avalanche curren, repeiive AR limied by max. T j =150 C I D_Puls A E AR mj I AR A VCC Supply Volage V VCC V FB Volage V FB V BL Volage V FB V CS Volage V CS V Juncion Temperaure T j C Conroller & CoolMOS Sorage Temperaure T S C Thermal Resisance Juncion -Ambien Soldering emperaure, wavesoldering only allowed a leads ESD Capabiliy (incl. Drain Pin) V ESD - 2 2) R hja - 90 K/W PG-DIP-8 T sold C 1.6mm (0.063in.) from case for 10s kv Human body model 3) 1) Repeiive avalanche causes addiional power losses ha can be calculaed as P AV =E AR *f 2) 3) 2KV is for all pin combinaions excep VCC o GND is 1KV According o EIA/JESD22-A114-B (discharging a 100pF capacior hrough a 1.5kΩ series resisor) Version Nov 2012

20 Elecrical Characerisics 4.2 Operaing Range Noe: Wihin he operaing range he IC operaes as described in he funcional descripion. Parameer Symbol Limi Values Uni Remarks min. max. VCC Supply Volage V VCC V VCCoff 26 V Juncion Temperaure of Conroller T jcon C Max value limied due o hermal shu down of conroller Juncion Temperaure of T jcoolmos C CoolMOS 4.3 Characerisics Supply Secion Noe: The elecrical characerisics involve he spread of values wihin he specified supply volage and juncion emperaure range T J from 25 C o 130 C. Typical values represen he median values, which are relaed o 25 C. If no oherwise saed, a supply volage of V CC = 18 V is assumed. Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sar Up Curren I VCCsar μa V VCC =17V VCC Charge Curren I VCCcharge ma V VCC = 0V I VCCcharge ma V VCC = 1V I VCCcharge ma V VCC =17V Leakage Curren of Sar Up Cell and CoolMOS I SarLeak μa V Drain = 450V a T j =100 C Supply Curren wih Inacive Gae I VCCsup ma Supply Curren wih Acive Gae I VCCsup ma I FB = 0A Supply Curren in Lached Off Supply Curren in Auo Resar wih Inacive Gae Supply Curren in Acive Burs wih Inacive Gae I VCClach μa I FB = 0A I VCCresar μa I FB = 0A I VCCburs μa V FB = 2.5V I VCCburs μa V VCC = 11.5V,V FB = 2.5V VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hyseresis V VCCon V VCCoff V VCChys V V V Version Nov 2012

21 Elecrical Characerisics Inernal Volage Reference Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Trimmed Reference Volage V REF V measured a pin FB I FB = PWM Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Fixed Oscillaor Frequency f OSC khz f OSC khz T j = 25 C Frequency Jiering Range f jier - ±4.0 - khz T j = 25 C Max. Duy Cycle D max Min. Duy Cycle D min V FB < 0.3V PWM-OP Gain A V Volage Ramp Offse V Offse-Ramp V V FB Operaing Range Min Level V FBmin V V FB Operaing Range Max level V FBmax V CS=1V, limied by Comparaor C4 1) FB Pull-Up Resisor R FB kω 1) The parameer is no subjeced o producion es - verified by design/characerizaion Sof Sar ime Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sof Sar ime SS ms Version Nov 2012

22 Elecrical Characerisics Conrol Uni Parameer Symbol Limi Values Uni Tes Condiion Clamped V BL volage during Normal Operaing Blanking ime volage limi for Comparaor C3 Over Load & Open Loop Deecion Limi for Comparaor C4 Acive Burs Level for Comparaor C5 Acive Burs Level for Comparaor C6a Acive Burs Level for Comparaor C6b min. yp. max. V BLclmp V V FB = 4V V BKC V V FBC V V FBC V V FBC6a V Afer Acive Burs is enered V FBC6b V Afer Acive Burs is enered Overvolage Deecion Limi V VCCOVP V V FB = 5V Lach Enable level a BL pin V LE V > 30μs Charging curren a BL pin I BK μa Charge sars afer he buil-in 20ms blanking ime elapsed Lached Thermal Shudown 1) T jsd C Buil-in Blanking Time for Overload Proecion or ener Acive Burs Inhibi Time for Lach Enable funcion during Sar up Spike Blanking Time before Lach off or Auo Resar Proecion Power Down Rese for Lached BK ms wihou exernal capacior a BL pin IHLE ms Coun when VCC > 18V Spike μs V VCCPD V Afer Lached Off is enered 1) The parameer is no subjeced o producion es - verified by design/characerizaion. The hermal shu down emperaure refers o he juncion emperaure of he conroller. Noe: The rend of all he volage levels in he Conrol Uni is he same regarding he deviaion excep V VCCOVP and V VCCPD Version Nov 2012

23 Elecrical Characerisics Curren Limiing Parameer Symbol Limi Values Uni Tes Condiion Peak Curren Limiaion (incl. Propagaion Delay) Peak Curren Limiaion during Acive Burs min. yp. max. V csh V dv sense / d = 0.6V/μs (see Figure 20) V CS V Leading Edge Blanking LEB ns CS Inpu Bias Curren I CSbias μa V CS =0V Over Curren Deecion for V CS V Lached Off CS Spike Blanking for Comparaor C11 CSspike ns CoolMOS Secion Parameer Symbol Limi Values Uni Tes Condiion Drain Source Breakdown Volage V (BR)DSS Drain Source On-Resisance R DSon - - min. yp. max ) The parameer is no subjeced o producion es - verified by design/characerizaion V V Ω Ω T j = 25 C T j = 110 C T j = 25 C T j =125 C 1) a I D = 1.0A Effecive oupu capaciance, C o(er) pf V DS = 0V o 480V energy relaed Rise Time rise ) - ns Fall Time fall ) - ns 2) Measured in a Typical Flyback Converer Applicaion Version Nov 2012

24 Temperaure deraing curve 5 Temperaure deraing curve 10 Safe Operaing Area for ICE3A(B)1065(ELJ) I D = f ( V DS ) parameer : D = 0, T C = 25deg.C 1 ID [A] p = 0.1ms p = 1ms p = 10ms p = 100ms p = 1000ms DC V DS [V] Figure 28 Safe Operaing area (SOA) curve 120 (p g p ) SOA emperaure deraing coefficien [%] Figure SOA emperaure deraing coefficien curve Version Nov 2012

25 Ouline Dimension 6 Ouline Dimension PG-DIP-8 (Plasic Dual In-Line Ouline) Figure 30 PG-DIP-8 (PB-free Plaing Plasic Dual In-Line Ouline) Version Nov 2012

26 Marking 7 Marking Marking Figure 31 Marking Version Nov 2012

27 Schemaic for recommended PCB layou 8 Schemaic for recommended PCB layou TR1 L Spark Gap 1 FUSE1 X-CAP C1 Spark Gap 3 L1 BR1 C11 bulk cap R11 D11 C12 D21 C21 Vo GND Spark Gap 2 N C2 Y-CAP C3 Spark Gap 4 Y-CAP C4 Y-CAP D11 IC11 R12 CS DRAIN F3 SOFTS VCC CoolSET Z11 R13 R14 C16 D13 R23 R22 R21 GND GND FB NC C22 C13 C15 C14 C23 R24 IC12 IC21 F3 CoolSET schemaic for recommended PCB layou R25 Figure 32 Schemaic for recommended PCB layou General guideline for PCB layou design using F3 CoolSET (refer o Figure 32): 1. Sar Ground a bulk capacior ground, C11: Sar Ground means all primary DC grounds should be conneced o he ground of bulk capacior C11 separaely in one poin. I can reduce he swiching noise going ino he sensiive pins of he CoolSET device effecively. The primary DC grounds include he followings. a. DC ground of he primary auxiliary winding in power ransformer, TR1, and ground of C16 and Z11. b. DC ground of he curren sense resisor, R12 c. DC ground of he CoolSET device, GND pin of IC11; he signal grounds from C13, C14, C15 and collecor of IC12 should be conneced o he GND pin of IC11 and hen sar connec o he bulk capacior ground. d. DC ground from bridge recifier, BR1 e. DC ground from he bridging Y-capacior, C4 2. High volage races clearance: High volage races should keep enough spacing o he nearby races. Oherwise, arcing would incur. a. 400V races (posiive rail of bulk capacior C11) o nearby race: > 2.0mm b. 600V races (drain volage of CoolSET IC11) o nearby race: > 2.5mm 3. Filer capacior close o he conroller ground: Filer capaciors, C13, C14 and C15 should be placed as close o he conroller ground and he conroller pin as possible so as o reduce he swiching noise coupled ino he conroller. Guideline for PCB layou design when >3KV lighning surge es applied (refer o Figure 32): 1. Add spark gap Spark gap is a pair of saw-ooh like copper plae facing each oher which can discharge he accumulaed charge during surge es hrough he sharp poin of he saw-ooh plae. a. Spark Gap 3 and Spark Gap 4, inpu common mode choke, L1: Gap separaion is around 1.5mm (no safey concern) Version Nov 2012

28 Schemaic for recommended PCB layou b. Spark Gap 1 and Spark Gap 2, Live / Neural o GROUND: These 2 Spark Gaps can be used when he lighning surge requiremen is >6KV. 230Vac inpu volage applicaion, he gap separaion is around 5.5mm 115Vac inpu volage applicaion, he gap separaion is around 3mm 2. Add Y-capacior (C2 and C3) in he Live and Neural o ground even hough i is a 2-pin inpu 3. Add negaive pulse clamping diode, D11 o he Curren sense resisor, R12: The negaive pulse clamping diode can reduce he negaive pulse going ino he CS pin of he CoolSET and reduce he abnormal behavior of he CoolSET. The diode can be a fas speed diode such as IN4148. The principle behind is o drain he high surge volage from Live/Neural o Ground wihou passing hrough he sensiive componens such as he primary conroller, IC11. Version Nov 2012

29 Toal Qualiy Managemen Qualiä ha für uns eine umfassende Bedeuung. Wir wollen allen Ihren Ansprüchen in der besmöglichen Weise gerech werden. Es geh uns also nich nur um die Produkqualiä unsere Ansrengungen gelen gleichermaßen der Lieferqualiä und Logisik, dem Service und Suppor sowie allen sonsigen Beraungs- und Bereuungsleisungen. Dazu gehör eine besimme Geiseshalung unserer Miarbeier. Toal Qualiy im Denken und Handeln gegenüber Kollegen, Lieferanen und Ihnen, unserem Kunden. Unsere Leilinie is jede Aufgabe mi Null Fehlern zu lösen in offener Sichweise auch über den eigenen Arbeisplaz hinaus und uns sändig zu verbessern. Unernehmenswei orienieren wir uns dabei auch an op (Time Opimized Processes), um Ihnen durch größere Schnelligkei den enscheidenden Webewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leisung durch umfassende Qualiä zu beweisen. Wir werden Sie überzeugen. Qualiy akes on an allencompassing significance a Semiconducor Group. For us i means living up o each and every one of your demands in he bes possible way. So we are no only concerned wih produc qualiy. We direc our effors equally a qualiy of supply and logisics, service and suppor, as well as all he oher ways in which we advise and aend o you. Par of his is he very special aiude of our saff. Toal Qualiy in hough and deed, owards co-workers, suppliers and you, our cusomer. Our guideline is do everyhing wih zero defecs, in an open manner ha is demonsraed beyond your immediae workplace, and o consanly improve. Throughou he corporaion we also hink in erms of Time Opimized Processes (op), greaer speed on our par o give you ha decisive compeiive edge. Give us he chance o prove he bes of performance hrough he bes of qualiy you will be convinced. hp:// Published by Infineon Technologies AG