A8502 Wide Input Voltage Range, High Efficiency Fault Tolerant LED Driver

Transcription

1 FEATURES AND BENEFITS AEC-Q100 qualified Wide inpu volage range of 5 o 40 V for sar/sop, cold crank and load dump requiremens Fully inegraed LED curren sinks and boos converer wih 60 V DMOS Sync funcion o synchronize boos converer swiching frequency up o 2.3 MHz, allowing operaion above he AM band Excellen inpu volage ransien response Single resisor primary OVP minimizes V OUT leakage Inernal secondary OVP for redundan proecion LED curren of 120 ma per channel Drives up o 12 series LEDs in 2 parallel srings 0.7% o 0.8% LED o LED maching accuracy PWM and analog dimming inpus 5000:1 PWM dimming a 200 Hz Provides driver for opional exernal PMOS inpu disconnec swich Exensive proecion agains: Shored boos swich or inducor Shored FSET or ISET resisor Shored oupu Open or shored LED pin Open boos Schoky Overemperaure (OTP) PACKAGE: 16-pin TSSOP wih exposed hermal pad (suffix LP) No o scale DESCRIPTION The A8502 is a muli-oupu whie LED driver for small-size LCD backlighing. I inegraes a curren-mode boos converer wih inernal power swich and wo curren sinks. The boos converer can drive up o 24 LEDs, 12 LEDs per sring, a 120 ma. The LED sinks can be paralleled ogeher o achieve even higher LED currens, up o 240 ma. The A8502 can operae wih a single power supply, from 5 o 40 V, which allows he par o wihsand load dump condiions encounered in auomoive sysems. If required, he A8502 can drive an exernal P-FET o disconnec he inpu supply from he sysem in he even of a faul. The A8502 provides proecion agains oupu shor and overvolage, open or shored diode, open or shored LED pin, shored boos swich or inducor, shored FSET or ISET resisor, and IC overemperaure. A dual level cycle-by-cycle curren limi funcion provides sof sar and proecs he inernal curren swich agains high curren overloads. The A8502 has a synchronizaion pin ha allows is swiching frequencies o be synchronized in he range of 260 khz o 2.3 MHz. The high swiching frequency allows he A8502 o operae above he AM radio band. Coninued on he nex page APPLICATIONS: LCD backlighing or LED lighing for: Auomoive infoainmen Auomoive cluser Auomoive cener sack Typical Applicaion Circui V IN 10 o 14 V R SC Ω Q1 L1 D1 10 µh 2A/ 60 V V OUT C IN 4.7 µf 50 V 100 kω V C R ADJ 249 Ω R C 20 Ω C C 22 nf C VDD 0.1 µf GATE VSENSE VIN VDD SW A8502 PAD OVP LED1 R OVP 137 kω C OUT 4.7 µf 50 V R ISET 8.25 kω R FSET 10 kω FAULT APWM ISET FSET/SYNC AGND PGND LED2 COMP C P 120 pf R Z 120 Ω C Z 0.47 µf Figure 1. Applicaion wih VIN o ground shor proecion, using opional P-MOSFET sensing A8502-DS, Rev. 7 February 27, 2017

2 DESCRIPTION (coninued) The A8502 is provided in a 16-pin TSSOP package (suffix LP) wih an exposed pad for enhanced hermal dissipaion. I is lead (Pb) free, wih 100% mae in lead frame plaing. SELECTION GUIDE Par Number Packing* A8502KLPTR-T 4000 pieces per 13-in. reel *Conac Allegro for addiional packing opions ABSOLUTE MAXIMUM RATINGS* Characerisic Symbol Noes Raing Uni LEDx Pins 0.3 o 55 V OVP Pin 0.3 o 60 V VIN, VSENSE, GATE Pins SW Pin VSENSE and GATE pins should no exceed V IN by more han 0.4 V 0.3 o 40 V Coninuous 0.6 o 62 V < 50 ns 1.0 V F ĀŪ L T Pin -0.3 o 40 V ISET, FSET, APWM, COMP Pins 0.3 o 5.5 V All Oher Pins 0.3 o 7 V Operaing Ambien Temperaure T A Range K 40 o 125 C Maximum Juncion Temperaure T J (max) 150 C Sorage Temperaure T sg 55 o 150 C *Sresses beyond hose lised in his able may cause permanen damage o he device. The Absolue Maximum raings are sress raings only, and funcional operaion of he device a hese or any oher condiions beyond hose indicaed in he Elecrical Characerisics able is no implied. Exposure o Absolue Maximum-raed condiions for exended periods may affec device reliabiliy. Table of Conens Specificaions 2 Pin-ou Diagram and Terminal Lis 3 Characerisic Performance 8 Funcional Descripion 11 Enabling he IC 11 Powering up: LED pin shor-o-ground check 11 Sof sar funcion 13 Frequency selecion 13 Sync 14 LED curren seing and LED dimming 16 PWM dimming 16 APWM pin 17 Analog dimming 19 LED shor deec 19 Overvolage proecion 19 Boos swich overcurren proecion 22 Inpu overcurren proecion and disconnec swich 23 Seing he curren sense resisor 24 Inpu UVLO 24 VDD 24 Shudown 25 Faul proecion during operaion 25 Applicaion Informaion 27 Design Example for Boos Configuraion 27 Design Example for SEPIC Configuraion 31 Package Ouline Drawing 35 2

3 Thermal Characerisics: May require deraing a maximum condiions; see applicaion informaion Characerisic Symbol Tes Condiions* Value Uni Package Thermal Resisance R θja On 2-layer PCB, 3 in C/W On 4-layer PCB based on JEDEC sandard 34 C/W *Addiional hermal informaion available on he Allegro websie Terminal Lis Table Pinou Diagram Number Name Funcion 1 VDD Oupu of inernal LDO; connec a 0.1 µf decoupling capacior beween his pin and ground. 2 PGND Power ground for inernal DMOS device. 3 OVP Overvolage Condiion (OVP) sense; connec he R OVP resisor from V OUT o his pin o adjus he overvolage proecion. 4 SW The drain of he inernal DMOS swich of he boos converer. 5 GATE Oupu gae driver pin for exernal P-channel FET conrol. 6 VSENSE VDD 1 PGND 2 OVP 3 SW 4 GATE 5 VSENSE 6 VIN 7 FAULT 8 16 LED2 15 LED1 14 AGND 13 ISET 12 FSET/SYNC APWM 9 COMP Connec his pin o he negaive sense side of he curren sense resisor R SC. The hreshold volage is measured as V IN V SENSE. There is also a fixed curren sink o allow for rip hreshold adjusmen. 7 VIN Inpu power o he A8502 as well as he posiive inpu used for curren sense resisor. PAD 8 F Ā Ū L T Indicaes a faul condiion. Connec a 100 kω resisor beween his pin and he required logic level volage. The pin is an open drain ype configuraion ha will be pulled low when a faul occurs. 9 COMP Oupu of he error amplifier and compensaion node. Connec a series R Z -C Z nework from his pin o ground for conrol loop compensaion. 10 APWM Analog rimming opion for dimming. Applying a digial PWM signal o his pin adjuss he inernal I SET curren. 11 PWM dimming pin, used o conrol he LED inensiy by using pulse widh modulaion. Also used o enable he A FSET/SYNC Frequency/synchronizaion pin. A resisor R FSET from his pin o ground ses he swiching frequency. This pin can also be used o synchronize wo or more A8502s in he sysem. The maximum synchronizaion frequency is 2.3 MHz. 13 ISET Connec he R ISET resisor beween his pin and ground o se he 100% LED curren. 14 AGND LED signal ground. 15 LED1 Connec he cahode of he LED sring o his pin. 16 LED2 Connec he cahode of he LED sring o his pin. PAD Exposed pad of he package providing enhanced hermal dissipaion. This pad mus be conneced o he ground plane(s) of he PCB wih a leas 8 vias, direcly in he pad. 3

4 Funcional Block Diagram VDD SW Inernal V CC VIN Regulaor UVLO V Ref V REF FSET/SYNC COMP Inernal V CC Oscillaor AGND + Driver Circui Faul Diode Open + Sense Inernal Sof Sar I SS Curren Sense + + PGND VSENSE Inpu Curren Sense Amplifier Thermal Shudown I ADJ GATE APWM PMOS Driver 100 kω Inernal V CC Enable PWM GOFF V REF ISET I SS Faul LED Driver Faul OVP Sense + V REF Open/Shor LED Deec OVP LED1 LED2 ISET AGND Faul FAULT PAD PGND AGND 4

5 ELECTRICAL CHARACTERISTICS [1][2] : Valid a V IN = 16 V, T A = 25 C, indicaes specificaions guaraneed by design and characerizaion over full operaing emperaure range wih T A = T J = 40 C o 125 C, unless oherwise saed Characerisics Symbol Tes Condiions Min. Typ. Max. Uni INPUT VOLTAGE SPECIFICATIONS Operaing Inpu Volage Range [3] V IN 5 40 V UVLO Sar Threshold V UVLOrise V IN rising 4.35 V UVLO Sop Threshold V UVLOfall V IN falling 3.90 V UVLO Hyseresis [2] V UVLOHYS mv INPUT CURRENTS Inpu Quiescen Curren I Q = V IH ; SW = 2 MHz, no load ma Inpu Sleep Supply Curren I QSLEEP V IN = 16 V, V PWMEN = V FSETSYNC = 0 V μa INPUT LOGIC LEVELS ( AND APWM) Inpu Logic Level-Low V IL V IN hroughou operaing inpu volage range 400 mv Inpu Logic Level-High V IH V IN hroughou operaing inpu volage range 1.5 V Pin Open Drain Pull-Down Resisor R PWMEN = 5 V kω APWM Pull-Down Resisor R APWM = V IH kω APWM APWM Frequency [2] f APWM V IH = 2 V, V IL = 0 V khz ERROR AMPLIFIER Open Loop Volage Gain A VOL db Transconducance g m ΔI COMP = ±10 μa μa/v Source Curren I EA(SRC) V COMP = 1.5 V 350 μa Sink Curren I EA(SINK) V COMP = 1.5 V 350 μa COMP Pin Pull-down Resisance R COMP F Ā Ū L T = Ω OVERVOLTAGE PROTECTION Overvolage Threshold V OVP(h) OVP conneced o V OUT V OVP Sense Curren I OVPH μa OVP Leakage Curren I OVPLKG R OVP = 40.2 kω, V IN = 16 V, = V IL μa Secondary Overvolage Proecion V OVP(sec) V BOOST SWITCH Swich On-Resisance R SW I SW = A, V IN = 16 V mω Swich Leakage Curren I SWLKG V SW = 16 V, = V IL µa Swich Curren Limi I SW(LIM) A Secondary Swich Curren Limi [2] Higher han I I SW(LIM) (max) for all condiions, SW(LIM2) device laches when deeced 7.00 A Sof Sar Boos Curren Limi I SWSS(LIM) Iniial sof sar curren for boos swich 700 ma Minimum Swich On-Time SWONTIME ns Minimum Swich Off-Time SWOFFTIME ns Coninued on he nex page 5

6 ELECTRICAL CHARACTERISTICS [1][2] (coninued): Valid a V IN = 16 V, T A = 25 C, indicaes specificaions guaraneed by design and characerizaion over full operaing emperaure range wih T A = T J = 40 C o 125 C, unless oherwise saed Characerisics Symbol Tes Condiions Min. Typ. Max. Uni OSCILLATOR FREQUENCY Oscillaor Frequency f SW R FSET = 10 kω MHz R FSET = 20 kω MHz R FSET = 35.6 kω khz R FSET = 105 kω khz FSET/SYNC Pin Volage V FSET R FSET = 10 kω 1.00 V FSET Frequency Range f FSET khz SYNCHRONIZATION Synchronized Swiching Frequency f SWSYNC khz Synchronizaion Inpu Minimum Off Time PWSYNCOFF 150 ns Synchronizaion Inpu Minimum On Time PWSYNCON 150 ns V SYNC(H) FSET/SYNC pin, high level 2.0 V SYNC Inpu Logic Volage V SYNC(L) FSET/SYNC pin, low level 0.4 V LED CURRENT SINKS LEDx Accuracy Err LED I SET = 120 µa 2 % LEDx Maching ΔLEDx I SET = 120 µa 1 % LEDx Regulaion Volage V LED V LED1 = V LED2, I SET = 120 µa mv I SET o I LEDx Curren Gain A ISET I SET = 120 µa A/A ISET Pin Volage V ISET V Allowable ISET Curren I SET µa While LED sinks are in regulaion, sensed V LED Shor Deec V LEDSC from LEDx pin o ground V Curren hrough each enabled LEDx pin Sof Sar LEDx Curren I LEDSS during sof sar 3.2 ma Maximum PWM Dimming Unil Off Time [2] PWML Measured while = low, during dimming conrol and inernal references are powered-on (exceeding PWML resuls in shudown) 32,750 Minimum PWM On Time PWMH Firs cycle when powering-up device µs Time beween PWM enable and LED curren PWM High o LED On Delay dpwm(on) reaching 90% of maximum Time beween PWM enable going low and PWM Low o LED Off Delay dpwm(off) LED curren reaching 10% of maximum f SW cycles µs ns Coninued on he nex page 6

7 ELECTRICAL CHARACTERISTICS [1][2] (coninued): Valid a V IN = 16 V, T A = 25 C, indicaes specificaions guaraneed by design and characerizaion over full operaing emperaure range wih T A = T J = 40 C o 125 C, unless oherwise saed Characerisics Symbol Tes Condiions Min. Typ. Max. Uni GATE PIN GATE Pin Sink Curren I GSINK V GS = V IN 104 µa Gae Faul Shudown Greaer Than 2 Curren [2] GFAULT2 3 µs Gae Faul Shudown Greaer Than 1 2 Curren GFAULT1 10,000 Gae o source volage measured when gae Gae Volage V GS is on 6.7 V VSENSE PIN VSENSE Pin Sink Curren I ADJ µa Measured beween VIN and VSENSE, VSENSE Trip Poin V SENSErip1 R ADJ = 0 Ω mv VSENSE 2 Trip [2] V SENSErip2 2 V SENSErip, insananeous shudown, R ADJ = 0 Ω 180 mv F Ā Ū L T PIN F Ā Ū L T Pull-Down Volage V FAULT I FAULT = 1 ma 0.5 V F Ā Ū L T Pin Leakage Curren I FAULTLKG V FAULT = 5 V 1 µa THERMAL PROTECTION (TSD) Thermal Shudown Threshold [2] T SD Temperaure rising 165 C Thermal Shudown Hyseresis [2] T SDHYS 20 C 1 For inpu and oupu curren specificaions, negaive curren is defined as coming ou of he node or pin (sourcing); posiive curren is defined as going ino he node or pin (sinking). 2 Ensured by design and characerizaion, no producion esed. 3 Minimum V IN = 5 V is only required a sarup. Afer sarup is compleed, he IC is able o funcion down o V IN = 4 V. f SW cycles 7

8 CHARACTERISTIC PERFORMANCE T A = T J I QSLEEP (µa) VIN Inpu Sleep Mode Curren versus Ambien Temperaure Temperaure ( C) Temperaure ( C) V UVLOrise (V) VIN UVLO Sar Threshold Volage versus Ambien Temperaure fsw (MHz) Swiching Frequency versus Ambien Temperaure Temperaure ( C) V UVLOfall (V) VIN UVLO Sop Threshold Volage versus Ambien Temperaure Temperaure ( C) I OVPH (µa) OVP Pin Sense Curren versus Ambien Temperaure Temperaure ( C) VOVP(h) (V) OVP Pin Overvolage Threshold versus Ambien Temperaure Temperaure ( C) 8

9 AISET ISET o LED Curren Gain versus Ambien Temperaure I SET = 120 µa Temperaure ( C) LEDx (%) LED o LED Maching Accuracy versus Ambien Temperaure Temperaure ( C) ILED (ma) LED Curren versus Ambien Temperaure I SET = 120 µa V GS (V) Inpu Disconnec Swich Gae o Source Volage versus Ambien Temperaure Temperaure ( C) Temperaure ( C) ErrLED (%) LED Curren Sepoin Accuracy versus Ambien Temperaure Temperaure ( C) IADJ (µa) VSENSE Pin Sink Curren versus Ambien Temperaure Temperaure ( C) 9

10 100 Efficiency for Various LED Configuraions I LED = 80 ma, LED V f 3.2 V Efficiency (%) srings, 6 series LEDs each 2 srings, 7 series LEDs each 2 srings, 8 series LEDs each Inpu Volage, V IN (V) Efficiency (%) Efficiency for Various LED Configuraions I LED = 100 ma, LED V f 3.2 V srings, 6 series LEDs each 2 srings, 7 series LEDs each 2 srings, 8 series LEDs each Inpu Volage, V IN (V) 10

11 FUNCTIONAL DESCRIPTION The A8502 incorporaes a curren-mode boos conroller wih inernal DMOS swich, and wo LED curren sinks. I can be used o drive wo LED srings of up o 12 whie LEDs in series, wih curren up o 120 ma per sring. For opimal efficiency, he oupu of he boos sage is adapively adjused o he minimum volage required o power boh LED srings. This is expressed by he following equaion: V OUT = max ( V LED1, V LED2 ) + V REG (1) where V LEDx is he volage drop across LED srings 1 and 2, and V REG is he regulaion volage of he LED curren sinks (ypically 0.72 V a he maximum LED curren). VDD FSET/SYNC ISET Enabling he IC The IC urns on when a logic high signal is applied on he pin wih a minimum duraion of PWMH for he firs clock cycle, and he inpu volage presen on he VIN pin is greaer han he 4.35 V necessary o clear he UVLO (V UVLOrise ) hreshold. The power-up sequence is shown in figure 2. Before he LEDs are enabled, he A8502 driver goes hrough a sysem check o deermine if here are any possible faul condiions ha migh preven he sysem from funcioning correcly. Also, if he FSET/SYNC pin is pulled low, he IC will no power-up. More informaion on he FSET/SYNC pin can be found in he Sync secion of his daashee. Powering up: LED pin shor-o-ground check The VIN pin has a UVLO funcion ha prevens he A8502 from powering-up unil he UVLO hreshold is reached. Afer he VIN pin goes above UVLO, and a high signal is presen on he pin, he IC proceeds o power-up. As shown in figure 3, a his poin he A8502 enables he disconnec swich and checks if any LEDx pins are shored o ground and/or are no used. The LED deec phase sars when he GATE volage of he disconnec swich is equal o V IN 4.5 V. Afer he volage hreshold on he LEDx pins exceeds 120 mv, a delay of beween 3000 and 4000 clock cycles is used o deermine he saus of he pins. Thus, he LED deecion duraion varies wih he swiching Figure 2. Power-up diagram; shows VDD (ch1, 2 V/div.), FSET/SYNC (ch2, 1 V/div.), ISET (ch3, 1 V/div.), and (ch4, 2 V/div.) pins, ime = 200 µs/div. GATE LEDx ISET GATE = V IN 4.5 V LED deecion period Figure 3. Power-up diagram; shows he relaionship of an LEDx pin wih respec o he gae volage of he disconnec swich (if used) during he LED deec phase, as well as he duraion of he LED deec phase for a swiching frequency of 2 MHz; shows GATE (ch1, 5 V/div.), LED (ch2, 500 mv/div.), ISET (ch3, 1 V/div.), and (ch4, 5 V/div.) pins, ime = 500 µs/div. 11

12 frequency, as shown in he following able: Swiching Frequency (MHz) Deecion Time (ms) o o o 5 LED1 LED2 LED deecion period o 6.7 The LED pin deecion volage hresholds are as follows: ISET LED Pin Volage LED Pin Saus Acion <70 mv Shor-o-ground Power-up is haled 150 mv No used LED removed from operaion 325 mv LED pin in use None All unused pins should be conneced wih a 1.54 kω resisor o ground, as shown in figure 5. The unused pin, wih he pull-down resisor, will be aken ou of regulaion a his poin and will no conribue o he boos regulaion loop. 4B. Example wih LED2 pin no being used; he deec volage is abou 150 mv; shows LED1 (ch1, 500 mv/div.), LED2 (ch2, 500 mv/div.), ISET (ch3, 1 V/div.), and (ch4, 5 V/div.) pins, ime = 500 µs/div. Shor removed LED1 LED deecion period Pin shored LED1 LED2 LED2 ISET ISET 4A. An LED deec occurring when boh LED pins are seleced o be used; shows LED1 (ch1, 500 mv/div.), LED2 (ch2, 500 mv/div.), ISET (ch3, 1 V/div.), and (ch4, 5 V/div.) pins, ime = 500 µs/div. 4C. Example wih one LED shored o ground. The IC will no proceed wih power-up unil he shored LED pin is released, a which poin he LED is checked o see if i is being used; shows LED1 (ch1, 500 mv/div.), LED2 (ch2, 500 mv/div.), ISET (ch3, 1 V/div.), and (ch4, 5 V/div.) pins, ime = 1 ms/div. 12

13 If a LEDx pin is shored o ground he A8502 will no proceed wih sof sar unil he shor is removed from he LEDx pin. This prevens he A8502 from powering-up and puing an unconrolled amoun of curren hrough he LEDs. Sof sar funcion During sof sar he LEDx pins are se o sink (I LEDSS ) and he boos swich curren is reduced o he I SWSS(LIM) level o limi he inrush curren generaed by charging he oupu capaciors. When he converer senses ha here is enough volage on he LEDx pins he converer proceeds o increase he LED curren o he prese regulaion curren and he boos swich curren limi is swiched o he I SW(LIM) level o allow he A8502 o deliver he necessary oupu power o he LEDs. This is shown in figure 6. Frequency selecion The swiching frequency on he boos regulaor is se by he resisor conneced o he FSET/SYNC pin. The swiching frequency can be can be anywhere from 200 khz o 2.3 MHz. Figure 7 shows he ypical swiching frequency for differen resisor values. The relaionship beween FSET resisance and he ypical swiching frequency is given as: k f SW = (R FSET + R INT) where f SW is in MHz, R FSET is in kw, k = 20.9, and R INT = 0.6 kw (inernal resisance of FSET pin). In case during operaion a faul occurs ha will increase he swiching frequency, he FSET/SYNC pin is clamped o a maximum swiching frequency of no more han 3.5 MHz. If he FSET/SYNC pin is shored o GND he par will shu down. For more deails see he Faul Mode able laer in his daashee. A8502 A8502 Frequency (MHz) Inrush curren caused by enabling he disconnec swich (when used) I OUT I IN V OUT Operaion during I SWSS(lim) Normal operaion I SW(lim) Figure 6. Sarup diagram showing he inpu curren, oupu volage, and oupu curren; shows I OUT (ch1, 200 ma/div.), I IN (ch2, 1 A/div.), V OUT (ch3, 20 V/div.), and (ch4, 5 V/div.), ime = 1 ms/div GND LED1 LED kω GND LED1 LED FSET Resisance (k ) Figure 7. Typical Swiching Frequency versus value of R FSET resisor. Figure 5. Channel selec seup: (lef) using only channel LED1, (righ) using boh channels. 13

14 Sync The A8502 can also be synchronized using an exernal clock on he FSET/SYNC pin. Figure 8 shows he correspondence of a sync signal and he FSET/SYNC pin, and figure 9 shows he resul when a sync signal is deeced: he LED curren does no show any variaion while he frequency changeover occurs. A power-up if he FSET/SYNC pin is held low, he IC will no power-up. Only when he FSET/SYNC pin is ri-saed o allow he pin o rise, o abou 1 V, or when a synchronizaion clock is deeced, will he A8502 ry o power-up. The basic requiremen of he sync signal is 150 ns minimum onime and 150 ns minimum off ime, as indicaed by he specificaions for PWSYNCON and PWSYNCOFF. Figure 10 shows he iming for a synchronizaion clock ino he A8502 a 2.2 MHz. Thus any pulse wih a duy cycle of 33% o 66% a 2.2 MHz can be used o synchronize he IC. The SYNC pulse duy cycle ranges for seleced swiching frequencies are: SYNC Pulse Frequency (MHz) Duy Cycle Range (%) o o o o o 91 If during operaion a sync clock is los, he IC will rever o he prese swiching frequency ha is se by he resisor R FSET. During his period he IC will sop swiching for a maximum period of abou 7 µs o allow he sync deecion circuiry o swich over o he exernally prese swiching frequency. If he clock is held low for more han 7 µs, he A8502 will shu V OUT I OUT FSET/SYNC SW node Figure 8. Diagram showing a synchronized FSET/SYNC pin and swich node; shows V OUT (ch1, 20 V/div.), I OUT (ch2, 200 ma/div.), FSET/SYNC (ch3, 2 V/div.), and SW node (ch4, 20 V/div.), ime = 2 µs/div. 2 MHz operaion FSET/SYNC 1 MHz operaion SW node V OUT I OUT Figure 9. Transiion of he SW waveform when he SYNC pulse is deeced. The A8502 swiching a 2 MHz, applied SYNC pulse a 1 MHz; shows V OUT (ch1, 20 V/div.), I OUT (ch2, 200 ma/div.), FSET/SYNC (ch3, 2 V/div.), and SW node (ch4, 20 V/div.), ime = 5 µs/div. 14

15 down. In his shudown mode he IC will sop swiching, he inpu disconnec swich is open, and he LEDs will sop sinking curren. To shudown he IC ino low power mode, he user mus disable he IC using he PWM pin, by keeping he pin low for a period of 32,750 clock cycles. If he FSET/SYNC pin is released a any ime afer 7 µs, he A8502 will proceed o sof sar. To preven generaing a faul when he exernal SYNC signal is suck a low, he circui shown in Figure 11 can be used. When he exernal SYNC signal goes low, he A8502 will coninue o operae normally a he swiching frequency se by RFSET. No FAULT flag is generaed. PWSYNCON 154 ns 150 ns 150 ns PWSYNCOFF T = 454 ns Figure 10. SYNC pulse on and off ime requiremens. Exernal Synchronizaion Signal FSET A pf Schoky Barrier Diode R FSET 10.2 kω Figure 11. Counermeasure o preven exernal sync signal suck-a-low faul 15

16 LED curren seing and LED dimming The maximum LED curren can be up o 120 ma per channel, and is se hrough he ISET pin. To se he I LED curren, connec a resisor, R ISET, beween his pin and ground, according o he following formula: R ISET = ( ) / I LED (2) where I LED is in A and R ISET is in Ω. This ses he maximum curren hrough he LEDs, referred o as he 100% curren. Sandard R ISET values, a gain equals 980, are as follows: V OUT COMP PWM I LED Sandard Closes R ISET Resisor Value (kω) LED curren per LED, I LED (ma) Figure 12B. Typical PWM diagram showing V OUT, I LED, and COMP pin as well as he PWM signal. PWM dimming frequency is 500 Hz a 1% duy cycle ; shows V OUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3, 5 V/div.), and I LED (ch4, 50 ma/div.), ime = 500 µs/div. PWM PWM dimming The LED curren can be reduced from he 100% curren level by PWM dimming using he pin. When he pin is pulled high, he A8502 urns on and all enabled LEDs sink 100% curren. When is pulled low, he boos converer and LED sinks are urned off. The compensaion (COMP) pin is floaed, and criical inernal circuis are kep acive. The ypical PWM dimming frequencies fall beween 200 Hz and 1 khz. Figures 12A o 12D provide examples of PWM swiching behavior. I LED Figure 12C. Delay from rising edge of PWM signal o LED curren; shows PWM (ch1, 2 V/div.), and I LED (ch2, 50 ma/div.), ime = 200 ns/div. V OUT COMP PWM PWM I LED I LED Figure 12A. Typical PWM diagram showing V OUT, I LED, and COMP pin as well as he PWM signal. PWM dimming frequency is 500 Hz a 50% duy cycle; shows V OUT (ch1, 10 V/div.), COMP (ch2, 2 V/div.), PWM (ch3, 5 V/div.), and I LED (ch4, 50 ma/div.), ime = 500 µs/div. Figure 12D. Delay from falling edge of PWM signal o LED curren urn off; shows PWM (ch1, 2 V/div.), and I LED (ch2, 50 ma/div.), ime = 200 ns/div. 16

17 Anoher imporan feaure of he A8502 is he PWM signal o LED curren delay. This delay is ypically less han 500 ns, which allows greaer accuracy a low PWM dimming duy cycles, as shown in figure 13. APWM pin The APWM pin is used in conjuncion wih he ISET pin (see figure 14). This is a digial signal pin ha inernally adjuss he ISET curren. When his pin is no used i should be ied o ground. The ypical inpu signal frequency is beween 20 khz and 1 MHz. The duy cycle of his signal is inversely proporional o he percenage of curren ha is delivered o he LEDs (figure 15). To use his pin for a rim funcion, he user should se he maximum oupu curren o a value higher han he required curren by a leas 5%. The LED I SET curren is hen rimmed down o he appropriae value. Anoher consideraion ha also is imporan is he limiaion of he user APWM signal duy cycle. In some cases i migh be preferable o se he maximum I SET curren o be 25% o 50% higher, hus allowing he APWM signal o have duy cycles ha are beween 25% and 50%. Err LED (%) Wors-case Typical PWM Duy Cycle, D (%) I OUT (ma) PWM Duy Cycle, D (%) Figure 13. Percenage Error of he LED curren versus PWM duy cycle (a 200 Hz PWM frequency). Figure 15. Oupu curren versus duy cycle; 200 khz APWM signal. APWM A R ISET ISET ISET Curren Mirror Curren Adjus Err LED (%) 10 5 PWM LED Driver PWM Duy Cycle, D (%) Figure 14. Simplified block diagram of he APWM and ISET circui. Figure 16. Percenage Error of he LED curren versus PWM duy cycle; 200 khz APWM signal. 17

18 As an example, a sysem ha delivers a full LED curren of 120 ma per LED would deliver 90 ma of curren per LED when an APWM signal is applied wih a duy cycle of 25% (figures 17 and 18). Alhough he APWM dimming funcion has a wide frequency range, if his funcion is used sricly as an analog dimming funcion i is recommended o use frequency ranges beween 50 and 500 khz for bes accuracy. The frequency range mus be considered only if he user is no using his funcion as a closed loop rim funcion. Anoher limiaion is ha he propagaion delay beween his APWM signal and I OUT akes several milliseconds o change he acual LED curren. This effec is shown in figures I LED I LED APWM APWM Figure 17. Diagram showing he ransiion of LED curren from 120 ma o 90 ma, when a 25% duy cycle signal is applied o he APWM pin; PWM = 1; shows I LED (ch1, 50 ma/div.), APWM (ch2, 5 V/div.), and (ch3, 5 V/div.), ime = 500 µs/div. Figure 18. Diagram showing he ransiion of LED curren from 90 ma o 120 ma, when a 25% duy cycle signal is removed from he APWM pin. PWM = 1; shows I LED (ch1, 50 ma/div.), APWM (ch2, 5 V/div.), and (ch3, 5 V/div.), ime = 500 µs/div. I OUT APWM Figure 19. Transiion of oupu curren level when a 50% duy cycle signal is applied o he APWM pin, in conjuncion wih a 50% duy cycle PWM dimming being applied o he PWM pin; shows I OUT (ch1, 100 ma/div.), APWM (ch2, 5 V/div.), and (ch3, 5 V/div.), ime = 1 ms/div. 18

19 Analog dimming The A8502 can also be dimmed by using an exernal DAC or anoher volage source applied eiher direcly o he ground side of he R ISET resisor or hrough an exernal resisor o he ISET pin (see figure 19). The limi of his ype of dimming depends on he range of he ISET pin. In he case of he A8502 he limi is 40 o 125 µa. For a single resisor (panel A of figure 20), he ISET curren is conrolled by he following formula: I SET = V ISET V DAC R ISET (3) where V ISET is he ISET pin volage and V DAC is he DAC oupu volage. When he DAC volage is 0 V he LED curren will be a is maximum. To keep he inernal gain amplifier sable, he user should no decrease he curren hrough he R ISET resisor o less han 40 µa For a dual-resisor configuraion (panel B of figure 20), he I SET curren is conrolled by he following formula: V ISET V DAC V ISET I SET = R (4) 1 R ISET The advanage of his circui is ha he DAC volage can be higher or lower, hus adjusing he LED curren o a higher or lower value of he prese LED curren se by he R ISET resisor: V DAC = V; he oupu is sricly conrolled by R ISET V DAC > V; he LED curren is reduced V DAC < V; he LED curren is increased LED shor deec Boh LEDx pins are capable of handling he maximum V OUT ha he converer can deliver, hus providing proecion from he LEDx pin o V OUT in he even of a connecor shor. An LEDx pin ha has a volage exceeding V LEDSC will be removed from operaion (see figure 21). This is o preven he IC from dissipaing oo much power by having a large volage presen on an LEDx pin. While he IC is being PWM-dimmed, he IC rechecks he disabled LED every ime he PWM signal goes high, o preven false ripping of an LED shor even. This also allows some self-correcion if an inermien LED pin shor o V OUT is presen. Overvolage proecion The A8502 has overvolage proecion (OVP) and open Schoky diode (D1 in figure 1) proecion. The OVP proecion has a DAC VDAC R ISET A8502 GND ISET GND I OUT (A) LED1 DAC R1 A8502 GND VDAC R ISET ISET GND (B) Figure 20. Simplified diagrams of volage conrol of I LED : ypical applicaions using a DAC o conrol I LED using a single resisor (upper), and dual resisors (lower). Figure 21. Example of he disabling of an LED sring when he LED pin volage is increased above 4.6 V; shows I OUT (ch1, 200 ma/div.), LED1 (ch2, 5 V/div.), and (ch3, 5 V/div.), ime = 10 µs/div. 19

20 defaul level of 8.1 V and can be increased up o 53 V by connecing resisor R OVP beween he OVP pin and V OUT. When he curren ino he OVP pin exceeds 199 μa (ypical), he OVP comparaor goes low and he boos sops swiching. The following equaion can be used o deermine he resisance for seing he OVP level: where: R OVP = ( V OUTovp V OVP(h) ) / I OVPH (5) V OUTovp is he arge overvolage level, R OVP is he value of he exernal resisor, in Ω, V OVP(h) is he pin OVP rip poin found in he Elecrical Characerisics able, and I OVPH is he curren ino he OVP pin. There are several possibiliies for why an OVP condiion would be encounered during operaion, he wo mos common being: a disconneced oupu, and an open LED sring. Examples of hese are provided in figures 22 and 23. Figure 22 illusraes when he oupu of he A8502 is disconneced from load during normal operaion. The oupu volage insanly increases up o OVP volage level and hen he boos sops swiching o preven damage o he IC. If he oupu is drained off, evenually he boos migh sar swiching for a shor duraion unil he OVP hreshold is hi again. Figure 23 displays a ypical OVP even caused by an open LED sring. Afer he OVP condiion is deeced, he boos sops swiching, and he open LED sring is removed from operaion. Aferwards V OUT is allowed o fall, and evenually he boos will resume swiching and he A8502 will resume normal operaion. A8502 also has buil-in secondary overvolage proecion o proec he inernal swich in he even of an open diode condiion. Open Schoky diode deecion is implemened by deecing overvolage on he SW pin of he device. If volage on he SW Oupu disconnec even deeced V OUT V OUT LED sring open condiion deeced SW node SW node PWM PWM I LED I LED Figure 22. OVP proecion in an oupu disconnec even; shows V OUT (ch1, 10 V/div.), SW node (ch2, 50 V/div.), PWM (ch3, 5 V/div.), and I LED (ch4, 200 ma/div.), ime = 1 ms/div. Figure 23. OVP proecion in an open LED sring even; shows V OUT (ch1, 10 V/div.), SW node (ch2, 50 V/div.), PWM (ch3, 5 V/div.), and I LED (ch4, 200 ma/div.), ime = 500 µs/div. 20

21 pin exceeds he device safe operaing volage raing, he A8502 disables and remains lached. To clear his faul, he IC mus be shu down eiher by using he signal or by going below he UVLO hreshold on he VIN pin. Figure 24 illusraes his. As soon as he swich node volage (SW) exceeds 60 V, he IC shus down. Due o small delays in he deecion circui, as well as here being no load presen, he swich node volage will rise above he rip poin volage. Figure 25 illusraes when he A8502 is being enabled during an open diode condiion. The IC goes hrough all of is iniial LED deecion and hen ries o enable he boos, a which poin he open diode is deeced. Open diode condiion deeced PWM SW node V OUT I OUT Figure 24. OVP proecion in an open Schoky diode even, while he IC is in normal operaion; shows PWM (ch1, 5 V/div.), SW node (ch2, 50 V/div.), V OUT (ch3, 20 V/div.), and I OUT (ch4, 200 ma/div.), ime = 1 µs/div. PWM Open diode condiion deeced SW node V OUT I OUT Figure 25. OVP proecion when he IC is enabled during an open diode condiion; shows PWM (ch1, 5 V/div.), SW node (ch2, 50 V/div.), V OUT (ch3, 10 V/div.), and I OUT (ch4, 200 ma/div.), ime = 500 µs/div. 21

22 Boos swich overcurren proecion The boos swich is proeced wih cycle-by-cycle curren limiing se a a minimum of 3.0 A. There is also a secondary curren limi ha is sensed on he boos swich. When deeced his curren limi immediaely shus down he A8502. The level of his curren limi is se above he cycle-by-cycle curren limi o proec he swich from desrucive currens when he boos inducor is shored. Various boos swich overcurren condiions are shown in figures 26 hrough 28. SW node SW node I L I L V OUT V OUT Figure 26. Normal operaion of he swich node (SW); inducor curren (I L ) and oupu volage (V OUT ) for 9 series LEDs in each of 2 srings configuraion; shows SW node (ch1, 20 V/div.), inducor curren, I L (ch2, 1 A/div.), V OUT (ch3, 10 V/div.), and (ch4, 5 V/div.), ime = 2 µs/div. Figure 27. Cycle-by-cycle curren limiing; inducor curren (yellow race, I L ), noe reducion in oupu volage as compared o normal operaion wih he same configuraion (figure 23); shows SW node (ch1, 20 V/div.), inducor curren, I L (ch2, 1 A/div.), V OUT (ch3, 10 V/div.), and (ch4, 5 V/div.), ime = 2 µs/div. FAULT SW node I L Figure 28. Secondary boos swich curren limi; when his limi is hi, he A8502 immediaely shus down; shows (ch1, 5 V/div.), F Ā Ū L T (ch2, 5 V/div.), SW node (ch3, 50 V/div.), and inducor curren, I L (ch4, 2 A/div.), ime = 100 ns/div. 22

23 Inpu overcurren proecion and disconnec swich The primary funcion of he inpu disconnec swich is o proec he sysem and he device from caasrophic inpu currens during a faul condiion. The exernal circui implemening he disconnec is shown in figure 29. If he inpu disconnec swich is no used, he VSENSE pin mus be ied o VIN and he GATE pin mus be lef open. When selecing he exernal PMOS, check for he following parameers: Drain-source breakdown volage V (BR)DSS > 40 V Gae hreshold volage (make sure i is fully conducing a V GS = -4 V, and cu-off a 1 V) R DS(on) : Make sure he on-resisance is raed a V GS = -4.5 V or similar, no a -10 V; derae i for higher emperaure The inpu disconnec swich has wo modes of operaion: 1X mode When he inpu curren is beween one and wo imes he prese curren limi value, he disconnec swich eners a consan-curren mode for a maximum duraion of 10,000 cycles or 5 ms a 2 MHz. During his ime, he Faul flag is se immediaely and he disconnec swich goes ino a linear mode of operaion, in which he inpu curren will be limied o a value approximae o he 1X curren rip poin level (figure 30). If he faul correcs iself before he expiraion of he imer, he Faul flag will be removed and normal operaion will resume. The user can also during his ime decide wheher o shu down he A8502. To immediaely shu down he device, pull he FSET/ SYNC pin low for more han 7 µs. Afer he FSET/SYNC pin has been low for a period longer han 7 µs, he IC will sop swiching, he inpu disconnec swich will open, and he LEDx pins will sop sinking curren. The A8502 can be powered-down ino low power mode. To do so, disable he IC by keeping he pin low for a period of 32,750 clock cycles. To keep he discon- Figure 30. Showing ypical wave forms for a 3-A, 1X curren limi under a faul condiion; shows f SW = 800 khz, F Ā Ū L T (ch1, 5 V/div.), I IN (ch2, 2 A/ div.), GATE (ch3, 5 V/div.), and (ch4, 5 V/div.), ime = 5 ms/div. FAULT I IN GATE (1) Iniial faul deeced (2) Disconnec swich goes ino a linear mode FAULT GATE I IN Faul flag se a 1X rip poin (3) I IN limied o 3 A (4) Afer 12.5 ms, disconnec swich shus down A8502 shus down a 2X rip poin V IN R SC Q1 To L1 R ADJ GATE A8502 Figure 29. Typical circui showing he implemenaion of he inpu disconnec feaure. R C CC VSENSE VIN Figure 31. 2X mode, secondary overcurren faul condiion. I IN is he inpu curren hrough he swich. The Faul flag is se a he 1X curren limi, and when he 2X curren limi is reached he A8502 disables he gae of he disconnec swich (GATE); shows F Ā Ū L T (ch1, 5 V/div.), GATE (ch2, 10 V/div.), I IN (ch3, 2 A/div.), and (ch4, 5 V/div.), ime = 5 µs/div. 23

24 nec swich sable while he disconnec swich is in 1X mode, use a 22 nf capacior for C C and a 20 Ω resisor for R C. 2X curren limi If he inpu curren level goes above 2X of he prese curren limi hreshold, he A8502 will shu down in less han 3 µs regardless of user inpu (figure 31). This is a lached condiion. The Faul flag is also se o indicae a faul. This feaure is mean o preven caasrophic failure in he sysem due o inducor shor o ground, swich pin shor o ground, or oupu shor o ground. Seing he curren sense resisor The ypical hreshold for he curren sense circui is 104 mv, when R ADJ is 0 Ω. This volage can be rimmed by he R ADJ resisor. The ypical 1X rip poin should be se a abou 3 A, which coincides wih he cycle-by-cycle curren limi minimum hreshold. For example, given 3 A of inpu curren, and he calculaed maximum value of he sense resisor, R SC = Ω. The R SC chosen is 0.03 Ω, a sandard. Also: R ADJ = (V SENSETRIP V ADJ ) / I ADJ (6) The rip poin volage is calculaed as: V ADJ = 3.0 A 0.03 Ω = V R ADJ = ( V) / (20.3 µa) = 731 Ω Inpu UVLO When V IN and V SENSE rise above he V UVLOrise hreshold, he A8502 is enabled. A8502 is disabled when V IN falls below he V UVLOfall hreshold for more han 50 μs. This small delay is used o avoid shuing down because of momenary gliches in he inpu power supply. When V IN falls below 4.35 V, he IC will shu down (see figure 32). VDD The VDD pin provides regulaed bias supply for inernal circuis. Connec he capacior C VDD wih a value of 0.1 μf or greaer o his pin. The inernal LDO can deliver no more han 2 ma of curren wih a ypical V DD of abou 3.5 V, enabling his pin o serve as he pull-up volage for he F Ā Ū L T pin. I OUT Figure 32. Shudown showing a falling inpu volage (V IN ); shows V IN (ch1, 2 V/div.), I OUT (ch2, 200 ma/div.), V DD (ch3, 5 V/div.), and (ch4, 2 V/div.), ime = 5 ms/div. V IN V DD GATE I OUT V DD Figure 33. Shudown using he enable funcion, showing he 16 ms delay beween he signal and when he VDD and GATE of he disconnec swich urns off; shows GATE (ch1, 10 V/div.), I OUT (ch2, 200 ma/div.), V DD (ch3, 5 V/div.), and (ch4, 2 V/div.), ime = 5 ms/div. 24

25 Shudown If he pin is pulled low for more han PWML (32,750 clock cycles), he device eners shudown mode and clears all inernal faul regisers. As an example, a a 2 MHz clock frequency, i will ake approximaely 16.3 ms o shu down he IC ino he low power mode (figure 33). When he A8502 is shu down, he IC will disable all curren sources and wai unil he signal goes high o re-enable he IC. If faser shu down is required, he FSET/SYNC pin can be used. Faul proecion during operaion The A8502 consanly moniors he sae of he sysem o deermine if any faul condiions occur during normal operaion. The response o a riggered faul condiion is summarized in he Faul Mode able. The possible faul condiions ha he device can deec are: Open LED pin, LED pin shored o ground, shored inducor, V OUT shor o ground, SW pin shored o ground, ISET pin shored o ground, and inpu disconnec swich source shored o ground. Noe he following: Some of he proecion feaures migh no be acive during sarup, o preven false riggering of faul condiions. Some of hese fauls will no be proeced if he inpu disconnec swich is no being used. An example of his is V OUT shor o ground. Faul Mode Table Faul Name Type Acive Primary swich overcurren proecion (cycle-by-cycle curren limi) Secondary swich curren limi Inpu disconnec curren limi Faul Flag Se Auo-resar Always No Lached Always Yes Lached Always Yes Secondary OVP Lached Always Yes Descripion This faul condiion is riggered by he cycle-bycycle curren limi, I SW(LIM). When he curren hrough he boos swich exceeds secondary curren SW limi (I SW(LIM2) ) he device immediaely shus down he disconnec swich, LED drivers, and boos. The Faul flag is se. To reenable he device, he pin mus be pulled low for 32,750 clock cycles. The device is immediaely shu off if he volage across he inpu sense resisor is 2X he prese curren value. The Faul flag is se. If he inpu curren limi is beween 1X and 2X, he Faul flag is se bu he IC will coninue o operae normally for GFAULT1 or unil i is shu down. To re-enable he device he pin mus be pulled low for 32,750 clock cycles. Secondary overvolage proecion is used for open diode deecion. When diode D1 opens, he SW pin volage will increase unil V OVP(SEC) is reached. This faul laches he IC. The inpu disconnec swich is disabled as well as he LED drivers, and he Faul flag is se. To re-enable he par he PWM pin mus be pulled low for 32,750 clock cycles. Boos Off for a single cycle Disconnec Swich On Sink Driver On Off Off Off Off Off Off Off Off Off Coninued on he nex page 25

26 Faul Mode Table (coninued) Faul Name Type Acive LED Pin Shor Proecion LED Pin open Faul Flag Se Auo-resar Sarup No Auo-resar Normal Operaion No ISET Shor Proecion Auo-resar Always No FSET/SYNC Shor Proecion Overvolage Proecion Auo-resar Always Yes Auo-resar Always No LED Shor Proecion Auo-resar Always No Overemperaure Proecion Auo-resar Always No VIN UVLO Auo-resar Always No Descripion This faul prevens he device from saring-up if eiher of he LEDx pins are shored. The device sops sof-sar from saring while eiher of he LEDx pins are deermined o be shored. Afer he shor is removed, sof-sar is allowed o sar. When an LEDx pin is open he device will deermine which LED pin is open by increasing he oupu volage unil OVP is reached. Any LED sring no in regulaion will be urned off. The device will hen go back o normal operaion by reducing he oupu volage o he appropriae volage level. This faul occurs when he ISET curren goes above 150% of he maximum curren. The boos will sop swiching, he disconnec swich will urn off, and he IC will disable he LED sinks unil he faul is removed. When he faul is removed he IC will ry o o regulae o he prese LED curren. Faul occurs when he FSET/SYNC curren goes above 150% of maximum curren, abou 180 µa. The boos will sop swiching, he disconnec swich will urn off, and he IC will disable he LED sinks unil he faul is removed. When he faul is removed he IC will ry o resar wih sof-sar. Faul occurs when OVP pin exceeds V OVP(h) hreshold. The A8502 will immediaely sop swiching o ry o reduce he oupu volage. If he oupu volage decreases hen he A8502 will resar swiching o regulae he oupu volage. Faul occurs when he LED pin volage exceeds V LEDSC. When he LED shor proecion is deeced he LED sring ha is above he hreshold will be removed from operaion. Faul occurs when he die emperaure exceeds he overemperaure hreshold, 165 C. Faul occurs when V IN drops below V UVLO, 3.90 V maximum. This faul reses all lached fauls. Boos Disconnec Swich Sink driver Off On Off On On Off for open pins. On for all ohers. Off On Off Off Off Off Sop during OVP even. On On On On Off for shored pins. On for all ohers. Off Off Off Off Off Off 26

27 APPLICATION INFORMATION Design Example for Boos Configuraion This secion provides a mehod for selecing componen values when designing an applicaion using he A8502. The resuling design is diagrammed in figure 34. Assumpions: For he purposes of his example, he following are given as he applicaion requiremens: V BAT : 10 o 14 V Quaniy of LED channels, # CHANNELS : 2 Quaniy of series LEDs per channel, # SERIESLEDS : 10 LED curren per channel, I LED : 120 ma LED V f a 120 ma: 3.2 V f SW : 2 MHz T A (max): 65 C PWM dimming frequency: 200 Hz, 1% duy cycle Procedure: The procedure consiss of selecing he appropriae configuraion and hen he individual componen values, in an ordered sequence. Sep 1: Connec LEDs o pins LED1 and LED2. Sep 2: Deermining he LED curren seing resisor R ISET : R ISET = (V ISET A ISET ) / I LED (7) = (1.003 (V) 980) / 120 (ma) = 8.19 kω Choose a 8.25 kω resisor. Sep 3: Deermining he OVP resisor. The OVP resisor is conneced beween he OVP pin and he oupu volage of he converer. Sep 3a: The firs sep is deermining he maximum volage based on he LED requiremens. The regulaion volage, V LED, of he A8502 is 720 mv. A consan erm, 2 V, is added o give margin o he design due o noise and oupu volage ripple. V OUT(OVP) = # SERIESLEDS V f + V LED + 2 (V) (8) = (V) (V) + 2 (V) = V Then he OVP resisor is: R OVP = (V OUT(OVP) V OVP(h) ) / I OVPH (9) = (34.72 V 8.1 V) / 199 µa = kω where boh I OVPH and V OVP(h) are aken from he Elecrical Characerisics able. Chose a value of resisor ha is higher value han he calculaed R OVP. In his case a value of 137 kω was seleced. Below is he acual value of he minimum OVP rip level wih he seleced resisor: V OUT(OVP) = 137 (kω) 199 (µa )+ 8.1 (V) = V Sep 3b: A his poin a quick check mus be done o deermine if he conversion raio is accepable for he seleced frequency. D maxofboos = 1 SWOFFTIME f SW (10) = 1 68 (ns) 2 (MHz) = 86.4% where he minimum off-ime ( SWOFFTIME ) is found in he Elecrical Characerisics able. The Theoreical Maximum V OUT is hen calculaed as: V OUT (max) V IN (min) = 1 D maxofboos V d 10 (V) = 0.4 (V) = V where V d is he diode forward volage. The Theoreical Maximum V OUT value mus be greaer han he value V OUT(OVP). If his is no he case, he swiching frequency of he boos converer mus be reduced o mee he maximum duy cycle requiremens. (11) Sep 4: Selecing he inducor. The inducor mus be chosen such ha i can handle he necessary inpu curren. In mos applicaions, due o sringen EMI requiremens, he sysem mus operae in coninuous conducion mode hroughou he whole inpu volage range. 27

28 Sep 4a: Deermining he duy cycle, calculaed as follows: D(max) = 1 V IN (min) V OUT(OVP) + V d 10 (V) = 1 = (V) (V) 72.04% (12) Sep 4b: Deermining he maximum and minimum inpu curren o he sysem. The minimum inpu curren will dicae he inducor value. The maximum curren raing will dicae he curren raing of he inducor. Firs, he maximum inpu curren, given: I OUT = # CHANNELS I LED (13) = (A) = A hen: I IN (max) = where η is efficiency. V OUT(OVP) VIN (min) (V) I OUT η 240 (ma) = = 10 (V) A Nex, calculae minimum inpu curren, as follows: I IN (min) = V OUT(OVP) V IN (max) (V) I OUT η 240 (ma) = = 14 (V) A A good approximaion of efficiency, η, can be aken from he efficiency curves locaed in he daashee. A value of 90% is a good saring approximaion. Sep 4c: Deermining he inducor value. To ensure ha he inducor operaes in coninuous conducion mode, he value of he inducor mus be se such ha he ½ inducor ripple curren is no greaer han he average minimum inpu curren. As a firs pass assume I ripple o be 40% of he maximum inducor curren: hen: (14) (15) ΔI L = I IN (max) I ripple (16) = 0.94 (A) 0.40 = A L = V IN (min) D(max) ΔI L f SW 10 (V) = 0.72 = 9.57 µh (A) 2 (MHz) (17) Sep 4d: Double-check o make sure he ½ curren ripple is less han I IN (min): I IN (min) > 1 / 2 ΔI L (18) 0.67 A > 0.19 A A good inducor value o use would be 10 µh. Sep 4e: This sep is used o verify ha here is sufficien slope compensaion for he inducor chosen. The slope compensaion value is deermined by he following formula: 3.6 f Slope Compensaion = SW = 3.6 A /µs (19) Nex inser he inducor value used in he design: ΔI Lused = V IN (min) D(max) L used f SW 10 (V) 0.72 = = 10 (µh) 2.0 (MHz) Calculae he minimum required slope: Required Slope (min) = ΔI Lused 1 f SW (1 D(max)) 0.36 A 0.36 (A) 1 10 = 6 = 2.57 A/µs 1 (1 0.72) 2.0 (MHz) (20) (21) If he minimum required slope is greaer han he calculaed slope compensaion, he inducor value mus be increased. Noe: The slope compensaion value is in A/µs, and is a consan muliplier. Sep 4f: Deermining he inducor curren raing. The inducor curren raing mus be greaer han he I IN (max) value plus half of he ripple curren ΔI L, calculaed as follows: L(min) = I IN (max) + 1 / 2 ΔI Lused (22) = 0.94 (A) (A) / 2 = 1.12 A Sep 5: Deermining he resisor value for a paricular swiching frequency. Use he R FSET values shown in figure 7. For example, a 10 kω resisor will resul in a 2 MHz swiching frequency. Sep 6: Choosing he proper swiching diode. The swiching diode mus be chosen for hree characerisics when i is used in LED lighing circuiry. The mos obvious wo are: curren raing of he diode and reverse volage raing. 28