LED System Driver IC ICLS8023Z. Data Sheet. Industrial & Multimarket

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1 LED Sysem Driver IC Off-Line LED Curren Mode Conrollers wih Inegraed 800 V CoolMOS & Sarup Cell Daa Shee Version 1.0, Indusrial & Mulimarke

2 Ediion Published by Infineon Technologies AG Munich, Germany 2011 Infineon Technologies AG All Righs Reserved. Legal Disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office ( Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac he neares Infineon Technologies Office. Infineon Technologies componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.

3 Revision Hisory Page or Iem Subjecs (major changes since previous revision) Version 1.0, Trademarks of Infineon Technologies AG AURIX, C166, CanPAK, CIPOS, CIPURSE, EconoPACK, CoolMOS, CoolSET, CORECONTROL, CROSSAVE, DAVE, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPIM, EiceDRIVER, eupec, FCOS, HITFET, HybridPACK, I²RF, ISOFACE, IsoPACK, MIPAQ, ModSTACK, my-d, NovalihIC, OpiMOS, ORIGA, PRIMARION, PrimePACK, PrimeSTACK, PRO-SIL, PROFET, RASIC, ReverSave, SaRIC, SIEGET, SINDRION, SIPMOS, SmarLEWIS, SOLID FLASH, TEMPFET, hinq!, TRENCHSTOP, TriCore. Oher Trademarks Advance Design Sysem (ADS) of Agilen Technologies, AMBA, ARM, MULTI-ICE, KEIL, PRIMECELL, REALVIEW, THUMB, µvision of ARM Limied, UK. AUTOSAR is licensed by AUTOSAR developmen parnership. Blueooh of Blueooh SIG Inc. CAT-iq of DECT Forum. COLOSSUS, FirsGPS of Trimble Navigaion Ld. EMV of EMVCo, LLC (Visa Holdings Inc.). EPCOS of Epcos AG. FLEXGO of Microsof Corporaion. FlexRay is licensed by FlexRay Consorium. HYPERTERMINAL of Hilgraeve Incorporaed. IEC of Commission Elecroechnique Inernaionale. IrDA of Infrared Daa Associaion Corporaion. ISO of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB of MahWorks, Inc. MAXIM of Maxim Inegraed Producs, Inc. MICROTEC, NUCLEUS of Menor Graphics Corporaion. Mifare of NXP. MIPI of MIPI Alliance, Inc. MIPS of MIPS Technologies, Inc., USA. muraa of MURATA MANUFACTURING CO., MICROWAVE OFFICE (MWO) of Applied Wave Research Inc., OmniVision of OmniVision Technologies, Inc. Openwave Openwave Sysems Inc. RED HAT Red Ha, Inc. RFMD RF Micro Devices, Inc. SIRIUS of Sirius Saellie Radio Inc. SOLARIS of Sun Microsysems, Inc. SPANSION of Spansion LLC Ld. Symbian of Symbian Sofware Limied. TAIYO YUDEN of Taiyo Yuden Co. TEAKLITE of CEVA, Inc. TEKTRONIX of Tekronix Inc. TOKO of TOKO KABUSHIKI KAISHA TA. UNIX of X/Open Company Limied. VERILOG, PALLADIUM of Cadence Design Sysems, Inc. VLYNQ of Texas Insrumens Incorporaed. VXWORKS, WIND RIVER of WIND RIVER SYSTEMS, INC. ZETEX of Diodes Zeex Limied. Las Trademarks Updae Daa Shee 3 Version 1.0,

4 Table of Conens Table of Conens Table of Conens Lis of Figures Lis of Tables Curren Mode Conroller wih Inegraed 800 V Sarup Cell/Depleion CoolMOS Pin Configuraion and Funcionaliy Pin Configuraion for PG-DIP PG-DIP-7 Package Pin Funcionaliy Block Diagram Funcional Descripion Inroducion Power Managemen Improved Curren Mode PWM-OP PWM Comparaor Sarup Phase PWM Secion Oscillaor PWM Lach FF Gae Driver Curren Limiing Leading Edge Blanking Propagaion Delay Compensaion (paened) Conrol Uni Basic and Exendable Blanking Mode Floaing Load Proecion (FLP) Proecion Modes Vcc OVP, OTP, Exernal Proecion Enable and Vcc Undervolage Overload Proecion, Open Loop Proecion Elecrical Characerisics Absolue Maximum Raings Operaing Range Characerisics Supply Secion Inernal Volage Reference PWM Secion Sof Sar Time Conrol Uni Curren Limiing CoolMOS Secion CoolMOS Performance Characerisic Inpu Power Curve Ouline Dimensions Ouline Dimensions of PG-DIP Marking Daa Shee 4 Version 1.0,

5 Lis of Figures Lis of Figures Figure 1 Typical applicaion of conrollers Figure 2 Pin configuraion of PG-DIP-7 (op view) Figure 3 Block diagram of conrollers Figure 4 Power managemen of conrollers Figure 5 Curren Mode Figure 6 Pulse Widh Modulaion Figure 7 Improved Curren Mode Figure 8 Ligh Load Condiions Figure 9 PWM Conrolling Figure 10 Sof Sar Figure 11 Sof Sar Phase Figure 12 Sof Sar Circui Figure 13 Gae Drive Signal in he Sof Sar Phase Figure 14 Sar-Up Phase Figure 15 PWM Secion Block Figure 16 Gae Driver Figure 17 Gae Rising Slope Figure 18 Curren Limiing Block Figure 19 Leading Edge Blanking Figure 20 Curren Limiing Figure 21 Overcurren Shudown Figure 22 Dynamic Volage Threshold V csh Figure 23 Basic and Exendable Blanking Mode Figure 24 Waveform a Exended Blanking Time Figure 25 Signals in FLP Mode Figure 26 Odd Skip Auo Resar Waveform Figure 27 Nonswich Auo Resar Waveform Figure 28 Vcc OVP, OTP, Exernal Proecion Enable Figure 29 Overload Proecion, Open Loop Proecion Figure 30 Safe Operaing Area (SOA) curve for conrollers Figure 31 SOA emperaure deraing coefficien curve Figure 32 Power dissipaion; P o =f(t a ) Figure 33 Drain-source breakdown volage; V BR(DSS) = f(t j ), I D = 0.25 ma Figure 34 Inpu power curve Vin = 85~265 Vac; P in = f(t a ) Figure 35 Inpu power curve Vin = 230 Vac ± 15 %; P in = f(t a ) Figure 36 PG-DIP-7 (Pb-free lead plaing plasic dual inline ouline) Figure 37 Marking for Daa Shee 5 Version 1.0,

6 Lis of Tables Lis of Tables Table 1 Pin Configuraion for PG-DIP Daa Shee 6 Version 1.0,

7 Curren Mode Conroller wih Inegraed 800 V Sarup Cell/Depleion CoolMOS Produc Highlighs 800 V avalanche-rugged CoolMOS wih sarup cell Adjusable blanking window for high-load jumps o increase reliabiliy Frequency jiering and sof driving for low EMI Auo Resar proecion for overload, overemperaure, overvolage and undervolage Pb-free lead plaing, RoHS-compilan Feaures 800 V avalanche-rugged CoolMOS wih sarup cell 65 khz inernally-fixed swiching frequency wih jiering feaure Auo Resar mode for overemperaure deecion Auo Resar mode for overvolage deecion Auo Resar mode for overload and open loop Auo Resar mode for VCC undervolage Floaing Load Proecion (FLP) mode in he case of open loads Exernal auo-resar enable pin Overemperaure proecion wih 50 C hyseresis Buil-in 10 ms sof sar Buil-in 20 ms and exendable blanking ime for shor duraion peak power Propagaion delay compensaion for boh maximum load and burs mode Overall olerance of curren limiing < ± 5 % Inernal leading edge blanking BiCMOS echnology for low power consumpion and wide VCC volage range Sof gae drive wih 50 Ω urn-on resisor Daa Shee 7 Version 1.0,

8 Descripion conrollers employ a fixed-frequency operaion mode opimized for offline LED lighing. The inegraed consan power funcion (paened by Infineon Techologies AG) and he frequency jier enable high performance wihou invesmen of oo much effor in sabilizaion of he sysem and filering in erms of EMC. A wide VCC range up o 26 V is provided by use of BiCMOS echnology o cover changes in he auxiliary supply volage if a CV/CC regulaion is implemened on he secondary side. Auo Resar Mode is enered in he case of overemperaure, VCC overvolage, oupu open loop or overload and VCC undervolage. If an open load even occurs, he device eners he so-called Floaing Load Proecion (FLP) mode o proec he LED agains desrucion. The dimensions of he ransformer and he secondary diode can be reduced owing o he inernal precise peak curren limiaion o yield greaer cos efficiency. 24V/350mA L1 7 VCC 4 D 5 D 1 BA 2 FB PWM Conrol 8 GND 3 CS Figure 1 Typical applicaion of conrollers Type Package Marking V DS F OSC 1) R DSon 230VAC ±15% 2) 110VAC±15% 2) PG-DIP V 65 khz 2.26 Ω 24 W 12 W 1) T = 25 C 2) Calculaed maximum inpu power raing a T a = 80 C, T j = 125 C and wihou copper area as hea sink Daa Shee 8 Version 1.0,

9 Pin Configuraion and Funcionaliy 1 Pin Configuraion and Funcionaliy 1.1 Pin Configuraion for PG-DIP-7 Table 1 Pin Configuraion for PG-DIP-7 Pin Symbol Funcion 1 BA Exended blanking ime & auo-resar enable 2 FB Feedback 3 CS Curren Sense / 800 V 1) depleion CoolMOS source 4 n.c. No conneced 5 Drain 800 V 1) CoolMOS drain 6 No pin 7 VCC Conroller supply volage 8 GND Conroller ground T j = 110 C 1.2 PG-DIP-7 Package BA 1 8 GND FB 2 7 VCC CS 3 n.c. 4 5 Drain Figure 2 Pin configuraion of PG-DIP-7 (op view) Daa Shee 9 Version 1.0,

10 Pin Configuraion and Funcionaliy 1.3 Pin Funcionaliy BA (exended blanking ime & auo-resar enable) The BA pin combines he funcions of exendable blanking ime for overload proecion and he exernal auoresar enable. The exendable blanking ime funcion is o exend he buil-in 20 ms blanking ime for overload proecion by adding an exernal capacior o ground. The exernal auo-resar enable funcion is an exernal access o sop he gae swiching and force he IC o ener auo-resar mode. I is riggered by pulling he pin volage o less han 0.4 V. FB (feedback) The informaion on he regulaion is provided by he FB pin o he inernal proecion uni and o he inernal PWM comparaor o conrol he duy cycle. In he even of an open load even, he device eners he Floaing Load Proecion (FLP) mode. CS (curren sense) The curren sense pin senses he volage developed on he series resisor insered ino he source of he inegraed depleion CoolMOS. If CS reaches he inernal hreshold of he curren limi comparaor, he driver oupu is immediaely swiched off. The curren informaion is provided o he PWM comparaor o realize he curren mode. Drain (drain of inegraed depleion CoolMOS ) The drain pin provides he connecion o he drain of he inernal depleion CoolMOS. VCC (power supply) The VCC pin is he posiive supply of he IC. The operaing range of he supply is beween 10.5 V and 25 V. GND (ground) The GND pin is he common ground of he conroller. Daa Shee 10 Version 1.0,

11 Block Diagram 2 Block Diagram Vcc DRAIN Power Managemen 5 V Conrol UNIT Inernal BIAS Volage Reference Sarup Cell Auo Resar FLP Power Down Rese UVLO GND BA PROTECTION OTP OVP OCP OLP Sof Sar Gae Drive Curren Mode Conrol PWM Comparaor Propagaion Delay Compensaion Leading Edge Blanking CS FB Figure 3 Block diagram of conrollers Daa Shee 11 Version 1.0,

12 Funcional Descripion 3 Funcional Descripion All values used in he funcional descripion are ypical values. When calculaing he wors cases, he minimium/maximum values lised in Elecrical Characerisics on page 32 have o be considered. 3.1 Inroducion For conrollers, a high volage sarup cell is inegraed ino he sysem IC, which is swiched off once he undervolage lockou-on hreshold of 17 V is exceeded. This sarup cell is par of he inegraed depleion CoolMOS. The exernal sarup resisor is no longer necessary as he sarup cell is conneced o he drain, resuling in reduced power losses. This increases he efficiency under ligh load condiions drasically. The sof sar capacior is also used for providing an adjusable blanking window for high load jumps. The overload deecion funcion is disabled during his window. Wih his concep, no furher exernal componens are necessary o adjus he blanking window. An Auo Resar mode is implemened in he IC o reduce he average power conversion in he even of malfuncion or unsafe operaing condiions in he LED drives. This feaure increases he sysem s robusness and safey, which would oherwise lead o a desrucion of he LED drive. Once he malfuncion is correced, normal operaion is auomaically iniiaed afer he nex sarup phase. Togeher wih he sof sar capacior, he feedback can also sense a missing load, which leads o rising oupu and auxiliary volages. This riggers he Floaing Load Proecion (FLP) mode. When feedback falls below 1.35 V, he Sof Sar volage begins o rise up o a hreshold of 4 V (depends on he C4 value) and he IC is swiched ino FLP mode. The precise inernal peak curren limiaion reduces he coss for he ransformer and he secondary diode. The influence of he change in he inpu volage on he power limiaion can be avoided ogeher wih he inegraed Propagaion Delay Compensaion circui. Consequenly, he maximum power is pracically independen of he inpu volage required for wide range LED drives. There is no need for addiional oversizing of he LED drives e.g., for he ransformer or he secondary diode. Daa Shee 12 Version 1.0,

13 Funcional Descripion 3.2 Power Managemen Drain VCC Sarup Cell CoolMOS Power Managemen Inernal Bias Undervolage Lockou 17V 10.5V Power-Down Rese Volage Reference 5.0V Sof Sar block Auo Resar Mode Floaing Load Proecion Figure 4 Power managemen of conrollers The undervolage lockou funcion moniors he exernal supply volage V VCC. When he LED drive is conneced o he main line, he inernal sarup cell is biased and sars o charge he exernal capacior C VCC, which is conneced o he VCC pin. The VCC charge curren ha is provided by he sarup cell from he drain pin is 0.9 ma. If V VCC exceeds he on-hreshold V CCon (= 17 V), he bias circui is swiched on. Then he sarup cell is swiched off by he undervolage lockou; herefore no power losses are presen due o he connecion of he sarup cell o he drain volage. An hyseresis loop is implemened o avoid unconrolled ringing a swich-on. Swich-off of he conroller can only ake place afer he acive mode has been enered and V VCC has fallen below 10.5 V. The maximum curren consumpion before he conroller is acivaed is abou 200 µa. If V VCC falls below he off-hreshold V CCoff (= 10.5 V), he bias circui is swiched off and he sof sar couner is rese. This ensures in every sarup cycle ha he sof sar begins a zero. The bias circui is swiched off if Auo Resar mode is enered. The curren consumpion is hen reduced o 320 µa. Once he malfuncion condiion is resolved, his block will hen urn back on. The recovery from Auo Resar mode does no require disconnecion of he LED drive from he AC line. When Floaing Load Proecion (LFP) is enered, he inernal bias is swiched off mos of he ime bu he volage reference is kep alive in order o reduce he curren consumpion below 620 µa. Daa Shee 13 Version 1.0,

14 Funcional Descripion 3.3 Improved Curren Mode Sof-Sar Comparaor FB C8 PWM Lach R Q Driver S Q 0.6V PWM OP x3.25 Improved Curren Mode CS Figure 5 Curren Mode Curren Mode means he duy cycle is conrolled by he slope of he primary curren. This is done by comparing he FB signal wih he amplified curren sense signal. Amplified Curren Signal FB 0.6V Driver on Figure 6 Pulse Widh Modulaion If he amplified curren sense signal exceeds he FB signal, he on-ime on of he driver is finished by reseing he PWM lach (Figure 6). The primary curren is sensed by he exernal series resisor R Sense insered in he source of he inegraed CoolMOS. By means of curren mode regulaion, he secondary oupu volage is insensiive o he line variaions. The curren waveform slope will change wih he line variaion, which conrols he duy cycle. The exernal R Sense allows individual adjusmen of he maximum source curren of he inegraed CoolMOS. Daa Shee 14 Version 1.0,

15 Funcional Descripion To improve he curren mode during ligh load condiions he amplified curren ramp of he PWM-OP is superimposed on a volage ramp, which is buil by he swich T2, he volage source V1 and a resisor R1 (see Figure 7). Every ime he oscillaor shus down for maximum duy cycle limiaion he swich T2 is closed by V OSC. When he oscillaor riggers he gae driver, T2 is opened so ha he volage ramp can sar. Sof-Sar Comparaor PWM Comparaor FB C8 PWM Lach Oscillaor V OSC ime delay circui (156 ns ) T 2 R 1 0.6V 10kΩ V 1 Gae Driver X3.25 PWM OP Volage Ramp Figure 7 Improved Curren Mode In he case of ligh loads he amplified curren ramp is oo small o ensure sable regulaion. In such cases he volage ramp is a well-defined signal for he comparison wih he FB signal. The duy cycle is hen conrolled by he slope of he volage ramp. By means of he ime delay circui which is riggered by he invered V OSC signal, he gae driver is swiched off unil i reaches approximaely a 156 ns delay ime (Figure 8). I allows he duy cycle o be reduced coninuously o 0 % by decreasing V FB below ha hreshold. V OSC max. Duy Cycle Volage Ramp 0. 6V FBB Gae Driver 156ns ime delay Figure 8 Ligh Load Condiions Daa Shee 15 Version 1.0,

16 Funcional Descripion PWM-OP The inpu of he PWM-OP is applied over he inernal leading edge blanking o he exernal sense resisor R Sense conneced o he CS pin. R Sense convers he source curren ino a sense volage. The sense volage is amplified wih a gain of 3.25 by he PWM-OP. The oupu of he PWM-OP is conneced o he volage source V1. The volage ramp wih he superimposed amplified curren signal is fed ino he posiive inpus of he PWM comparaor C8 and he sof sar comparaor (Figure 9) PWM Comparaor The PWM comparaor compares he sensed curren signal of he inegraed CoolMOS wih he feedback signal V FB (Figure 9). V FB is creaed by an exernal opocoupler or exernal ransisor in combinaion wih he inernal pullup resisor R FB and provides he load informaion of he feedback circuiry. When he amplified curren signal of he inegraed CoolMOS exceeds he signal V FB he PWM comparaor swiches off he gae driver. 5V R FB Sof-Sar Comparaor FB C8 PWM Lach PWM Comparaor Opocoupler 0.6V PWM OP X3.25 CS Improved Curren Mode Figure 9 PWM Conrolling Daa Shee 16 Version 1.0,

17 Funcional Descripion Sarup Phase In he sarup phase, he IC provides a sof sar period o conrol he primary curren by means of a duy cycle limiaion. The sof sar funcion is a buil-in funcion and i is conrolled by an inernal couner. Sof Sar couner Sof Sar finish SofS C7 Sof Sar Sof Sar Sof-Sar Comparaor & Gae Driver G7 0.6V PWM OP x3.25 CS Figure 10 Sof Sar When he V CC exceeds he on-hreshold volage, he IC sars he sof sar mode (Figure 11). Figure 11 Sof Sar Phase Daa Shee 17 Version 1.0,

18 Funcional Descripion The funcion is realized by an inernal sof sar resisor, a curren sink and a couner. The ampliude of he curren sink is conrolled by he couner (Figure 12). Figure 12 Sof Sar Circui Afer he IC is swiched on, he V SofS volage is conrolled such ha he volage is increased sep-by-sep (in 32 seps) wih he increase of he couns. The sof sar couner sends a signal o he curren sink conrol every 300 µs so ha he curren sink decreases gradually and he duy raio of he gae drive increases gradually. The sof sar is finished in 10 ms ( Sof-Sar ) afer he IC is swiched on. A he end of he sof sar period, he curren sink is swiched off. Wihin he sof sar period, he duy cycle increases from zero o maximum gradually (see Figure 13). Figure 13 Gae Drive Signal in he Sof Sar Phase In addiion o sar-up, sof sar is also acivaed a each resar aemp during auo resar. Daa Shee 18 Version 1.0,

19 Funcional Descripion V SofS Sof-Sar V SOFTS32 V FB 4.5V V OUT V OUT Sar-Up Figure 14 Sar-Up Phase The sar-up ime Sar-Up before he converer oupu volage V OUT is seled mus be shorer han he sof sar phase Sof-Sar (Figure 14). Sof sar allows effecive minimizaion of curren and volage sresses on he inegraed CoolMOS, he clamp circui and he oupu recifier and i helps o preven sauraion of he ransformer during sar-up. Daa Shee 19 Version 1.0,

20 Funcional Descripion 3.4 PWM Secion Figure 15 PWM Secion Block Oscillaor The oscillaor generaes a fixed frequency of 65 khz wih frequency jiering of ± 4 % (which is ± 2.6 khz) a a jiering period of 4 ms. A capacior, a curren source and curren sink which deermine he frequency are inegraed. The charging and discharging curren of he implemened oscillaor capacior are inernally rimmed in order o achieve a very accurae swiching frequency. The raio of conrolled charge o discharge curren is adjused o reach a maximum duy cycle limiaion of D max =0.75. Daa Shee 20 Version 1.0,

21 Funcional Descripion Once he sof sar period is over and when he IC goes ino normal operaing mode, he swiching frequency of he clock is varied by he conrol signal from he sof sar block. Then he swiching frequency is varied in he range of 65 khz ± 2.6 khz a period of 4 ms PWM Lach FF1 The oupu of he oscillaor block provides coninuous pulses o he PWM lach, which urns on/off he inegraed CoolMOS. Afer he PWM lach is se, i is rese by he PWM comparaor, he sof sar comparaor or he curren limi comparaor. When i is in rese mode, he oupu of he driver is shu down immediaely Gae Driver VCC PWM Lach 1 50Ω Gae CoolMOS Gae Driver Figure 16 Gae Driver The driver sage is opimized o minimize EMI and o provide high circui efficiency. This is done by reducing he swich-on slope when exceeding he inegraed CoolMOS hreshold. This is achieved by a slope conrol of he rising edge a he driver s oupu (Figure 17) and adding a 50 Ω gae urn-on resisor (Figure 16). Thus he leading swich-on spike is minimized. (inernal) V Gae yp. = 160 ns 4.6V Figure 17 Gae Rising Slope Furhermore he driver circui is designed o eliminae cross conducion of he oupu sage. Daa Shee 21 Version 1.0,

22 Funcional Descripion During power-up, when V CC is below he undervolage lockou hreshold V VCCoff, he oupu of he gae driver is se o low in order o disable power ransfer o he secondary side. 3.5 Curren Limiing A cycle-by-cycle peak curren limiing operaion is realized by he curren limi comparaor C10. The source curren of he inegraed CoolMOS is sensed via an exernal sense resisor R Sense. By means of R Sense he source curren is ransformed o a sense volage V Sense, which is fed o he pin CS. If he volage V Sense exceeds he inernal hreshold volage V csh, he comparaor C10 immediaely urns off he gae drive by reseing he PWM lach FF1. PWM Lach FF1 Curren Limiing Propagaion Delay Compensaion PWM-OP & G10 C10 C12 V csh LEB 220ns LEB 180ns S4 V CSh_burs Floaing Load Proecion Propagaion Delay Compensaion Burs or G13 V FB_burs C5 10k D1 1pF FB CS Figure 18 Curren Limiing Block Propagaion delay compensaion is added o suppor he immediae shudown of he inegraed CoolMOS wih very shor propagaion delay. Thus he influence of he AC inpu volage on he maximum oupu power can be reduced o a minimu. This compensaion applies o boh he peak load and burs mode. In order o preven he curren limi from disorions caused by leading edge spikes, Leading Edge Blanking (LEB) is inegraed ino he curren sense pah for he comparaors C10, C12 and he PWM-OP. The oupu of comparaor C12 is acivaed by he gae G10 if he FLP is enered. When i is acivaed, he curren limiing is reduced o V csh_flp. This volage level deermines he maximum power level in Floaing Load Proecion mode Leading Edge Blanking Whenever he inegraed CoolMOS is swiched on, a leading edge spike is generaed due o he primary-side capaciances and reverse recovery ime of he secondary-side recifier. This spike can cause he gae drive o swich off uninenionally. In order o avoid premaure erminaion of he swiching pulse, his spike is blanked ou wih a ime consan of LEB = 220 ns for normal load and LEB = 180 ns for FLP mode. Daa Shee 22 Version 1.0,

23 Funcional Descripion V Sense V csh LEB = 220ns /180ns Figure 19 Leading Edge Blanking Propagaion Delay Compensaion (paened) In he case of overcurren deecion, here is always propagaion delay o swich off he inegraed CoolMOS. An overshoo of he peak curren I peak is induced o he delay, which depends on he raio of di/d of he peak curren (Figure 20). Figure 20 Curren Limiing The overshoo of Signal2 is larger han of Signal1 due o he seeper rising waveform. This change in he slope depends on he AC inpu volage. Propagaion Delay Compensaion is inegraed o reduce he overshoo due o di/d of he rising primary curren. Thus he propagaion delay ime beween exceeding he curren sense hreshold V csh and he swiching-off of he inegraed CoolMOS is compensaed over emperaure wihin a wide inpu range. Curren limiing is hen very accurae. For example, I peak = 0.5 A wih R Sense = 2. The curren sense hreshold is se o a saic volage level V csh =1V wihou Propagaion Delay Compensaion. A curren ramp of di/d = 0.4 A/µs, or dv Sense /d = 0.8 V/µs, and a propagaion delay ime of Propagaion Delay = 180 ns leads o an I peak overshoo of 14.4 %. Wih he propagaion delay compensaion, he overshoo is only around 2 % (Figure 21). Daa Shee 23 Version 1.0,

24 Funcional Descripion Figure 21 Overcurren Shudown The Propagaion Delay Compensaion is realized by means of a dynamic hreshold volage V csh (Figure 22). In case of a seeper slope he swich-off of he driver is earlier o compensae he delay. V OSC max. Duy Cycle off ime V Sense Propagaion Delay V csh Signal1 Signal2 Figure 22 Dynamic Volage Threshold V csh Daa Shee 24 Version 1.0,

25 Funcional Descripion Similarly, he same concep of propagaion delay compensaion is also implemened in FLP mode wih a reduced level, V csh_flp (Figure 18). Wih his implemenaion, he enry and exi FLP mode power can be very close beween low line and high line inpu volage. 3.6 Conrol Uni The Conrol Uni conains he funcions for Floaing Load Proecion (FLP) mode and Auo Resar mode. The FLP mode and he Auo Resar mode boh have 20 ms inernal blanking imes. For he overload Auo Resar mode, he 20 ms blanking ime can be furher exended by adding an exernal capacior a he BA pin. Wih he blanking ime, he IC avoids enering ino hose wo modes accidenally. This buffer ime is very useful for he applicaion, which works in shor duraions of peak power occasionally Basic and Exendable Blanking Mode 5.0V I chg_eb Auo Resar Mode R BO2 # C BK BA S1 4.5V 500Ω 0.9V C11 C3 Couner CT1 Spike Blanking 30us & G5 S2 FB 4.5V C4 20ms Blanking Time Conrol Uni Figure 23 Basic and Exendable Blanking Mode There are 2 kinds of blanking mode: basic mode and he exendable mode. The basic mode is a buil-in 20 ms blanking ime while he exendable mode can exend his blanking ime by connecing an exernal capacior o he BA pin. For he exendable mode, he gae G5 remains blocked even hough he 20 ms blanking ime is reached. Afer reaching he 20 ms blanking ime he couner is acivaed and he swich S1 is urned on o charge he volage of he BA pin by he consan curren source, I chg_eb. When he volage of he BA pin his 4.5 V, which is sensed by he comparaor C11, he couner will increase he couner by 1. Then i swiches off he swich S1 and urns on he swich S2. The volage a he BA pin will be discharged hrough a 500 Ω resisor. When he volage drops o 0.9 V, which is sensed by he comparaor C3, he swich S2 will be urned off and he swich S1 will be urned on. Then he consan curren I chg_eb will charge he C BK capacior again. When he volage a BA his 4.5 V, which is sensed by comparaor C11, he couner will increase he coun o 2. The process repeas unil i reaches a oal coun of 256 (Figure 23). Then he couner will release a high oupu signal. When he AND gae G5 deecs boh Daa Shee 25 Version 1.0,

26 Funcional Descripion high signals a he inpus, i will acivae he 30 ms spike blanking circui and finally he Auo Resar mode will be acivaed. 4.5V 256 couns V BA normal operaion 0.9V exended blanking ime auo resar Figure 24 Waveform a Exended Blanking Time For example, if C BK = 0.1 µf, I chg_eb = 720 µa Exended blanking ime = 256*(C BK *(4.5V-0.9V)/I chg_eb + C BK *500*ln(4.5/0.9)) = ms Toal blanking ime = 20 ms ms = ms If here is a resisor R BO2 conneced o he BA pin, he effecive charging curren will be reduced. The blanking ime will be increased. For example, if C BK = 0.1 µf, I chg_eb =720 µa, R BO2 = 12.8 KΩ, I chg_eb = I chg_eb -(4.5 V+0.9 V)/(2*R BO2 ) = 509 µa Exended blanking ime = 256*(C BK *(4.5V-0.9V)/I chg_eb + C BK *500*ln(4.5/0.9)) = 201.6ms Toal blanking ime = 20 ms = ms where I chg_eb =ne charging curren o C BK Daa Shee 26 Version 1.0,

27 Funcional Descripion Floaing Load Proecion (FLP) The circui sars up as usual, bu a missing load leads o a rise in he oupu and auxiliary volages. Reaching he VCC hreshold of 24.5 V (volage divider RD2/R4 and Q2) leads o a reducion in he feedback volage and hence o reduced oupu curren pulses in order o keep he oupu volage below he maximum raing of he componens. If he feedback level falls below 1.35 V, he Sof Sar volage begins o rise up o a hreshold of 4 V (depends on he C4 value) and he IC is swiched ino he FLP mode. V FB 4.0V 3.5V 3.2V Enering FLP Mode Leaving FLP Mode V FB_FLP Blanking Timer 20ms Blanking Time V CS V csh Curren limi level during FLP Mode V csh_flp V VCC 10.5V I VCC 3.4mA 620uA V OUT Figure 25 Signals in FLP Mode Daa Shee 27 Version 1.0,

28 Funcional Descripion Proecion Modes The IC provides Auo Resar mode as he major proecion feaure. Auo Resar mode can preven desrucion of he LED. There are 2 kinds of auo resar mode: odd skip auo resar mode and non swich auo resar mode. Odd skip auo resar mode is provided so here is no deecion of fauls and no swiching pulse for he odd number resar cycle. On even numbers of resar cycles he faul deec and sof sar swiching pulses are mainained. If he faul persiss, i coninues he Auo Resar mode. However, if he faul is removed, i can release o normal operaion only on he even number auo resar cycle (Figure 26). V VCC Faul deeced No deec Sarup and deec No deec 17V 10.5V V CS Figure 26 Odd Skip Auo Resar Waveform Nonswich auo resar mode is similar o odd skip auo resar mode excep he sar-up swiching pulses are also suppressed on he even number of he resar cycle. The deecion of fauls sill remains on even numbers of he resar cycle. When he faul is removed, he IC will resume normal operaion on he even number of he resar cycle (Figure 27). V VCC Faul deeced No deec Sarup and deec No deec 17V 10.5V V CS No swiching Figure 27 Nonswich Auo Resar Waveform The main purpose of he odd skip auo resar is o exend he resar ime so ha he power loss during auo resar proecion can be reduced. This feaure is paricularly good for smaller Vcc capaciors where he resar ime is shorer. The following able liss he possible sysem failures and he corresponding proecion modes: Daa Shee 28 Version 1.0,

29 Funcional Descripion VCC overvolage (1) VCC overvolage (2) Overload Open loop VCC undervolage Shor opocoupler Overemperaure Exernal proecion enable Odd skip auo resar mode Odd skip auo resar mode Odd skip auo resar mode Odd skip auo resar mode Nonswich auo resar mode Nonswich auo resar mode Nonswich auo resar mode Nonswich auo resar mode Vcc OVP, OTP, Exernal Proecion Enable and Vcc Undervolage There are 2 ypes of Vcc overvolage proecion: Vcc OVP (1) and Vcc OVP (2). The Vcc OVP (1) akes acion only during he sof sar period. The Vcc OVP (2) akes acion in any condiion. Auoresar Enable Signal BA T AE 0.4V 25.5V C9 C2 Thermal Shudown T j >130 C 120μs blanking ime Sop gae drive Spike Blanking 30μs Auo Resar Mode Rese V VCC < 10.5V Auo Resar mode VCC 20.5V C1 & Volage Reference FB 4.5V C4 G1 Conrol Uni sofs_period Figure 28 Vcc OVP, OTP, Exernal Proecion Enable Vcc OVP (1) condiion is when V VCC volage is > 20.5 V, V FB volage is > 4.5 V and during he sof sar period, he IC eners ino odd skip auo resar mode. This condiion likely happens during sar-up on an open loop faul (Figure 28). Vcc OVP (2) condiion is when V VCC volage is > 25.5 V, he IC eners ino odd skip auo resar mode (Figure 28). The overemperaure proecion OTP is sensed inside he conroller IC. The Thermal Shudown block keeps on monioring he juncion emperaure of he conroller. Afer deecing a juncion emperaure higher han 130 C, he IC will ener ino he nonswich auo resar mode. The IC is also implemened wih a 50 C hyseresis. This means he IC can only be recovered when he conroller juncion emperaure is dropped 50 C lower han he overemperaure rigger poin (Figure 28). The exernal auo resar enable feaure can provide flexibiliy o a cusomer s self-defined proecion feaure. This funcion can be riggered by pulling down he V BA volage o < 0.4 V. Or i can simply rigger he base pin of an Daa Shee 29 Version 1.0,

30 Funcional Descripion exernal ransisor, T AE a he BA pin. When his funcion is enabled, i will ener ino he nonswich auo resar mode. The gae drive is sopped and here is no swiching pulse before i is recovered (Figure 28). The Vcc undervolage and shor opo-coupler will go ino he nonswich auo resar mode inherenly. In he case of V CC undervolage, he V CC volage drops indefiniely. When i drops below he V CC undervolage lockou OFF volage (10.5 V), he IC will urn off he IC and he sarup cell will urn on again. Then he V CC volage will be charged up o UVLO ON volage (17 V) and he IC urns on again provided he sarup cell charge-up curren is no drained by he faul. If he faul is no removed, he V CC will coninue o drop unil i his UVLO OFF volage and he resar cycle repeas. Shor opocoupler can lead o V CC undervolage because once he opocoupler (ransisor side) is shored, he feedback volage will drop o zero and here will be no swiching pulse. Then he V CC volage will drop he same as he V CC undervolage Overload Proecion, Open Loop Proecion In overload or open loop cases, he V FB volage exceeds 4.5 V, which will be observed by comparaor C4. Then he buil-in blanking ime couner sars o coun. When i reaches 20 ms, he exended blanking ime couner CT1 is acivaed. The swich S2 is urned on and he volage a he BA pin will be discharged hrough a 500 Ω resisor. When i drops o 0.9 V, he swich S2 is urned off and he swich S1 is urned on. Then a consan curren source I chg_eb will sar o charge up he BA pin. When he volage his 4.5 V, which is moniored by he comparaor C11, he swich S1 is urned off and he coun will increase by 1. Then he swich S2 will urn on again and he volage will drop o 0.9 V and rise o 4.5 V again. The coun will hen increase by 1 again. When he oal coun reaches 256, he couner CT1 will sop and i will release a high oupu signal. When boh he inpu signals a AND gae G5 is high, he odd skip auo resar mode is acivaed afer he 30 µs spike blanking ime (Figure 29). 5. 0V Volage Reference S1 I chg_eb Auo Resar Mode Rese V VCC < 10.5V Auo Resar Mode R BO2 # C BK BA 4.5V C11 couner 500 Ω CT1 C3 0.9V Spike Blanking 30us S2 & G5 FB 4. 5V C4 20ms Blanking Time Conrol Uni Figure 29 Overload Proecion, Open Loop Proecion The oal blanking ime depends on he addiion of he buil-in and he exended blanking ime. If here is no C BK capacior a he BA pin, he coun will finish wihin 0.1 ms and he equivalen blanking ime is jus he buil-in ime Daa Shee 30 Version 1.0,

31 Funcional Descripion of 20 ms. However, if he C BK capacior is big enough, i can be as long as 1 s. If C BK is 0.1 µf and I chg_eb is 720 µa, he exendable blanking ime is around ms and he oal blanking ime is ms. Since he BA pin is a mulifuncion pin, i can share wih differen funcions. The resisor R BO2 may however affec he exendable blanking ime (Figure 29). Thus i should consider R BO2 in he calculaion of he exendable blanking ime. For example, he exended blanking ime may be changed from ms o ms for cases wih and wihou 12.8 KΩ R BO2 resisor. The lis below shows one paricular C BK, R BO2 vs blanking ime. C BK RBO2 Exended blanking ime Overall blanking ime 0.1 µf ms ms 0.1 µf 37.5 KΩ ms ms 0.1 µf 12.8 KΩ ms ms Anoher facor o affec he exended blanking ime is he inpu volage hrough he R B01 and R B02. I would, on he conrary, reduce he exended blanking ime. Daa Shee 31 Version 1.0,

32 Elecrical Characerisics 4 Elecrical Characerisics All volages are measured in respec o ground (GND, pin 8). The volage levels are valid if oher raings are no violaed. 4.1 Absolue Maximum Raings Absolue maximum raings are defined as raings, which when exceeded may lead o desrucion of he inegraed circui. For he same reason, ensure ha any capacior o be conneced o pin 7 (VCC) is discharged before assembling he applicaion circui. T a = 25 C unless oherwise specified. Parameer Symbol Limi Values Uni Remarks min. max. Drain/source volage V DS 800 V Pulse drain curren, p limied by max. T j =150 C I D_Puls 4.9 A Avalanche energy, repeiive AR limied by max. T j = 150 C 1) E AR mj Avalanche curren, repeiive AR limied by max. T j =150 C 1) I AR 1.5 A VCC supply volage V VCC V FB volage V FB V BA volage V BA V CS volage V CS V Juncion emperaure T j C Conroller & CoolMOS Sorage emperaure T S C Thermal resisance juncion, ambien R hja 96 K/W Soldering emperaure, wavesoldering only allowed a leads T sold 260 C 1.6 mm (0.063 in.) from case for 10 s ESD capabiliy (incl. drain pin) V ESD 2 kv Human body model 2) 1) Repeeive avalanche causes addiional power losses ha can be calculaed as P AV =E AR * f 2) According o EIA/JESD22-A114-B (discharging a 100 pf capacior hrough a 1.5 kω series resisor) Daa Shee 32 Version 1.0,

33 Elecrical Characerisics 4.2 Operaing Range Wihin he operaing range he IC operaes as described in he funcional descripion. Parameer Symbol Limi Values Uni Remarks min. max. VCC supply volage V VCC V VCCoff 25 V Max. value limied due o Vcc OVP Juncion emperaure of conroller Max. value limied due o hermal T jcon C shudown of conroller Juncion emperaure of CoolMOS T JCoolMOS C 4.3 Characerisics Supply Secion The elecrical characerisics involve he spread of values guaraneed wihin he specified supply volage and juncion emperaure range T J from 25 C o 125 C. Typical values represen he median values, which are relaed o 25 C. Unless oherwise saed, a supply volage of VCC = 17 V is assumed. Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. Sarup curren I VCCsar µa V VCC = 16 V VCC charge curren I VCCcharge1 5.0 ma V VCC = 0 V I VCCcharge ma V VCC = 1 V I VCCcharge ma V VCC = 16 V Leakage curren of he sarup cell & CoolMOS I SarLeak µa V Drain = 650 V a T j = 100 C 1) Supply curren wih ma I inacive gae VCCsup1 Supply curren wih acive gae I VCCsup ma I FB = 0 A Supply curren in Auo Resar 320 µa I mode wih inacive gae VCCresar I FB = 0 A Supply curren in Floaing Load I VCCFLP µa V FB = 2.5 V Proecion (FLP) mode wih inacive gae I VCCFLP µa V CC = 11.5 V, V FB = 2.5 V VCC urn-on hreshold VCC Turn-off hreshold VCC Turn-on/off hyseresis V VCCon V VCCoff V VCChys ) The parameer is no subjeced o producion esing; i is verified by design/characerizaion V V V Daa Shee 33 Version 1.0,

34 Elecrical Characerisics Inernal Volage Reference Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. Trimmed reference volage V REF V Measured a pin FB, I FB = 0 A PWM Secion Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. Fixed oscillaor frequency f OSC khz f OSC khz T j = 25 C Frequency jiering range f jier ± 2.6 khz T j = 25 C Frequency jiering period jier 4.0 ms T j = 25 C Max. duy cycle D max Min. duy cycle D min 0 V FB < 0.3 V PWM OP gain A V Volage ramp offse V Offse-Ramp 0.6 V V FB operaing range, min. level V FBmin 0.7 V V FB operaing range, max. level V FBmax 4.3 V CS=1V limied by comparaor C4 1) Feedback pull-up resisor R FB kω 1) This parameer is no subjec o producion esing and is verified by design/characerizaion Sof Sar Time Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. Sof sar ime SS 10.0 ms Daa Shee 34 Version 1.0,

35 Elecrical Characerisics Conrol Uni Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. Blanking ime volage lower limi for comparaor C3 V BKC V Blanking ime volage upper limi for comparaor C11 V BKC V Overload limi for comparaor C4 V FBC V Enry FLP selec high level for comparaor C19 V FBLPC V Enry FLP selec low level for comparaor C20 V FBLPC V FLP mode enry 10 % P in_max V FB_FLP V < 7 couns level for comparaor 6.67 % P in_max V FB_FLP V 8 ~ 39 couns C % P in_max V FB_FLP V 40 ~ 191 couns FLP mode high level for comparaor C6a V FBFLPC6a V FLP mode low level for comparaor C6b V FBFLPC6b V FLP mode level for comparaor C13 V FBFLPC V Overvolage deecion limi for comparaor C1 V VCCOVP V Overvolage deecion limi for comparaor C2 V VCCOVP V Auo-resar enable reference volage for comparaor C9 V AE V Charging curren for exended blanking ime I chg_eb μa Thermal shudown 1) Hyseresis for hermal shudown 1) T jsd_hys C Buil-in blanking ime for overload proecion or ener FLP mode BK ms Time for enry FLP selec EFLPS ms Spike blanking ime for auo resar proecion Spike μs T jsd C Conroller In Floaing Load Proecion (FLP) mode V FB = 5 V, during sof sar 1) The parameer is no subjeced o producion esing bu is verified by design/characerizaion. The hermal shudown emperaure refers o he juncion emperaure of he conroller. Noe: The rend of all he volage levels in he Conrol Uni is he same regarding he deviaion excep V VCCOVP and V VCCPD. Daa Shee 35 Version 1.0,

36 Elecrical Characerisics Curren Limiing Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. Peak curren limiaion (incl. propagaion delay) V csh V dv sense / d = 0.6 V/µs (Figure 21) Peak curren limiaion during 20 % P in_max V cshflp V < 7 couns Floaing Load Proecion mode 13.3 % P in_max V cshflp V 8 ~ 39 couns 9.6 % P in_max V cshflp V 40 ~ 191 couns Leading edge blanking Normal mode LEBnormal 220 ns FLP mode LEB_FLP 180 ns CS inpu bias curren I CSbias μa V CS = 0 V CoolMOS Secion Parameer Symbol Limi Values Uni Tes Condiions min. yp. max. Drain/source breakdown volage V (BR)DSS Drain/source on resisance R DSon V V T j = 25 C T j = 110 C 1) Effecive oupu capaciance, energyrelaed C o(er) pf V DS = 0 V o 480 V Rise ime rise 30 2) ns Fall ime fall 30 2) ns 1) The parameer is no subjec o producion esing and is verified by design/characerizaion 2) Measured in a ypical flyback converer applicaion Ω Ω Ω T j = 25 C T j = 125 C 1) T j = 150 C 1) a I D = 0.81 A Daa Shee 36 Version 1.0,

37 CoolMOS Performance Characerisic 5 CoolMOS Performance Characerisic Figure 30 Safe Operaing Area (SOA) curve for conrollers LedSET Figure 31 SOA emperaure deraing coefficien curve Daa Shee 37 Version 1.0,

38 CoolMOS Performance Characerisic Allowable Power Dissipaion Figure 32 Power dissipaion; P o =f(t a ) Figure 33 Drain-source breakdown volage; V BR(DSS) = f(t j ), I D =0.25mA Daa Shee 38 Version 1.0,

39 Inpu Power Curve 6 Inpu Power Curve Two inpu power curves giving he ypical inpu power versus ambien emperaure are showed below; Vin = 85 Vac ~ 265 Vac (Figure 34) and Vin=230Vac±15% (Figure 35). The curves are derived on he basis of a ypical disconinuous mode flyback model which considers eiher a 60 % maximum duy raio or 150 V maximum secondary-o-primary-refleced volage (higher prioriy). The calculaion is based on no copper area as he hea sink for he device. The inpu power already includes he power loss a inpu common mode choke, bridge recifier and he CoolMOS.The device sauraion curren (I T j = 125 C) is also considered. To esimae he oupu power of he device, simply muliply he inpu power a a paricular operaing ambien emperaure wih he esimaed efficiency for he applicaion. For example, a wide range inpu volage (Figure 34), operaing emperaure 50 C, esimaed efficiency 85 %, hen he esimaed oupu power is 23 W (28 W * 85 %). Figure 34 Inpu power curve Vin = 85~265 Vac; P in = f(t a ) Figure 35 Inpu power curve Vin = 230 Vac ± 15 %; P in = f(t a ) Daa Shee 39 Version 1.0,

40 Ouline Dimensions 7 Ouline Dimensions 7.1 Ouline Dimensions of PG-DIP-7 Figure 36 PG-DIP-7 (Pb-free lead plaing plasic dual inline ouline) Daa Shee 40 Version 1.0,

41 Marking 8 Marking Figure 37 Marking for Daa Shee 41 Version 1.0,

42 Published by Infineon Technologies AG

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