Smart Ballast Control IC for Fluorescent Lamp Ballasts

Transcription

1 Preliminary Daashee Version 1.02, March 2009 ICB1FL03G Smar Ballas Conrol IC for Fluorescen Lamp Ballass Indusrial & Mulimarke

2 Revision Hisory: V 1.02 Previous Version: V 1.01 Page Subjecs (major changes since las revision) Ediion Published by Infineon Technologies AG Munich, Germany 2009 Infineon Technologies AG. All Righs Reserved. Legal Disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office ( Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac he neares Infineon Technologies Office. Infineon Technologies componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.

3 Smar Ballas Conrol IC for Fluorescen Lamp Ballass Produc Highlighs Lowes Coun of exernal Componens HV-Driver wih coreless Transformer Technology Improved Reliabiliy and minimized Spread due o digial and opimized analog conrol funcions PG-DSO-18-2 PG-DSO-18-1 Feaures PFC Disconinuous Conducion Mode PFC Inegraed Compensaion of PFC Conrol Loop Adjusable PFC Curren Limiaion Adjusable PFC Bus Volage Feaures Lamp Ballas Inverer Suppors Resar afer Lamp Removal and End-of- Life Deecion even in serial Muli-Lamp Topologies End-of-Life (EOL) deeced by adjusable ± Thresholds of sensed lamp volage Recifier Effec deeced by raio of ± Ampliude of Lamp Volage Deecion of differen capaciive Mode Operaions Adjusable Inverer Overcurren Shudown Self-adapion of Igniion Time from 40ms o 235ms Parameers adjusable by Resisors only Pb-free lead plaing; RoHS complian Halogen-free mould compound, WEEE complian Descripion The Smar Ballas IC is designed o conrol a Fluorescen Lamp Ballas including a Disconinuous Conducion Mode Power Facor Correcion (PFC), a lamp Inverer Conrol and a High Volage Level Shif Half-Bridge Driver. The applicaion requires a minimum of exernal componens. There are inegraed low pass filers and an inernal compensaion for he PFC volage loop conrol. Preheaing ime is adjusable by a single resisor only in he range beween 0 and 2000ms. In he same way he preheaing frequency and run frequency are se by resisors only. The conrol concep covers requiremens for T5 lamp ballass such as deecion of end-of-life and deecion of capaciive mode operaion and oher proecion measures in serial mulilamp opologies. ICB1FL03G is easy o use and easy o design and herefore a basis for a cos effecive soluion for fluorescen lamp ballass. R41 R42 R43 C5 L10 D1...4 C1 C VAC PE C2 C3 R1 R2 R3 L1 Q1 R11 C10 R12 D5 R13 R14 R15 R16 R18 R19 C11R20 D9 C12 R34 PFCZCD PFCGD PFCVS PFCCS GND VCC C61 SMD ICB1FL03G RFRUN RFPH LVS R26 HSGD HSVCC HSGND LSGD LSCS RTPH RES C14 R27 D6 R61 R35 Q2 Q3 R21R22R23 R30 C13 R24R25 C15 C18 C17 C16 D7 D8 L2 K6 K2 D61 C19 SMD-Z K1 C24 K5 R36 Type Package ICB1FL03G PG-DSO-18-2 Preliminary Daashee Version March 2009

4 Table of Conens Page 1 Pin Configuraion and Descripion Pin Configuraion PG-DSO Pin Descripion Block Diagram Funcional Descripion Typical operaing levels during sar-up PFC Preconverer Typical operaing levels during sar-up Deecion of End-of-Life and Recifier Effec Deecion of capaciive mode operaing condiions Inerrupion of Operaion and Resar afer Lamp Removal Sae Diagram Proecion Funcions Elecrical Characerisics Absolue Maximum Raings Operaing Range Characerisics Power Supply Secion PFC Secion PFC Curren Sense (PFCCS) PFC Zero Curren Deecor (PFCZCD) PFC Bus Volage Sense (PFCVS) PFC PWM Generaion PFC Gae Drive (PFCGD) Inverer Secion Inverer Conrol (RFRUN, RFPH, RTPH) Inverer Low Side Curren Sense (LSCS) Resar afer Lamp Removal (RES) Lamp Volage Sense (LVS) Inverer Low Side Gae Drive (LSGD) Inverer High Side Gae Drive (HSGD) Applicaion Examples Operaing Behaviour of a Ballas for a single Fluorescen Lamp Design Equaions of a Ballas Applicaion Mulilamp Ballas Topologies Package Oulines Preliminary Daashee Version March 2009

5 1 Pin Configuraion and Descripion 1.1 Pin Configuraion PG-DSO-18-2 Pin Symbol Funcion 1 LSCS Low side curren sense (inverer) 2 LSGD Low side gae drive (inverer) 3 VCC Supply volage 4 GND Conroller ground 5 PFCGD PFC gae drive 6 PFCCS PFC curren sense 7 PFCZCD PFC zero curren deecor 8 PFCVS PFC volage sense 9 RFRUN Se R for run frequency 10 RFPH Se R for preheaing frequency 11 RTPH Se R for preheaing ime 12 RES Resar afer lamp removal 13 LVS Lamp volage sense 14 n.c. No conneced 15 n.e. No exising 16 n.e. No exising 17 HSGND High side ground 18 HSVCC High side supply volage 19 HSGD High side gae drive 20 HSGND High side ground Pin Configuraion and Descripion 1.2 Pin Descripion LSCS (Low side curren sense, Pin This pin is direcly conneced o he shun resisor which is locaed beween he Source erminal of he low-side MOSFET of he inverer and ground. Inernal clamping srucures and filering measures allow for sensing he Source curren of he low-side inverer MOSFET wihou addiional filer componens. There is a firs hreshold of 0,8V, which provides a couple of increasing seps of frequency during igniion mode, if exceeded by he sensed curren signal for a ime longer han 250ns. If he sensed curren signal exceeds a second hreshold of 1,6V for longer han 400ns during all operaing modes, a lached shu down of he IC will be he resul. LSGD (Low side gae drive, Pin 2) The Gae of he low-side MOSFET in a half-bridge inverer opology is conrolled by his pin. There is an acive L-level during UVLO (undervolage lockou) and a limiaion of he max. H-level a 11V during normal operaion. Turning on he MOSFET sofly (wih reduced di DRAIN /d), he Gae drive volage rises wihin 220ns from L-level o H-level. The fall ime of he Gae drive volage is less han 50ns in order o urn off quickly. This measure produces differen swiching speeds during urn-on and urn-off as i is usually achieved wih a diode in parallel o a resisor in he Gae drive loop. I is recommended o use a resisor of abou 15Ohm beween drive pin and Gae in order o avoid oscillaions and in order o shif he power dissipaion of discharging he Gae capaciance ino his resisor. The dead ime beween LSGD signal and HSGD signal is 1800ns ypically. LSCS LSGD VCC GND PFCGD PFCCS PFCZCD PFCVS ICB1FL03G N.C. HSGD HSVCC HSGND N.C. LVS VCC (Supply volage, Pin 3) This pin provides he power supply of he ground relaed secion of he IC. There is a urn-on hreshold a 14V and an UVLO hreshold a 10,5V. Upper supply volage level is 17,5V. There is an inernal zener diode clamping Vcc a 16V (2mA ypically). The zener curren is inernally limied o 5mA max. For higher curren levels an exernal zener diode is required. Curren consumpion during UVLO and during faul mode is less han 150µA. A ceramic capacior close o he supply and GND pin is required in order o ac as a lowimpedance power source for Gae drive and logic signal currens. RFRUN RFPH PG-DSO-18-2 (300mil) RES RTPH GND (Ground, Pin 4) This pin is conneced o ground and represens he ground level of he IC for supply volage, Gae drive and sense signals. Preliminary Daashee Version March 2009

6 Pin Configuraion and Descripion PFCGD (PFC gae drive, Pin 5) The Gae of he MOSFET in he PFC preconverer designed in boos opology is conrolled by his pin. There is an acive L-level during UVLO and a limiaion of he max. H-level a 11V during normal operaion. Turning on he MOSFET sofly (wih a reduced di DRAIN / d), he Gae drive volage rises wihin 220ns from L- level o H-level. The fall ime of he Gae volage is less han 50ns in order o urn off quickly. A resisor of abou 15Ω beween drive pin and Gae in order o avoid oscillaions and in order o shif he power dissipaion of discharging he Gae capaciance ino his resisor is recommended. The PFC secion of he IC conrols a boos converer as a PFC preconverer in disconinuous conducion mode (DCM). Typically he conrol sars wih Gae drive pulses wih an on-ime of 1µs increasing up o 24µs and a off-ime of 40µs. As soon as a sufficien ZCD (zero curren deecor) signal is available, he operaing mode changes from a fixed frequen operaion o an operaion wih variable frequency. During raed and medium load condiions we ge an operaion wih criical conducion mode (CriCM), ha means riangular shaped currens in he boos converer choke wihou gaps when reaching he zero level and variable operaing frequency. During ligh load (deeced by he inernal error amplifier) we ge an operaion wih disconinuous conducion mode (DCM), ha means riangular shaped currens in he boos converer choke wih gaps when reaching he zero level and variable operaing frequency in order o avoid seps in he consumed line curren. PFCCS (PFC curren sense, Pin 6) The volage drop across a shun resisor locaed beween Source of he PFC MOSFET and GND is sensed wih his pin. If he level exceeds a hreshold of 1V for longer han 260ns he PFC Gae drive is urned off as long as he ZCD (zero curren deecor) enables a new cycle. If here is no ZCD signal available wihin 40µs afer urn-off of he PFC Gae drive, a new cycle is iniiaed from an inernal sar-up imer. PFCZCD (PFC zero curren deecion, Pin 7) This pin senses he poin of ime when he curren hrough he boos inducor becomes zero during offime of he PFC MOSFET in order o iniiae a new cycle. The momen of ineres appears when he volage of he separae ZCD winding changes from posiive o negaive level which represens a volage of zero a he inducor windings and herefore he end of curren flow from lower inpu volage level o higher oupu volage level. There is a hreshold wih hyseresis, for increasing volage a level of 1,5V, for decreasing volage a level of 0,5V, ha deecs he change of inducor volage. A resisor conneced beween ZCD winding and sense inpu limis he sink and source curren of he sense pin, when he volage of he ZCD winding exceeds he inernal clamping levels (6,3V and 4mA) of he IC. If he sensed level of he ZCD winding is no sufficien (e.g. during sar-up), an inernal sar-up imer will iniiae a new cycle every 40µs afer urn-off of he PFC Gae drive. PFCVS (PFC volage sense, Pin 8) The inermediae circui volage (bus volage) a he smoohing capacior is sensed by a resisive divider a his pin. The inernal reference volage for raed bus volage is 2,5V. There are furher hresholds a 0,375V (15% of raed bus volage), 1,83V (73% of raed bus volage) and 2,725V (109% of raed bus volage) for deecing open conrol loop, undervolage and overvolage. RFRUN (Se R for run frequency, Pin 9) A resisor from his pin o ground ses he operaing frequency of he inverer during run mode. Typical run frequency range is 20kHz o 100kHz. The se resisor R RFRUN can be calculaed based on he run frequency f RUN according o he equaion R = ΩHz RFRUN f RUN RFPH (Se R for preheaing frequency, Pin 10) A resisor from his pin o ground ses ogeher wih he resisor a pin 9 he operaing frequency of he inverer during prehea mode. Typical prehea frequency range is run frequency (as a minimum) o 150kHz. The se resisor R RFPH can be calculaed based on he prehea frequency f PH and he resisor R RFRUN according o he equaion: R R = RFRUN RFPH f PH R RFRUN ΩHz The oal value of boh resisors R RFPH and R RFRUN swiched in parallel should no be less han 3,3kOhm. RTPH (Se R for preheaing ime, Pin 1 A resisor from his pin o ground ses he preheaing ime of he inverer during prehea mode. A se resisor range from zero o 18kOhm corresponds o a range of preheaing ime from zero o 2000ms subdivided in 127 seps. RES (Resar afer lamp removal, Pin 12) A source curren ou of his pin via resisor and filamen o ground moniors he exisence of he low-side filamen of he fluorescen lamp for resar afer lamp Preliminary Daashee Version March 2009

7 removal. A capacior from his pin direcly o ground eliminaes a superimposed AC volage ha is generaed as a volage drop across he low-side filamen. During ypical sar-up wih conneced filamens of he lamp a curren source I RES3 (20µA) is acive as long as Vcc> 10,5V and V RES < V RESC1 (1,6V). An open Lowside filamen is deeced, when V RES > V RESC1. Such a condiion will preven he sar-up of he IC. In addiion he comparaor hreshold is se o V RESC2 (1,3V) and he curren source changes o I RES4 (17µA). Now he sysem is waiing for a volage level lower han V RESC2 a he RES-Pin ha indicaes a conneced low-side filamen, which will enable he sar-up of he IC. An open high-side filamen is deeced when here is no sink curren I LVSsink (15µA) ino he LVS-Pin before he V CC sar-up hreshold is reached. Under hese condiions he curren source a he RES-Pin is I RES1 (41µA) as long as Vcc> 10,5V and V RES < V RESC1 (1,6V) and he curren source is I RES2 (34µA) when he hreshold has changed o V RESC2 (1,3V). In his way he deecion of he high-side filamen is mirrored o he levels on he RES-Pin. Finally here is a delay funcion implemened a he RES-Pin. When a faul condiion happens e.g. by an end-of-life crieria he inverer is urned-off. In some opologies a ransien AC lamp volage may occur immediaely afer shu down of he Gae drives which could be inerpreed as a lamp removal. In order o generae a delay for he deecion of a lamp removal he capacior a he RES-Pin is charged by he I RES3 (20µA) curren source up o he hreshold V RESC1 (1,6V) and discharged by an inernal resisor R RESdisch, which operaes in parallel o he exernal sense resisor a his pin, o he hreshold V RESC3 (0,375V). The oal delay amouns o 32 of hese cycles, which corresponds o a delay ime beween 30ms o 100ms dependen on capacior value. In addiion his pin is applied o sense capaciive mode operaion by use of a furher capacior conneced from his pin o he nod of he high-side MOSFET s Source erminal and he low-side MOSFET s Drain erminal. The sense capacior and he filer capacior are acing as a capaciive volage divider ha allows for deecing volage slopes versus iming sequence and herefore indicaing capaciive mode operaion. A ypical raio of he capaciive divider is 410V/2,2V which resuls in he capacior values e.g. of 10nF and 53pF (56pF). LVS (Lamp volage sense, Pin 13) Before he IC eners he sofsar mode his pin has o sense a sink curren above 26µA (max) which is fed via resisors from he bus volage across he high-side filamen of he fluorescen lamp in order o monior he exisence of he filamen for resar afer lamp removal. Togeher wih RES (pin 12) he IC can monior he lamp removal of oally 2 lamps in series. During run mode he lamp volage is sensed by he AC curren fed ino his pin via resisors. Exceeding one of Pin Configuraion and Descripion he wo hresholds of eiher +215µA or -215µA cycle by cycle for longer han 610µs, he inerpreaion of his even is a failure due o EOL1 (end-of-life). A recifier effec (EOL2) is assumed if he raio of he sequence of posiive and negaive ampliudes is above 1,15 or below 0,85 for longer han 500ms. A failure due o EOL1 or EOL2 changes he operaing mode from run mode ino a lached faul mode ha sops he operaion unil a rese occurs by lamp removal or by cycle of power. EOL1 and EOL2 require an AC curren wih zerocrossings a LVS-Pin for a reliable deecion. A DC curren a LVS-Pin resuls in a definie urn-off acion acc. o EOL1 only if he sensed curren exceeds he hreshold I LVSEOLDC = +/-175µA (ypically). If he funcionaliy of his pin is no required i can be disabled by connecing his pin o ground. No Conneced (Pin 14) This pin is inernally no conneced. HSGND (High side ground, Pin 17) This pin is conneced o he Source erminal of he high-side MOSFET, which is also he nod of high-side and low-side MOSFET. This pin represens he floaing ground level of he high-side driver and high-side supply. HSVCC (High side supply volage, Pin 18) This pin provides he power supply of he high-side ground relaed secion of he IC. An exernal capacior beween pin 15 and 16 acs like a floaing baery which has o be recharged cycle by cycle via high volage diode from low-side supply volage during on-ime of he low-side MOSFET. There is an UVLO hreshold wih hyseresis ha enables high-side secion a 10,1V and disables i a 8,4V. HSGD (High side gae drive, Pin 19) The Gae of he high-side MOSFET in a half-bridge inverer opology is conrolled by his pin. There is an acive L-level during UVLO and a limiaion of he max. H-level a 11V during normal operaion. The swiching characerisics are he same as described for LSGD (pin 2). I is recommended o use a resisor of abou 15Ohm beween drive pin and Gae in order o avoid oscillaions and in order o shif he power dissipaion of discharging he Gae capaciance ino his resisor. The dead ime beween LSGD signal and HSGD signal is 1800ns ypically. HSGND (High side ground, Pin 20) This pin is inernally conneced wih pin 17. Preliminary Daashee Version March 2009

8 Block Diagram 2 Block Diagram 5V H = on L = off I1 = 5µA C2 2,0V D2 I LVS 13 LVS D1 15µA VCC OFF_H G1 POWER_DOWN_L G2 EOLOFF_L D Q VPEAK(N) G3 EN N N+2 EN=L => Saus Lached VPEAK(N+ T1 N+1 D3 Q C3 G4 C1 +215µA G5 G6 LINSERT_H C4 END-OF-LIFE EOLACTIVE_H -215µA Peak Recificaion ILVS VPEAK(N+ = VPEAK(N) > 1,15...=> Q = H = 0,85..1,15=> Q = L < 0,85...=> Q = H 9 RFRUN LVS LVS 10 RFPH Av= 2.5 OP1 R1 R2 11 RTPH VTH 1= 2,725V VTH 2= 2,625V VTH= 1,83V 8 PFCVS V TH= 0,375V END-OF-LIFE 2 CAPACITIVE LOAD 1 DIGITAL LOOP OPEN FILAMENT 8-Bi ADC CONTROL VBUS OVERVOLTAGE PFC_PWM_IN END-OF-LIFE 1 V REF= 2,50V CAPACITIVE LOAD 2 5µs VBUS C1 OPERATION ABOVE Blank OVERVOLTAGE RUN FREQUENCY INVERTER VBUS C2 5µs OVERCURRENT Blank UNDERVOLTAGE LVS_L 5µs VBUS OPEN C3 OFF_H Blank LOOP DETECT LAMP_INSERT_H UVLO _L PFC_VS OPEN_LOOP_L Up & Down 1 Couner min.duraion of effec: 500ms 1 min.duraion of effec: 610µs 235ms afer end of prehea mode min.duraion of effec: 400ns FAULT LATCH POWER_DOWN_L ERROR_LOGIC 5,0V LVS I3= 20µA; V RES< 1,6V; VCC> 10,5V; ILVS> 15µA; or during run mode I1= 41µA; VRES< 1,6V; VCC> 10,5V; ILVS< 15µA; OPEN_FILAMENT I4= 17µA; VRES> 1,6V; VCC> 10,5V; ILVS> 15µA; 3,2V CA PLOAD1 I2= 34µA; V RES> 1,6V; VCC> 10,5V; ILVS< 15µA; D Q 12 RES Capaciive Load I5= 41µA & 0µA alernaing for 32 cycles as a delay; C1 Deecion 1,6V G1 5µs V C3 Lamp inser INV1 DS Blank deecion for VRES < 1,6V D Q 1,3V 5µs CAP LOAD1 C4 during Blank G3 power down. V DS T1 0,375V 5µs C2 D Q C5 Delay generaor Blank for acivaing 0,24V G2 CAP LOAD2 lamp removal T1 afer faul lach LS GDIN_H CA PLOAD2 54k is se. HSGDIN_H LAMP_INSERT_H CAPLOAD-RES dac4 Oher Modes 5,0V Run Mode T2 T1 S1 OP I OSC Bias Cell1 Oscillaor dac7 R1 Iosc fosc S2 OP OSC 2,5V Bias Cell2 RFRUN dac7, dac4 = 2,5V Prehea Mode GND during Oher Modes run mode, oherwise S3 OP ransien volage levels dac7 (0..2,5V) Bias Cell3 RFPH VCO 2,0V Sofsar and 5,0V Prehea Mode T2 T1 Oher Modes S1 OP PHEND_H 5µs Bias Cell1 Blank R1 RTPH C1 PREHEAT_TIMER dac 7 VCC In. Supply 5V 5µs C1 Blank UVLO V TH1=14,0V V TH2=10,5V VDD_good_H G3 Z1 C2 OFF_H V TH=10,5V POWERSUPPLY PHEND_H dac4 dac7 DSC OSC Digial sequenial conrol Bandgap Vref=2.5V Maser Clock SPI for Tes Mode POWER_DOWN_L MCLOCK_SPI Coreless T. HS G1 V GATE slope conrol Z1 =12V 0 220ns VCC LS G1 V GATE slope conrol Z1 =12V 0 220ns LS PWM INV_OC HS inverer 400ns DSC Blank 1,8µs 250ns Dead Blank ime IGN-LIM INVPWM VCC PFCGDIN G1 VGATE slope conrol Z1 =12V 0 220ns PFC 260ns PWM & Blank Conrol PFC_CLIM PFCGDIN PFC_PWM_IN DSC PFC_ZCD Sar-up C2 D3 imer VTH off-ime 1=1,5V 40µs V TH 2=0,5V PFCPWM T2 D2 T1 D1 Z1 HSGD T2 D2 T1 D1 Z1 LSGD 1,6V C1 C2 0,8V INVCLIM T2 D2 T1 D1 Z1 PFCGD C1 1.0V 5,0V D1 R1 D2 R2 PFCCS HSVCC HSGD HSGND VCC LSGD GND LSCS PFCGD PFCCS PFCZCD & 1 & 1 & S R 1 1 Q Q vr e f & Figure 1 Simplified Blockdiagram of ICB1FL03G Preliminary Daashee Version March 2009

9 Funcional Descripion 3 Funcional Descripion 3.1 Typical operaing levels during sar-up The conrol of he ballas should be able o sar he operaion wihin less han 100ms. Therefore he curren consumpion of he IC is less han 150µA during UVLO. Wih a small sar-up capacior (abou 1µF) and a power supply, ha feeds wihin 100µs (charge pump of he inverer) he IC can cover his feaure. As long as he Vcc is less han 10,5V, he curren consumpion is ypically 80µA. Above a Vcc volage level of 10,5V he IC checks wheher he lamp(s) are assembled by deecing a curren across he filamens. The low-side filamen is checked from a source curren (20µA yp.) ou of pin RES, ha produces a volage drop a he sense resisor, which is conneced via low-side filamen o ground. An open filamen is deeced, when he volage level a pin RES is above 1,6V. The high-side filamen (or he high-side of a series opology) is checked by a curren (15µA yp.) ino he LVS pin. An open high-side filamen causes a higher source curren (41µA / 34µA yp.) ou of pin RES in order o exceed he 1,6V hreshold. If he filamen is no able o conduc he es curren, he conrol circui is disabled. The IC is enabled as soon as a sufficien curren is deeced across he filamen or he supply volage drops below he UVLO hreshold (10,5V) e.g. by urn-off and urn-on of mains swich. V CC 14,0V 10,5V UVLO START-UP HYSTERESIS IC ACTIVE SOFTSTART I VCC 80µA 80µA <150µA 5mA + QGae V RES 3,2V 1,6V <3,2V I RES 20µA 20µA I LVS >15µA >15µA < +/- 2,5mA Figure 2 Progress of levels during a ypical sar-up. When he previous condiions are fulfilled, and Vcc has reached he sar-up hreshold (14V), here is finally a check of he Bus volage. If he level is less han 15% of raed Bus volage, he IC is waiing in power down mode unil he volage increases. If he level is above 109% of raed Bus volage here is no Gae drive, bu an acive IC. The supply volage Vcc will fall below he UVLO hreshold and a new sar-up aemp is iniiaed. As soon as sar-up condiions are fulfilled he IC sars driving he inverer wih he sar-up frequency of 125kHz. Now he complee conrol including imers and he PFC conrol can be se in acion. There are curren limiaion hresholds for PFC preconverer and ballas inverer equipped wih spike filers. The PFC curren limiaion inerrups he on-ime of he PFC MOSFET if he volage drop a shun resisor exceeds 1V and resars afer nex inpu from ZCD. The inverer curren limiaion operaes wih a firs hreshold of 0,8V which increases he operaing frequency during igniion mode if exceeded. A second hreshold is provided a 1,6V ha sops he whole conrol circui and laches his even as a faul. Preliminary Daashee Version March 2009

10 Funcional Descripion V CC 16,0V 14,0V 10,5V I VCC 80µA V RES 5,0V 3,2V 1,6V 1,3V I RES LS FILAMENT OPEN UVLO HS FILAMENT CLOSED START-UP HYSTERESIS 80µA <170µA LAMP REMOVAL LS + HS OPEN V RES > 1,3V <150µA IC ACTIVE SOFTSTART 5mA + QGae <3,2V 20µA I LVS 20µA 17µA 34µA 17µA 20µA >15µA POWER DOWN SIGNAL >15µA >15µA < +/- 2,5mA H Figure 3 Sar-up wih LS filamen broken and subsequen lamp removal. V CC 16,0V 14,0V 10,5V I VCC 80µA V RES 5,0V 3,2V 1,6V 1,3V I RES UVLO 80µA HS FILAMENT OPEN LS FILAMENT CLOSED START-UP HYSTERESIS <170µA LAMP REMOVAL V RES > 1,3V LS + HS OPEN <150µA 1,3V IC ACTIVE SOFTSTART 5mA + QGae <3,2V 20µA I LVS 41µA 34µA 34µA 17µA 20µA >15µA POWER DOWN SIGNAL >15µA < +/- 2,5mA H Figure 4 Sar-up wih HS filamen broken and subsequen lamp removal. Preliminary Daashee Version March 2009

11 3.2 PFC Preconverer Funcional Descripion PFC is saring wih a fixed frequen operaion (ca. 25kHz), beginning wih an on-ime of 1µs and an off-ime of 40µs. The on-ime is enlarged every 400µs o a maximum on-ime of 23µs. The conrol swiches over ino criical conducion mode (CriCM) operaion as soon as a sufficien ZCD signal is available. There is an overvolage hreshold a 109% of raed Bus volage ha sops PFC Gae drive as long as he Bus volage has reached a level of 105% of raed Bus volage again. The compensaion of he volage conrol loop is compleely inegraed. The inernal reference level of he Bus volage sense (PFCVS) is 2,5V wih high accuracy. The PFC conrol operaes in CriCM in he range of 23µs > on-ime > 2,3µs. For lower loads he conrol operaes in disconinuous conducion mode (DCM) wih an on-ime down o 0,5µs and an increasing off-ime. Wih his conrol mehod he PFC preconverer covers a sable operaion from 100% of load o 0,1%. C VAC PE L101 D1...4 C2 R1 R2 R3 L1 Q1 R11 R12 R34 D5 R13 R14 R15 R16 C10 PFCZCD PFCGD PFCVS PFCCS ICB1FL03G LVS AUX HSGD HSVCC HSGND LSGD LSCS GND VCC RFRUN RFPH RTPH RES R18R19 C11 R20 D9 C12 R21R22R23 C13 Figure 5 Circui Diagram of he PFC preconverer secion. Overvolage, undervolage and open loop deecion a pin PFCVS are sensed by analog comparaors. The BUS volage loop conrol is provided by a 8bi sigma-dela A/D-Converer wih a sampling rae of 400µs and a resoluion of 4mV/bi. So a range of +/- 0,5V from he reference level of 2,50V is covered. The digial error signal has o pass a digial noch filer in order o suppress he AC volage ripple of wice of he mains frequency. A subsequen error amplifier wih PI characerisic cares for sable operaion of he PFC preconverer. The zero curren deecion is sensed by a separae pin PFCZCD. The informaion of finished curren flow during demagneizaion is required in CriCM and in DCM as well. The inpu is equipped wih a special filering including a blanking of ypically 500ns and is combined wih a large hyseresis beween he hresholds of ypically 0,5V and 1,5V. In case of bad coupling beween primary inducor winding and secondary ZCD-winding an addiional filering by a capacior a ZCD pin migh be necessary in order o avoid misriggering by long lasing oscillaions during swiching slopes of he PFC MOSFET. PFCVS Σ -ADC SRae 400µs Res 4mV/bi Noch Filer PI Loop Conrol Pulse widh Generaor Gae Driver PFCGD Undervolage 73% +/- 2,5% Overvolage 109% +/-2,0% Overcurren Proecion 1,0V +/-5% ZCD 1,50V / 0,5V Sar-up PFCCS PFCZCD Open Loop Deecion 15% +/- 20% Clock 600kHz Reference 2,50V +/-1,5% Figure 6 Srucure of he mixed digial and analog conrol of PFC preconverer. Preliminary Daashee Version March 2009

12 Funcional Descripion Disconinuous Conducion Mode <> Criical Conducion Mode Relaive Power % idenificaion markings unfilled Operaing Frequency (khz) a VIN = VOUT/2 idenificaion markings filled 0, Digial Conrol Seps Figure 7 Relaive oupu power and operaing frequency of PFC conrol a VIN = VOUT /2 versus conrol sep. Disconinuous Conducion Mode <> Criical Conducion Mode On-Time (µs) idenificaion markings unfilled Operaing Frequency (khz) a VIN = VOUT/2 idenificaion markings filled Digial Conrol Seps Figure 8 On-ime and operaing frequency of PFC conrol a VIN = VOUT /2 versus conrol sep. Preliminary Daashee Version March 2009

13 3.3 Typical operaing levels during sar-up Funcional Descripion Wihin 10ms afer sar-up he inverer shifs operaing frequency from 125kHz o he preheaing frequency se by resisor a pin RFPH. Preheaing ime can be seleced by programming resisor a RFPH pin in seps of 17ms from 0ms o 2000ms. Afer preheaing he operaing frequency of he inverer is shifed downwards in 40ms ypically o he run frequency. During his frequency shifing he volage and curren in he resonan circui will rise when operaing close o he resonan frequency wih increasing volage across he lamp. As soon as he lower curren sense level (0,8V) is reached, he frequency shif downwards is sopped and increased by a couple of frequency seps in order o limi he curren and he igniion volage also. The procedure of shifing he operaing frequency up and down in order o say wihin he max igniion level is limied o a ime frame of 235ms. If here is no igniion wihin his ime he conrol is disabled and he saus is lached as a faul mode. Typical variaion of operaing frequency during sar-up 125kHz f, V 65kHz Frequency 50kHz 40kHz Lamp Volage 10ms Sofsar ms ms 250ms Preheaing Igniion Pre-Run Normal Operaion Sofsar proceeds in 15 seps à 650µs according f PH = (120kHz - f PH )/ 15seps. Igniion proceeds in 127 seps à 324µs according f IGN = (f PH - f RUN )/ 127seps. Figure 9 Typical variaion of operaing frequency and lamp volage during sar-up Lamp Volage Wihou Load Wih Load Run Afer Igniion Operaing Frequency Igniion Preheaing Figure 10 Typical lamp volage versus operaing frequency due o load change of he resonan circui. Preliminary Daashee Version March 2009

14 3.4 Deecion of End-of-Life and Recifier Effec Funcional Descripion Afer igniion he lamp volage breaks down o is run volage level (ypically 50Vpeak o 300Vpeak). Reaching he run frequency here follows a ime period of 250ms called Pre-Run Mode, in which some of he monioring feaures (EOL1, EOL2, Cap.Load are sill disabled. In he subsequen Run Mode he End-of-life (EOL) monioring is enabled. The even EOL1 is deeced by measuring he posiive and negaive peak level of he lamp volage by a curren fed ino he LVS pin (R41, R42, R43 in Fig. 1. If he sensed curren exceeds 215µA for longer han 610µs he saus end-of-life (EOL or he exceeding of he maximum oupu power is deeced. In Fig. 12 he differen levels of he sensed lamp volage are illusraed. R34 R41 R42 R43 D9 C10 PFCZCD PFCGD PFCVS PFCCS ICB1FL03G LVS AUX HSGD GND VCC RFRUN RFPH RTPH RES HSVCC HSGND C14 Q3 R27 LSGD LSCS R35 Q2 R26 D6 R61 R30 R21R22R23 C13 R24 R25 C15 C17 C18 C16 R36 D7 D8 L2 D61 SMD-Z C24 C19 Figure 11 Circui diagram of he lamp inverer secion. + Shu down level + Igniion level V LAMP-IGN + EOL Threshold IV L+PEAK I/IV L-PEAK I 0 V LAMP-RUN - EOL Threshold - Igniion level - Shu down level Figure 12 Sensed lamp volage levels. Preliminary Daashee Version March 2009

15 Funcional Descripion 2,5 2,4 2,3 2,2 Raio of higher Ampliude / smaller Ampliude 2,1 2 1,9 1,8 1,7 1,6 1,5 1,4 1,3 1,2 1, I LVS = Lamp Volage / Sense Resisor [ua] of smaller Ampliude Figure 13 Maximum raio of ampliudes versus sense curren. Furhermore he recificaion effec (EOL2) is deeced when he raio of he higher ampliude divided by he smaller ampliude of he lamp volage is bigger han illusraed in Fig. 13. for longer han 500ms. The raio is evaluaed each cycle of he lamp volage. The limi of he raio increases dependend on he peak curren of he smaller ampliude of he lamp volage from 1,15 a I LVS = 200µA nonlinear o 1,4 a I LVS = 50µA. If he EOL2 condiions are deeced, he conrol is disabled and he saus is lached as a failure mode. Measuring he duraion of incorrec operaing condiions is done by a check every 4ms. If he faul condiion is exising, a couner couns up, if he faul condiion is no exising, he couner couns down. So we ge an inegraion of he faul evens ha allows a very effecive monioring of srange operaing condiions. The deecion of EOL1 and EOL2 requires an AC curren inpu a he sense pin LVS for proper operaion. A DC curren a pin LVS will lead o a defined reacion only, if he level exeeds 175µA (ypically) for longer han 610µs which resuls in a shu down and change over ino he lached failure mode. 3.5 Deecion of capaciive mode operaing condiions If here happens a siuaion like an open resonan circui (e.g. a sudden break of he ube) he volage across he resonan capacior and curren hrough he shun of he low-side inverer MOSFET rise quickly. This even is deeced by inverer curren limiaion (1,6V) and resuls in shu down of he conrol. This saus is lached as a failure mode. In anoher kind of failure he operaion of he inverer may leave he zero volage swiching (ZVS) and move ino capaciive mode operaion or ino operaion below resonance. There are wo differen levels for capaciive mode deecion implemened in he IC. A firs crieria deecs low deviaions from ZVS (CapLoad and changes operaion ino faul mode, if his operaion lass longer han 500ms. For CapLoad1 he same couner is used as for he end-of-life evaluaion. Preliminary Daashee Version March 2009

16 Funcional Descripion A second hreshold deecs severe deviaions such as recangular shapes of volage during operaion below resonance (CapLoad2). Then he inverer is urned off as soon as hese condiions las longer han 610µs and he IC changes over ino faul mode. The evaluaion of he failure condiion is done by an up and down couner which samples he saus every 40µs. CapLoad1 is sensed in he momen when low-side Gae drive is urned on. If he volage level a pin RES is above he V REScap hreshold (yp. 0,24V) relaed o he level V RESLLV, condiions of CapLoad1 are assumed. CapLoad2 is sensed in he momen when he high-side Gae drive is urned on. If he volage level a pin RES is below he V REScap hreshold relaed o he level V RESLLV, condiions of CapLoad2 are assumed. As he reference level V RESLLV is a floaing level, i is updaed every on-ime of he low-side MOSFET. D61 limis volage ransiens a pin RES ha can occur during removal of he lamp in run mode. V DSLS I DLS V RES V RESCAP V RESLLV Gae HS Gae LS CAPM 1 CAPM 2 Deadime Figure 14 Levels and poins in ime for deecion of CapLoad1 and CapLoad Inerrupion of Operaion and Resar afer Lamp Removal In he even of a failing operaion he faul lach is se afer he specified reacion ime (e.g. 500ms a EOL2). Then he Gae drives are shu down immediaely, he conrol funcions are disabled and he curren consumpion is reduced o a level of 150µA (ypically). Vcc is clamped by inernal zener diode o max 17,5V a 2mA. So he inernal zener diode is only designed o limi Vcc when fed from he sar-up curren, bu no from he charge pump supply! There is a curren limiaion a he inernal zener diode funcion (max 5mA a Vcc= 17,5V) in order o avoid conflics wih he clamping level of he exernal zener diode. The capacior a pin RES is discharged and charged during 32 cycles in order o generae a delay of several 10ms. The delay is implemened for avoiding malfuncions in deecing he lamp removal due o volage ransiens ha can occur afer shu down. The rese of he faul lach happens afer exceeding he 1,6V hreshold a pin RES and enabling he IC afer lamp removal and subsequen decreasing volage level a pin RES below he 1,3V hreshold. Preliminary Daashee Version March 2009

17 Funcional Descripion The saus failure mode is kep as long unil a lamp removal is deeced (inerrupion of curren across filamens and deecion of he reurn of he curren) or he supply volage drops below UVLO. Afer a break down of he supply volage below he undervolage lockou (UVLO) hreshold he IC reses any failure lach and will ry o resar as soon as Vcc exceeds he sar-up hreshold. An undervolage (75%) of he bus volage will no be lached as a faul condiion. If he undervolage lass longer han 80µs he Gae drives are swiched off and he IC ries o resar afer a Vcc hyseresis has been passed. V CC 16,0V 14,0V 10,5V V RES 5,0V 3,2V 1,6V 1,3V 0,375V I RES 41µA I LVS <2,5mA POWER DOWN SIGNAL FAULT LATCH SIGNAL IC ACTIVE FAULT LATCH SET E.G. BY EOL I VCC 5mA + QGae <170µA 20µA H 32 CYCLES (>50ms ypically) TRANSIENT AT LVS PIN LAMP REMOVAL LS + HS OPEN V RES >1,3V IC ACTIVE SOFTSTART 20µA 34µA 17µA 20µA >15µA >15µA >15µA SET SIGNAL 1,6V <150µA RESET SIGNAL 1,3V 5mA + QGae < +/- 2,5mA H <3,2V Figure 15 Inerrupion of operaion by a faul condiion and subsequen lamp removal. Preliminary Daashee Version March 2009

18 Sae Diagram 4 Sae Diagram Mains Swich urned on; 0 < Vcc < 10,5V; IS< 80µA; IRES= 0µA 10,5 < Vcc < 14,0V; IS< 150µA; IRES= 20µA Vcc > 14,0V & VRES< 1,6V=> Sar 125kHz > f > F_PH; 10,5 < Vcc < 16,0V; f= F_PH 10,5 < Vcc < 16,0V; IRES= 20µA; f= F_RUN 10,5 < Vcc < 16,0V; f= F_RUN 10,5 < Vcc < 16,0V; F_PH > f > F_RUN Earlies Sop by EOL 62ms 35ms 10ms 0ms 2000ms 40ms 235ms 250ms 500ms UVLO Monioring Sofsar Preheaing Igniion Pre -Run Run BUS Overvolage >109% BUS Undervolage <75% BUS Open Loop <15% Overcurren PFC 1,0V acive acive acive acive acive acive (80µs) (300ns) acive acive acive acive acive acive acive ac,resar ac,resar acive acive Overcurren Inverer 1,6V Capaciive Load 2 Cap.Load1; EOL1,2 acive acive acive (605µs) acive, & 0,8V acive acive acive acive Faul Mode: disabled by Lamp Removal or UVLO; 10,5 < Vcc< 16,0V; IS< 150µA; IRES= 20µA Figure 16 Sae Diagram Preliminary Daashee Version March 2009

19 Proecion Funcions 5 Proecion Funcions Descripion of Faul Faul-Type Deecion acive during Consequence Min. Duraion of Effec Sofsar 10ms Prehea Mode ms Igniion Mode ms Pre-Run Mode 250ms Run Mode +/- Peak Level of Lamp Volage above hreshold Raio of +/- ampliudes of lamp volage > 1.15 or < 0.85 EOL1 610µs X Power down, lached Faul Mode EOL2 500ms X Power down, lached Faul Mode No zero volage swiching Cap.Load 1 500ms X Power down, lached Faul Mode Volage a Pin RES > 3.0V Open Filamen 500ms X Power down, lached Faul Mode Bus volage > 109% of raed level in acive operaion Bus volage > 109% of raed level 10µs afer power up Bus volage > 109% of raed level in acive operaion Overvolage 500ms X Power down, lached Faul Mode Overvolage PFC Overvolage Gae drivers off, resar afer V CC hyseresis 5µs X X X X X Turn-off PFC MOSFET unil Bus Volage < 105% Bus volage < 75% of raed level Undervolage 80µs X Gae drivers off, resar afer V CC hyseresis Bus volage < 15% of raed level Capaciive Load, Operaion below resonance Open Loop Deecion 1µs X X X X X Power down Cap.Load 2 610µs X X Power down, lached Faul Mode Run frequency can no be achieved No Igniion 235ms X Power down, lached Faul Mode Volage a Pin RES > 1.6V before power up Curren ino Pin LVS < 12µA Volage a Pin PFCCS > 1.0V Volage a Pin LSCS > 0.8V Volage a Pin LSCS > 1.6V Supply volage a Pin VCC < 14.0V before power up Supply volage a Pin VCC < 10.5V afer power up LS open Filamen HS open Filamen PFC Overcurren Inverer Curren Limi Inverer Overcurren Below sarup hreshold Below UVLO hreshold 1ms 1ms Prevens power up Prevens power up 260ns X X X X X Turn-off PFC MOSFET immediaely 250ns X Increases he Operaing Frequency 400ns X X X X X Power Down, Lached Faul Mode 1µs Prevens power up 1µs X X X X X Power Down, Rese of Lached Faul Mode Preliminary Daashee Version March 2009

20 Elecrical Characerisics 6 Elecrical Characerisics Noe: All volages wihou he high side signals are measured wih respec o ground (pin 4). The high side volages are measured wih respec o pin17/20. The volage levels are valid if oher raings are no violaed. 6.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 3 (VCC) and pin 18 (HSVCC) is discharged before assembling he applicaion circui. Parameer Symbol Limi Values Uni Remarks min. Preliminary Daashee Version March 2009 max. LSCS Volage V LSCS -5 6 V LSCS Curren I LSCS -3 3 ma LSGD Volage V LSGD -0.3 V cc +0.3 V inernally clamped o 11V VCC Volage V VCC V see VCC Zener Clamp VCC Zener Clamp Curren I VCCzener -5 5 ma IC in Power Down Mode PFCGD Volage V PFCGD -0.3 V cc +0.3 V inernally clamped o 11V PFCCS Volage V PFCCS -5 6 V PFCCS Curren I PFCCS -3 3 ma PFCZCD Volage V PFCZCD -3 6 V PFCZCD Curren I PFCZCD -5 5 ma PFCVS Volage V PFCVS V RFRUN Volage V RFRUN V RFPH Volage V RFPH V RTPH Volage V RTPH V RES Volage V RES V LVS Curren1 I LVS_1-1 1 ma IC in Power Down Mode LVS Curren2 I LVS_2-3 3 ma IC in Acive Mode HSGND Volage V HSGND V referring o GND HSGND, Volage Transien dv HSGND /d V/ns HSVCC Volage V HSVCC V referring o HSGND HSGD Volage V HSGD -0.3 V HSVCC V inernally clamped o 11V referring o HSGND PFCGD Peak Source Curren I PFCGDsomax 150 ma < 100ns PFCGD Peak Sink Curren I PFCGDsimax 700 ma < 100ns LSGD Peak Source Curren I LSGDsomax 75 ma < 100ns LSGD Peak Sink Curren I LSGDsimax 400 ma < 100ns HSGD Peak Source Curren I HSGDsomax 75 ma < 100ns HSGD Peak Sink Curren I HSGDsimax 400 ma < 100ns Juncion Temperaure T j C

21 Elecrical Characerisics Sorage Temperaure T S C Max possible Power Dissipaion P o 2 W PG-DSO-18-2, T amb = 25 C Thermal Resisance (Boh Chips) R hja 60 K/W PG-DSO-18-2 Juncion-Ambien Thermal Resisance (HS Chips) R hjahs 120 K/W PG-DSO-18-2 Juncion-Ambien Thermal Resisance (LS Chips) R hjals 120 K/W PG-DSO-18-2 Juncion-Ambien Soldering Temperaure 260 C wave sold. acc.jesd22a111 ESD Capabiliy V ESD 2 kv Human body model According o EIA/JESD22-A114-B (discharging an 100pF capacior hrough an 1.5kΩ series resisor). 6.2 Operaing Range Parameer Symbol Limi Values Uni Remarks min. max. HSVCC Supply Volage V HSVCC V HSVCCoff 17.0 V referring o HSGND HSGND Supply Volage V HSGND V referring o GND VCC Supply Volage V VCC V VCCoff 17.5 V LSCS Volage Range V LSCS -4 5 V PFCVS Volage Range V PFCVS 0 4 V PFCCS Volage Range V PFCCS -4 5 V PFCZCD Curren Range I PFCZCD -4 4 ma LVS Volage Range V LVS -0.3 LVS Curren Range I LVS Limied by maximum of curren range a LVS 2) Limied by minimum of volage range a LVS V IC in Power Down Mode 2) 300 µa IC in Power Down Mode LVS Curren Range I LVS ma IC in Acive Mode Juncion Temperaure T j C Adjusable Preheaing Frequency F RFPH F RFRUN 150 khz Range se by RFPH Adjusable Run Frequency Range F RFRUN khz se by RFRUN Adjusable Preheaing Time RTPH ms Range se by RTPH Se Resisor for Run Frequency R FRUN 5 25 kω Se Resisor for Preheaing Frequency (R FRUN parallel R FPH ) R FRUN 3.3 kω II R FPH Se Resisor for Preheaing Time R TPH 0 20 kω Preliminary Daashee Version March 2009

22 Elecrical Characerisics 6.3 Characerisics Power Supply Secion Noe: The elecrical characerisics involve he spread of values given wihin he specified supply volage and juncion emperaure range T J from 25 C o 125 C. Typical values represen he median values, which are relaed o 25 C. If no oherwise saed, a supply volage of V CC = 15 V and V HSVCC = 15V is assumed and he IC operaes in acive mode. Furhermore all volages are referring o GND if no oherwise menioned. Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. High Side Leakage Curren I HSGNDleak µa V HSGND = 800V V GND = 0V VCC Quiescen Curren I VCCqu µa V VCC = V VCCoff - 0.5V VCC Quiescen Curren I VCCqu µa V VCC = V VCCon - 0.5V VCC Supply Curren wih Inacive Gaes VCC Supply Curren in Lached Faul Mode I VCCsup1 5 7 ma V PFCVS > 2.725V I VCClach µa V RES = 5V LS VCC Turn-On Threshold LS VCC Turn-Off Threshold LSVCC Turn-On/Off Hyseresis V VCCon V VCCoff V VCChys V V V VCC Zener Clamp Volage V VCCclmp V I VCC = 2mA V RES = 5V VCC Zener Clamp Curren I VCCzener ma V VCC = 17.5V V RES = 5V HSVCC Quiescen Curren I HSVCCqu µa V HSVCC = V HSVCCon -0.5V HSVCC Supply Curren wih Inacive Gae I HSVCCsup ma HSVCC Turn-On Threshold HSVCC Turn-Off Threshold HSVCC Turn-On/Off Hyseresis V HSVCCon V HSVCCoff V HSVCChys V V V Wih reference o High Side Ground HSGND Preliminary Daashee Version March 2009

23 Elecrical Characerisics PFC Secion PFC Curren Sense (PFCCS) Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Turn-Off Threshold V PFCCSoff V Duraion of Overcurren for urn-off PFCCSoff ns Spike Blanking blanking ns PFCCS Bias Curren I PFCCSbias µa V PFCCS = 1.5V PFC Zero Curren Deecor (PFCZCD) Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Zero Crossing Upper Threshold V PFCZCDup V Zero Crossing Lower Threshold V PFCZCDlow V Zero Crossing Hyseresis V PFCZCDhys 1.0 V Clamping of Posiive Volages V PFCZCDpclp V I PFCZCD = 4mA Clamping of Negaive Volages V PFCZCDnclp V I PFCZCD = 4mA PFCZCD Bias Curren I PFCZCDbias µa V PFCZCD = 1.7V PFCZCD Ringing Suppression Time ringsup ns PFC Bus Volage Sense (PFCVS) Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Trimmed Reference Volage V PFCVSref V Overvolage Upper Deecion Limi V PFCVSup V Overvolage Lower Deecion Limi V PFCVSlow V Overvolage Hyseresis V PFCVShys mv Undervolage Deecion Limi V PFCVSuv V Undervolage Shu Down V PFCVSsd V Bias Curren (ESD-Sress<1KV) I PFCVSbias -1 1 µa V PFCVS = 2.5V Bias Curren (ESD-Sress>1KV) I PFCVSbias µa V PFCVS = 2.5V Preliminary Daashee Version March 2009

24 Elecrical Characerisics PFC PWM Generaion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Iniial On-Time PFCon-iniial µs V PFCZCD = 0V Max. On-Time PFCon-max µs 0.45V < V PFCVS < 2.45V Repeiion Time when missing Zero PFCrep µs V PFCZCD = 0V Crossing Off-ime when missing ZCD Signal PFCoff µs V PFCZCD = 0V PFC Gae Drive (PFCGD) Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. PFCGD Low Volage V PFCGDlow V I PFCGD = 5mA V I PFCGD = 20mA V I PFCGD = -20mA PFCGD High Volage V PFCGDhigh V I PFCGD = -20mA 9.0 V I PFCGD = -1mA V VCC = V VCCoff + 0.3V 8.5 V I PFCGD = -5mA V VCC = V VCCoff + 0.3V PFCGD Volage Acive Shu Down V PFCGDsd V I PFCGD = 20mA V VCC = 5V PFCGD Peak Source Curren I PFCGDsource 100 ma R load = 4Ω + C Load = 3.3nF PFCGD Peak Sink Curren I PFCGDsink -500 ma R load = 4Ω + C Load = 3.3nF PFCGD Rise Time 2V < V LSGD < 8V PFCGD Fall Time 8V > V LSGD > 2V PFCGDrise ns R load = 4Ω + C Load = 3.3nF PFCGDfall ns R load = 4Ω + C Load = 3.3nF The parameer is no subjec o producion es - verified by design/characerizaion Preliminary Daashee Version March 2009

25 Elecrical Characerisics Inverer Secion Inverer Conrol (RFRUN, RFPH, RTPH) Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Fixed Sar-Up Frequency F sarup khz Duraion of Sof Sar, shif F from Sar-Up o Preheaing Frequency sofsar ms Preheaing Frequency F RFPH khz R RFPH = 10kΩ R RFRUN = 10kΩ Run Frequency F RFRUN khz R RFRUN = 10kΩ Preheaing Time RTPH ms R RTPH = 8.06kΩ Preheaing Time RTPH ms R RTPH = 806Ω Curren Source Preheaing Time I RTPH µa Min. Duraion of Igniion, shif F from Preheaing o Run Frequency Max. Duraion of Igniion, shif F from Preheaing o Run Frequency Duraion of Pre-Run, ime period afer operaing frequency has reached Run Frequency firs ime afer igniion Minimum Duraion of faul condiion by EOL2, Cap.Load 1, Open filamen and Overvolage for enering lached Faul Mode Minimum Duraion of faul condiion by EOL1, Cap.Load 2 for enering lached Faul Mode IGNITION ms NOIGNITION ms PRERUN ms CAPLOAD ms CAPLOAD µs The parameer is no subjec o producion es - verified by design/characerizaion Inverer Low Side Curren Sense (LSCS) Parameer Symbol Limi Values Uni Tes Condiion Curren Limi Threshold during Igniion Mode Duraion of Curren above Threshold for enabling Frequency Increase min. yp. max. V LSCSlimi V LSCSlimi ns Overcurren Shu Down Threshold V LSCSovc V Duraion of Overcurren for enering Lached Faul Mode LSCSovc ns Bias Curren LSCS I LSCSbias µa V LSCS = 1.5V Inverer Dead Time beween LS off and HS on deadime µs Preliminary Daashee Version March 2009

26 Elecrical Characerisics Resar afer Lamp Removal (RES) Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Low-side Open Filamen Threshold V RESofil V Capaciive Load Deecion Threshold V REScap V Discharge Resisor during Lached R RESdisch kω Faul Mode I1 Curren Source I RES µa V RES =1V; LVS=5µA I2 Curren Source I RES µa V RES =2V; LVS=5µA I3 Curren Source I RES µa V RES =1V; LVS=50µA I4 Curren Source I RES µa V RES =2V; LVS=50µA C1 Comparaor Threshold V RESC V C2 Comparaor Threshold V RESC V C3 Comparaor Threshold V RESC V Lamp Volage Sense (LVS) Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Source Curren before Sar Up I LVSsource µa 11 < V VCC < 13V V LVS = 0V Threshold for enabling Lamp V LVSenable V 11 < V VCC < 13V Monioring Sink Curren Threshold for Lamp I LVSsink µa V LVS > V VCC Deecion Posiive EOL Curren Threshold I LVSpEOLAC µa T > 0 C, AC inpu Negaive EOL Curren Threshold I LVSnEOLAC µa T > 0 C, AC inpu EOL Curren Threshold I LVSEOLDC +/-145 +/-175 +/-210 µa T > 0 C, DC inpu Maximum Raio beween posiive and negaive Curren Ampliude RO LVSmax I LVSsourpeak =150µA I LVSsinkpeak = increasing Minimum Raio beween posiive and negaive Curren Ampliude RO LVSmin I LVSsinkpeak =150µA I LVSsourcepeak = increasing Posiive Clamping Volage I LVSclmp - V VCC + 1V - V I LVS = 300µA Preliminary Daashee Version March 2009