Packages R VBUS1 R SUPPLY R CPH C VBUS VBUS 1 HO 16 R VBUS C PH CPH 2 VCO 3 IRS2168D R RPH FMIN VCC 13 FMIN 4 C COMP COM 12 COMP 5 R 1 LO 11 R GPFC

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1 Feaures PFC, ballas conrol and 600 V half-bridge driver in one IC Criical-conducion mode boos-ype PFC Programmable PFC over-curren proecion Programmable half-bridge over-curren proecion Programmable prehea frequency Programmable prehea ime Programmable igniion ramp Programmable run frequency Closed-loop igniion curren regulaion ohs complian Descripion The IS2168D is a fully inegraed, fully proeced 600 V ballas conrol IC designed o drive all ypes of fluorescen lamps. The IS2168D is based on he popular I2166 conrol IC wih addiional improvemens o increase ballas performance. The PFC circuiry operaes in criical conducion mode and provides high PF, low THD and DC bus regulaion. The IS2168D feaures include programmable prehea and run frequencies, programmable prehea ime, programmable PFC over-curren proecion, closed-loop half-bridge igniion curren regulaion, and programmable end-of-life proecion. Comprehensive proecion feaures such as proecion from failure of a lamp o srike, filamen failures, end-of-life proecion, DC bus undervolage rese as well as an auomaic resar funcion, have been included in he design. Daa Shee No. PD60310 IS2168D(SPbF ADVANCED PFC + BALLAST CONTOL IC Fixed inernal 1.6 µs HO and deadime Volage-conrolled oscillaor (VCO End-of-life window comparaor pin Inernal 65-even curren sense up/down faul couner DC bus undervolage rese Lamp removal/auo-resar shudown pin Inernal boosrap MOSFET Inernal 15.6 V Zener clamp diode on V cc Micropower sarup (250 µa Lach immuniy and ESD proecion Sysem Feaures One-chip ballas conrol soluion Wide range PFC for universal inpu and muli-lamp ballass Ulra low THD Closed-loop igniion regulaion for reliable lamp igniion End-of-Life window comparaor wih inernal OTA Lamp removal/auo-resar funcion Faul couner for robus noise immuniy Brown-ou proecion and rese Inernal boosrap MOSFET Packages 16-Lead PDIP IS2168DPbF 16-Lead SOIC IS2168DSPbF Applicaion Diagram (Typical Only + ecified AC Line D BUS VBUS1 SUPPLY C VBUS CPH VBUS 1 HO 16 GHS M1 M3 C BUS + VBUS C PH C VCO PH FMIN C COMP 1 GPFC CPH 2 VCO 3 FMIN 4 COMP 5 ZX 76 PFC 7 IS2168D VS 15 C BOOT VB COM C 1 C 2 GLS 3 M2 CBCK L ES C SNUB D CP D CP2 8 C ES 2 OC 8 9 SD/EOL D 1 5 OC C OC C SD1 C C SD2 D 2 D 3 C EOL 9 - ecified AC Line * Please noe ha his daashee conains advanced informaion ha could change before he produc is released o producion. Page 1

2 Absolue Maximum aings Absolue maximum raings indicae susained limis beyond which damage o he device may occur. All volage parameers are absolue volages referenced o COM, all currens are defned posiive ino any lead. The hermal resisance and power dissipaion raings are measured under board mouned and sill air condiions. Symbol Definiion Min. Max. Unis V B V B pin high-side floaing supply volage V S V S pin high-side floaing supply offse volage V B 25 V B V HO HO pin high-side floaing oupu volage V S V B V V PFC I O, MAX pin low-side oupu volage PFC gae driver oupu volage -0.3 V CC Maximum allowable oupu curren (HO,, PFC due o exernal power ransisor miller effec I CC V CC curren (see Noe V BUS V CPH V COMP V ZX V OC V SD/EOL V VBUS pin volage CPH pin volage COMP pin volage ZX pin volage OC pin volage SD/EOL pin volage pin volage V ma -0.3 V CC V V VCO VCO pin volage V I CPH I VCO I FMIN I COMP I ZX I OC I SD/EOL I CPH pin curren VCO pin curren FMIN pin curren COMP pin curren ZX pin curren OC pin curren SD/EOL pin curren pin curren -5 5 ma dv/d Allowable V S pin offse volage slew rae V/ns P D θja Package power T A +25 ºC (16-Pin DIP PD = (T JMAX -T A / θja (16-Pin SOIC Thermal resisance, juncion o ambien (16-Pin DIP (16-Pin SOIC T J Juncion emperaure T S Sorage emperaure T L Lead emperaure (soldering, 10 seconds Noe 1: This IC conains a Zener clamp srucure beween he chip V CC and COM which has a nominal breakdown volage of 15.6 V. This supply pin should no be driven by a DC, low impedance power source greaer han he V CLAMP specified in he Elecrical Characerisics secion. W ºC/W ºC Page 2

3 ecommended Operaing Condiions For proper operaion he device should be used wihin he recommended condiions. Symbol Definiion Min. Max. Unis V B -V S High-side floaing supply volage V BSUV+ V CLAMP V S Seady sae high-side floaing supply offse volage V V CC Supply volage V CCUV+ V CLAMP I CC V CC supply curren Noe 2 10 I SD/EOL SD/EOL pin curren I I OC pin curren OC pin curren -1 1 ma I ZX ZX pin curren V VCO VCO pin volage 0 5 V FMIN FMIN pin programming resisor kω T J Juncion emperaure ºC Noe 2: Enough curren should be supplied ino he V CC pin o keep he inernal 15.6 V Zener clamp diode on his pin regulaed a is volage, V CLAMP. Elecrical Characerisics V CC = V BS = V BIAS =14 V +/ V, C = C HO = C PFC = 1000 pf, FMIN = 42.2 kω, PH = N/C, V CPH = V VCO = 0 V, V SD/EOL = V COMP = V = V OC = V BUS = V ZX = 0 V, T A =25 o C unless oherwise specified. Symbol Definiion Min Typ Max Unis Tes Condiions Supply Characerisics V CCUV + V CCUV - V CC supply undervolage posiive going hreshold V CC supply undervolage negaive going hreshold V CC rising from 0 V V V CC falling from 14 V V UVHYS V CC supply undervolage lockou hyseresis I QCCUV UV mode V CC quiescen curren µa V CC = 8 V I QCCFLT V CC quiescen curren in faul mode MODE=FAULT I CCUN un mode V CC supply curren ma MODE = UN V BUS =4 V D/EOL=1 nf PFC off ime = 5 µs V CLAMP V CC Zener clamp volage V I CC = 10 ma Floaing Supply Characerisics I BS V BS supply curren ma MODE=PEHEAT V BSUV+ V BSUV- V BS supply undervolage posiive going hreshold V BS supply undervolage negaive going hreshold V BS rising from 0 V V V BS falling from 14 V I LKVS V S offse supply leakage curren µa V B = V S = 600 V Page 3

4 Elecrical Characerisics (con d V CC = V BS = V BIAS =14 V +/ V, C = C HO = C PFC = 1000 pf, FMIN = 42.2 kω, PH = N/C, V CPH = V VCO = 0 V, V SD/EOL = V COMP = V = V OC = V BUS = V ZX = 0 V, T A =25 o C unless oherwise specified. Symbol Definiion Min Typ Max Unis Tes Condiions PFC Error Amplifier Characerisics I COMP, SOUCE I COMP, SINK COMP pin OTA error amplifier oupu curren Sourcing COMP pin OTA error amplifier oupu curren Sinking µa MODE = UN V VBUS = 3.5 V V COMP=4.0 V MODE = UN V VBUS = 4.5 V V COMP=4.0 V V COMPOH OTA error amplifier oupu volage swing (high sae V BUS=3.5 V I COMP=I COMPSOUCE-5 µa V COMPOL OTA error amplifier oupu volage swing (low sae V V BUS=5.0 V I COMP=I COMPSINK+5 µa V COMPFLT OTA error amplifier oupu volage in faul mode V BUS=4.0 V PFC Conrol Characerisics V VBUSEG V BUS inernal reference volage V VBUSOV V BUS overvolage comparaor hreshold V COMP = 4.0 V V VBUSOV- V BUS overvolage faul rese hreshold V V ZX ZX pin hreshold volage V ZXHYS ZX pin comparaor hyserisis mv V ZXclamp ZX pin clamp volage (high sae V I ZX = 1 ma BLANK OC pin curren-sensing blank ime ns V BUS=4.0 V V COMP=4.0 V WD PFC wach-dog pulse inerval µs ZX = 0, V COMP = 4.0 V PFC Proecion Circuiry Characerisics V VBUSUV- V BUS pin undervolage rese hreshold V OCTH+ OC pin over-curren sense hreshold V V BUS=V COMP=4.0 V Page 4

5 Elecrical Characerisics (con d V CC = V BS = V BIAS =14 V +/ V, C = C HO = C PFC = 1000 pf, FMIN = 42.2 kω, PH = N/C, V CPH = V VCO = 0 V, V SD/EOL = V COMP = V = V OC = V BUS = V ZX = 0 V, T A =25 o C unless oherwise specified. Symbol Definiion Min Typ Max Unis Tes Condiions Ballas Conrol Oscillaor Characerisics f OSC, UN Half-bridge oscillaor run frequency MODE = UN khz PH = 42.2 kω, f OSC, PH Half-bridge oscillaor prehea frequency MODE = PEHEAT D Oscillaor duy cycle % d, oupu deadime d, HO HO oupu deadime µs V FMIN F MIN pin volage V V CC = 14.0 V Ballas Conrol Prehea, Igniion and un Mode Characerisics V CPHEOP+ CPH pin end of prehea rising hreshold volage CPH pin sar of igniion falling hreshold V CPHSOI volage V V VCOPH VCO pin prehea mode volage MODE = PEHEAT V VCOIGN VCO pin igniion mode volage --- I VCOIGN VCO pin igniion regulaion discharge curren (Open Drain ma MODE = IGNITION, V < V TH+ MODE = IGNITION, V VCO = 1 V, V > V TH+ V CPHUN+ CPH pin run mode rising hreshold volage MODE = IGNITION V (Open V VCOUN VCO pin run mode volage MODE = UN Drain Ballas Conrol Proecion Circuiry Characerisics V TH+ pin over-curren sense hreshold V n EVENTS pin faul couner number of evens V SDTH+ SD pin rising non-lached shudown hreshold volage V SDTH- SD pin falling rese hreshold volage V EOLBIAS EOL pin inernal bias volage V EOLTH+ V EOLTH- EOL pin rising lached shudown hreshold volage EOL pin falling lached shudown hreshold volage MODE = PEHEAT or UN MODE = UN I EOL, SOUCE EOL pin OTA oupu sourcing curren I EOL, SINK EOL pin OTA oupu sinking curren V µa MODE = UN MODE = PEHEAT V EOL = 1.5 V MODE = PEHEAT V EOL = 2.5 V V CPHFLT V VCOFLT V FMINFLT CPH pin faul mode volage VCO pin faul mode volage FMIN pin faul mode volage V MODE = FAULT Page 5

6 Elecrical Characerisics (con d V CC = V BS = V BIAS =14 V +/ V, C = C HO = C PFC = 1000 pf, FMIN = 42.2 kω, PH = N/C, V CPH = V VCO = 0 V, V SD/EOL = V COMP = V = V OC = V BUS = V ZX = 0 V, T A =25 o C unless oherwise specified. Gae Driver Oupu Characerisics (HO, and PFC pins V OL Low-level oupu volage --- COM --- V OH High-level oupu volage --- V CC --- r Turn-on rise ime f Turn-off fall ime V ns I 0+ Source curren I 0- Sink curren ma Boosrap FET Characerisics V B/ON V B when he boosrap FET is on V I B/CAP V B source curren when FET is on C BS=0.1 µf ma I B/10V V B source curren when FET is on V B=10 V Page 6

7 Schemaic Block Diagram 13 COM V VCO 3 Oscillaor I FMIN Driver and Deadime Logic Boosrap Conrol High- Side Driver 14 VB 16 HO FMIN 4 I FMIN = CPH 2 2V 2.0V FMIN Mode Logic PH IGN 65 Even Faul Couner OUT IN Igniion egulaion Low- Side Driver 1.2V 15 VS UN UV Faul Logic 3V 2V +/-10uA 1V OC VBUS COMP V 200ns Blank Time 4.0V Gain OTA1 4.3V OVP 5V 3V 1M 9 SD/EOL Ballas Conrol PFC Conrol 7 PFC S Q Q ZX 6 6.5V 3V 2V S Q Q VBUS Under-Volage ese S 1 2 Q Q 400us Wachdog Timer Please Noe: All values shown in block diagram are ypical values only. Page 7

8 Sae Diagram Power Turned On SD/EOL > 5.0 V (V SDTH+ (Lamp emoval or V CC < 10.5 V (V CCUV- (Power Turned Off UV Mode 1 / 2 -Bridge Off I QCCUV 250 µa CPH = 0 V VCO = 0 V PFC Off V CC > 12.5 V (V CCUV+ and SD/EOL < 3.0 V (V SDTH- SD/EOL > 5.0 V (V SDTH+ (Lamp Faul or Lamp emoval V CC < 10.5V (V CCUV- (V CC Faul or Power Down FAULT Mode Faul Lach Se 1 / 2 -Bridge Off I QCCFLT 400 µa CPH = 0 V V CC = 15.6V V CO = 0 V PFC Off > 1. 2V (V TH+ for 65 evens (n EVENTS PEHEAT Mode 1 / 2 -Bridge f PH V CO = 0 V PH // FMIN CPH charging hrough CPH PFC Enabled (High Gain C S Faul Couner Enabled CPH discharged o CPHSOI- CPH > 9.3 V (V CPHEOP+ (End of PEHEAT Mode egulaion VCO discharged slighly wih 0.6 ma curren sink (IV COIGN C S <1.2 V (V TH+ >1.2 V (V TH- > 1.2 V (VTH+ for 65 evens (nevents or SD/EOL < 1.0 V (V EOLTH- or SD/EOL > 3.0 V (V EOLTH+ IGNITION Mode CPH charging hrough CPH VCO ramping up hrough PH f PH ramps o f UN PFC = High Gain Mode Faul Couner Disabled Igniion egulaion Enabled CPH > 9.3 V (V CPHUN (End of IGNITION Mode UN Mode VCO = 2 V 1/2-Bridge UN EOL Thresholds Enabled PFC = Low Gain Mode V BUS UV Threshold Enabled C S Faul Couner Enabled Igniion egulaion Disabled CPH < 4.9 V (V CPHSOI- (Sar of IGNITION Mode V BUS < 3.0 V (V BUSUV- Discharge V CC o UV All values are ypical. Please refer o applicaion diagram on page 1. Page 8

9 Lead Assignmens & Definiions VBUS CPH VCO FMIN COMP ZX PFC OC IS2168D HO VS VB COM SD/EOL Pin # Symbol Descripion VBUS CPH VCO FMIN COMP ZX PFC OC SD/EOL COM VB VS HO DC bus sensing inpu Prehea iming inpu Volage conrolled oscillaor/igniion ramp inpu Oscillaor minimum frequency seing PFC error amplifier compensaion PFC zero-crossing deecion PFC gae driver oupu PFC curren sensing inpu Shudown/end of life sensing inpu Half-Bridge curren sensing inpu Low-side gae driver oupu IC power & signal ground Logic & low-side gae driver supply High-side gae driver floaing supply High volage floaing reurn High-side gae driver oupu Page 9

10 Timing Diagrams Ballas Secion 15.6V UV+ UV- CPH (2/3* (1/3* 2V VCO AMP = PH *C VCO FEQ f ph (FMIN//PH f run (FMIN SD HO, 1.25V UV FAULT SD > 5V PH IGN PH IGN UN UV HO HO HO 1.25V Page 10

11 I. Ballas Secion Funcional Descripion V C1 C DISCHAGE INTENAL ZENE CLAMP VOLTAGE Undervolage Lockou Mode (UV The undervolage lockou mode (UV is defined as he sae he IC is in when V CC is below he urn-on hreshold of he IC. To idenify he differen modes of he IC, refer o he Sae Diagram shown on page 3 of his documen. The IS2168D undervolage lockou is designed o mainain an ulra low supply curren of 250 µa (I QCCUV, and o guaranee he IC is fully funcional before he high- and low-side oupu drivers are acivaed. Figure 1 shows an efficien supply volage using he micro-power sar-up curren of he IS2168D ogeher wih a snubber charge pump from he half-bridge oupu (, C 1, C 2, C SNUB, D CP1 and D CP2. V ECT (+ V BUS (+ V BUS (- IC COM BSFET CONTOL IS2168D BSFET HO HO 16 MHS VS VB COM C 3 C BS 2 C 1 C 2 1 MLS D CP2 Figure 1: Sar-up and supply circuiry C SNUB D CP1 To Load Load eurn The V CC capaciors (C 1 and C 2 are charged by he curren hrough supply resisor ( minus he sar-up curren drawn by he IC. This resisor is chosen o se he desired AC line inpu volage urn-on hreshold for he ballas. When he volage a V CC exceeds he IC sar-up hreshold (V CCUV+ and he SD pin is below 3.0 V (V SDTH -, he IC urns on and begins o oscillae. The capaciors a V CC begin o discharge due o he increase in IC operaing curren (Fig. 2. The high-side supply volage, V B- V S, begins o increase as capacior C BS is charged hrough he inernal boosrap MOSFET during he onime of each swiching cycle. When he V B- V S volage exceeds he high-side sar-up hreshold (V BSUV+, HO hen begins o oscillae. This may ake several cycles of o charge V B -V S above V BSUV+ due o DSon of he inernal boosrap MOSFET. V UV+ V UV- VHYST & C 1,2 TIME CONSTANT DISCHAGE TIME CHAGE PUMP OUTPUT Figure 2: V CC supply volage When and HO are boh oscillaing, he exernal MOSFETs (MHS and MLS are urned on and off wih a 50% duy cycle and a non-overlapping deadime of 1.6 µs ( d. The half-bridge oupu (pin V S begins o swich beween he DC bus volage and COM. During he deadime beween he urn-off of and he urn-on of HO, he half-bridge oupu volage ransiions from COM o he DC bus volage a a dv/d rae deermined by he snubber capacior (C SNUB. As he snubber capacior charges, curren will flow hrough he charge pump diode (D CP2 o V CC. Afer several swiching cycles of he halfbridge oupu, he charge pump and he inernal 15.6 V Zener clamp of he IC ake over as he supply volage. Capacior C 2 supplies he IC curren during he V CC discharge ime and should be large enough such ha V CC does no decrease below UV- before he charge pump akes over. Capacior C 1 is required for noise filering and mus be placed as close as possible and direcly beween V CC and COM, and should no be lower han 0.1 µf esisors 1 and 2 are recommended for limiing high currens ha can flow o V CC from he charge pump during hard-swiching of he half-bridge or during lamp igniion. The inernal boosrap MOSFET and supply capacior (C BS comprise he supply volage for he high side driver circuiry. During UV mode, he high- and low-side driver oupus HO and are boh low, he inernal oscillaor is disabled, and pin CPH is conneced inernally o COM for reseing he prehea ime. Page 11

12 Prehea Mode (PH The IS2168D eners prehea mode when V CC exceeds he UV posiive-going hreshold (V CCUV+. The inernal MOSFET ha connecs pin CPH o COM is urned off and an exernal resisor (Fig. 3 begins o charge he exernal prehea iming capacior (C PH. and HO begin o oscillae a a higher sof-sar frequency and ramp down quickly o he prehea frequency. The VCO pin is conneced o COM hrough an inernal off and resisor PH is disconneced from COM. The equivalen resisance a he FMIN pin increases from he parallel combinaion ( PH // FMIN o FMIN a a rae programmed by he exernal capacior a pin VCO (C VCO and resisor PH. This causes he operaing frequency o ramp down smoohly from he prehea frequency hrough he igniion frequency o he final run frequency. During his igniion ramp, he frequency sweeps hrough he resonance frequency of he lamp oupu sage o ignie he lamp. V CPH V BUS (+ 2/3*V CC CPH C PH CPH 3 HO MODE 16 MHS 1/3*V CC C VCO PH VCO 4 M1 Half- Bridge Oupu I AD Half- Bridge Driver VS 15 PH = CPH * C PH FMIN 5 FMIN OSC. 11 MLS V VCO 2V 10 3 AMP = PH * C VCO IS2168D C PEHEAT IGNITION UN 12 COM Load eurn Figure 4: C PH and VCO iming diagram V BUS (- V BUS (+ Figure 3: Prehea circuiry MOSFET M1 so he prehea frequency is deermined by he equivalen resisance a he FMIN pin formed by he parallel combinaion of resisors FMIN and PH. The frequency remains a he prehea frequency unil he volage on pin C PH exceeds approvixmaely 2/3*V CC (V CPHEOP+ and he IC eners Igniion Mode. During prehea mode, he over-curren proecion on pin and he 65-cycle (n EVENTS consecuive over-curren faul couner are boh enabled. The PFC circui is working in high-gain mode (see PFC secion and keeps he DC bus volage regulaed a a consan level. CPH C PH C VCO PH FMIN CPH VCO FMIN IGN. EG. IS2168D MODE 16 M1 OSC. Half- Bridge Oupu Half- Bridge Driver V HO VS 3 C MHS MLS 12 COM I AD Load eurn Igniion Mode (IGN The IS2168D igniion mode is defined by he second ime C PH charges from 1/3*V CC (V CPHSOI- o 2/3*V CC (V CPHUN+. When he volage on pin CPH exceeds 2/3*V CC (V CPHUN+ for he firs ime, pin CPH is discharged quickly hrough an inernal MOSFET down o 1/3*V CC (V CPHSO I - (see Figs. 4 and 5. The inernal MOSFET urns off and he volage on pin C PH begins o increase again. The inernal MOSFET M1 a pin V CO urn V BUS (- Figure 5: Igniion circuiry The over-curren hreshold on pin will proec he ballas agains a non-srike or open-filamen lamp faul condiion. The volage on pin is defined by he lower half-bridge MOSFET curren flowing hrough he exernal curren sensing resisor. This resisor programs he maximum peak igniion curren (and herefore peak Page 12

13 igniion volage of he ballas oupu sage. Should his volage exceed he inernal hreshold of 1.2 V (V TH+, he igniion regulaion circui conrols he volage on he VCO pin o increase he frequency slighly (see Fig. 6. This cycle-by-cycle feedback from he C S pin o he VCO pin will adjus he frequency each cycle o limi he ampliude of he curren for he enire duraion of igniion mode. VOUT HO VCPH VS V PH IGN 1.25V AMP Figure 7: Ballas oupu volage and CPH pin during prehea and igniion wih deacivaed lamp, ime span 100ms V VCO 2V VOUT Figure 6: Igniion regulaion iming diagram When C PH exceeds 2/3*V CC (V CPHUN+ for he second ime, he IC eners run mode and he faul couner becomes enabled. The igniion regulaion disabled in run mode bu he IC will ener faul mode afer 65 (n EVENTS consecuive over-curren fauls and gae driver oupus HO, and PFC will be lached low. The oupu volage of he ballas will increase during he igniion ramp AMP because he frequency ramp down from he prehea frequency o he igniion frequency and will be consan during igniion because he igniion regulaion circui will regulae he ampliude of he curren for he enire duraion of he igniion ime IGN (Figs. 7 and 8. VCPH AMP Figure 8: Ballas oupu volage and CPH pin during prehea and igniion wih deacivaed lamp, ime span 50ms IGN During igniion mode, he PFC circui is working in highgain mode and keeps he DC bus volage regulaed a a consan level. The high-gain mode is necessary o preven he DC bus from decreasing during lamp igniion or igniion regulaion. Also during igniion mode, he SD/EOL faul is disabled. Page 13

14 un Mode (UN Once V CC has exceeded 2/3*V CC (V CPHUN+ for he second ime, he IC eners run mode. CPH coninues o charge up o V CC. The operaing frequency is a he minimum frequency (afer he igniion ramp and is programmed by he exernal resisor ( FMIN a he FMIN pin. Should hard-swiching occur a he half-bridge a any ime (open-filamen, lamp removal, ec., he volage across he curren sensing resisor ( will exceed he inernal hreshold of 1.2 V (V TH+ and he faul couner will begin couning (see Fig. 5. Should he number of consecuive over-curren fauls exceed 65 (n EVENTS, he IC will ener faul mode and he HO, and PFC gae driver oupus will be lached low. During run mode, he end-of-life (EOL window comparaor and he DC bus undervolage rese are boh enabled. DC Bus Undervolage ese Should he DC bus decrease oo low during a brown-ou line condiion or over-load condiion, he resonan oupu sage o he lamp can shif near or below resonance. This can produce hard swiching a he half- bridge ha can damage he half-bridge swiches, or, he DC bus can decrease oo far and he lamp can exinguish. To proec agains his, he V BUS pin includes a 3.0 V undervolage rese hreshold V BUSUV-. When he IC is in run mode and he volage a he V BUS pin decreases below 3.0 V (V BUSUV-, V CC will be discharged hrough an inernal MOSFET down o he V CCUV- hreshold and all gae driver oupus will be lached low. For proper ballas design, he designer should se he over-curren limi of he PFC secion such ha he DC bus does no drop unil he AC line inpu volage falls below he minimum raed inpu volage of he ballas (see PFC secion. When he PFC over-curren limi is correcly se, he DC bus volage will sar o decrease when over-curren is reached during low-line condiions. The volage measured a he V BUS pin will decrease below he inernal 3.0 V hreshold V BUSUVand he ballas will urn off cleanly. The pull-up resisor o V CC ( will hen urn he ballas on again when he AC inpu line volage increases high enough again where V CC exceeds V CCUV+. should be se o urn he ballas on a he minimum specified ballas inpu volage and he PFC over-curren should be se somewhere below his level. This hyseresis will resul in clean urn-on and urnoff of he ballas. SD/EOL and Faul Mode Should he volage a he SD/EOL pin exceed 3.0 V (V EOLTH+ or decrease below 1.0 V (V EOLTH- during run mode, an end-of-life (EOL faul condiion has occurred and he IC eners faul mode., HO and PFC gae driver oupus are all lached off in he low sae. CPH is discharged o COM for reseing he prehea ime and VCO is discharged o COM for reseing he frequency. To exi faul mode, V CC can be decreased below V CCUV- (ballas power off or he SD pin can be increased above 5.0 V (V SDTH+ (lamp removal. Eiher of hese will force he IC o ener UV mode (see Sae Diagram, page 3. Once V CC is above V CCUV+ (ballas power on and SD is pulled above 5.0 V (V SDTH+ and back below 3.0 V (V SDTH- (lamp re-inserion, he IC will ener prehea mode and begin oscillaing again. The curren sense funcion will force he IC o ener faul mode only afer he volage a he pin has been greaer han 1.2 V (V TH+ for 65 (n EVENTS consecuive cycles of. The volage a he pin is AND-ed wih (see Fig. 9 so i will work wih pulses ha occur during he on-ime or DC. If he over-curren fauls are no consecuive, hen he inernal faul couner will coun back down each cycle when here is no faul. Should an over-curren faul occur only for a few cycles and hen no occur again, he couner will evenually rese o zero. The over-curren faul couner is enabled during prehea and run modes and disabled during igniion mode. 1.25V 50 Cycles un or Prehea Mode Faul Mode Figure 9: Faul couner iming diagram Page 14

15 II. PFC Secion Funcional Descripion V, I In mos elecronic ballass i is necessary o have he circui ac as a pure resisive load o he AC inpu line volage. The degree o which he circui maches a pure resisor is measured by he phase shif beween he inpu volage and inpu curren and how well he shape of he inpu curren waveform maches he shape of he sinusoidal inpu volage. The cosine of he phase angle beween he inpu volage and inpu curren is defined as he power facor (PF, and how well he shape of he inpu curren waveform maches he shape of he inpu volage is deermined by he oal harmonic disorion (THD. A power facor of 1.0 (maximum corresponds o zero phase shif and a THD of 0% and represens a pure sinusoidal waveform (no disorion. For his reason i is desirable o have a high PF and a low THD. To achieve his, he IS2168D includes an acive power facor correcion (PFC circui. The conrol mehod implemened in he IS2168D is for a boos-ype converer (Fig. 10 running in criicalconducion mode (CCM. This means ha during each swiching cycle of he PFC MOSFET, he circui wais unil he inducor curren discharges o zero before urning he PFC MOSFET on again. The PFC MOSFET is urned on and off a a much higher frequency (>10 khz han he line inpu frequency (50 o 60 Hz. (+ (- LPFC MPFC DPFC DC Bus + CBUS Figure 10: Boos converer circui When he swich M PFC is urned on, he inducor L PFC is conneced beween he recified line inpu (+ and (- causing he curren in L PFC o charge up linearly. When M PFC is urned off, L PFC is conneced beween he recified line inpu (+ and he DC bus capacior C BUS (hrough diode D PFC and he sored curren in L PFC flows ino C BUS. M PFC is urned on and off a a high frequency and he volage on C BUS charges up o a specified volage. The feedback loop of he IS2168D regulaes his volage o a fixed value by coninuously monioring he DC bus volage and adjusing he on-ime of M PFC accordingly. For an increasing DC bus he on-ime is decreased, and for a decreasing DC bus he on-ime is increased. This negaive feedback conrol is performed wih a slow loop speed and a low loop gain such ha he average inducor curren smoohly follows he low-frequency line inpu volage for high power facor and low THD. The on-ime of M PFC herefore appears o be fixed (wih an addiional modulaion o be discussed laer over several cycles of he line volage. Wih a fixed on-ime, and an off-ime deermined by he inducor curren discharging o zero, he resul is a sysem where he swiching frequency is free-running and consanly changing from a high frequency near he zero crossing of he AC inpu line volage, o a lower frequency a he peaks (Fig. 11. Figure 11: Sinusoidal line inpu volage (solid line, riangular PFC Inducor curren and smoohed sinusoidal line inpu curren (dashed line over one half-cycle of he AC line inpu volage When he line inpu volage is low (near he zero crossing, he inducor curren will charge up o a small amoun and he discharge ime will be fas resuling in a high swiching frequency. When he inpu line volage is high (near he peak, he inducor curren will charge up o a higher amoun and he discharge ime will be longer giving a lower swiching frequency. The PFC conrol circui of he IS2168D (Fig. 12 includes five conrol pins: V BUS, COMP, ZX, PFC and OC. The V BUS pin measures he DC bus volage via an exernal resisor volage divider. The COMP pin programs he on-ime of M PFC and he speed of he feedback loop wih an exernal capacior. The ZX pin deecs when he inducor curren discharges o zero each swiching cycle using a secondary winding from he P FC inducor. The P FC pin is he low-side gae driver oupu for he exernal MOSFET, M PFC. The OC pin senses he curren flowing hrough M PFC and performs cycle-by-cycle over-curren proecion. (+ (- VBUS1 VBUS2 VBUS VBUS COMP CCOMP LPFC PFC Conrol COM Figure 12: IS2168D simplified PFC conrol circui The V BUS pin is regulaed agains a fixed inernal 4.0 V reference volage for regulaing he DC bus volage (Fig. 13. The feedback loop is performed by an operaional ransconducance amplifier (OTA ha sinks or sources a curren o he exernal capacior a he COMP pin. The resuling volage on he COMP pin ses he hreshold for he charging of he inernal iming capacior (C1, Figure 13 and herefore programs he on-ime of M PFC. During prehea and igniion modes of he ballas secion, he gain of he OTA is se o a high level o raise he DC bus level quickly and o minimize he ransien on he DC bus ha can occur during igniion. During run mode, he gain is hen decreased o a lower level necessary for a slower ZX PFC OC ZX PFC DFPC MPFC OC CBUS Page 15

16 loop speed for achieving high power facor and low THD. On-ime Modulaion Circui VBUS 1 COMP 5 ZX 6 3.0V 5.1V un Mode Signal 4.0V COMP2 GAIN 2.0V OTA1 Discharge o UV- M1 C1 COMP3 4.3V M2 Faul Mode Signal COMP5 COMP4 S Q 1 2 Q S3 S S4 Q Q WATCH DOG TIME Figure 13: IS2168D deailed PFC conrol circui 1.2V 7 PFC 8 OC The off-ime of M PFC is deermined by he ime i akes he L PFC curren o discharge o zero. The zero curren level is deeced by a secondary winding on LPFC ha is conneced o he ZX pin hrough an exernal curren limiing resisor ZX. A posiive-going edge exceeding he inernal 2 V hreshold (V ZXTH+ signals he beginning of he off-ime. A negaive-going edge on he ZX pin falling below 1.7 V (V ZXTH+ - V ZXHYS will occur when he L PFC curren discharges o zero which signals he end of he off-ime and M PFC is urned on again (Fig. 14. The cycle repeas iself indefiniely unil he PFC secion is disabled due o a faul deeced by he ballas secion (Faul Mode, an over-volage or undervolage condiion on he DC bus, or, he negaive ransiion of ZX pin volage does no occur. Should he negaive edge on he ZX pin no occur, M PFC will remain off unil he wach-dog imer forces a urn-on of M PFC for an on-ime duraion programmed by he volage on he COMP pin. The wach-dog pulses occur every 400 µs ( WD indefiniely unil a correc posiive- and negaive-going signal is deeced on he ZX pin and normal PFC operaion is resumed. Should he OC pin exceed he 1.2 V (V OCTH+ over-curren hreshold during he on-ime, he PFC oupu will urn off. The circui will hen wai for a negaive-going ransiion on he ZX pin or a forced urn-on from he wach-dog imer o urn he PFC oupu on again. I LPFC PFC ZX 1.2V OC Figure 14: Inducor curren, PFC pin, ZX pin and OC pin iming diagram A fixed on-ime of M PFC over an enire cycle of he line inpu volage produces a peak inducor curren which naurally follows he sinusoidal shape of he line inpu volage. The smoohed averaged line inpu curren is in phase wih he line inpu volage for high power facor bu he oal harmonic disorion (THD, as well as he individual higher harmonics, of he curren can sill be oo high. This is mosly due o cross-over disorion of he line curren near he zero-crossings of he line inpu volage. To achieve low harmonics ha are accepable o inernaional sandard organizaions and general marke requiremens, an addiional on-ime modulaion circui has been added o he PFC conrol. This circui dynamically increases he on-ime of M PFC as he line inpu volage nears he zero-crossings (Fig. 15. This causes he peak L PFC curren, and herefore he smoohed line inpu curren, o increase slighly higher near he zerocrossings of he line inpu volage. This reduces he amoun of cross-over disorion in he line inpu curren which reduces he THD and higher harmonics o low levels. I LPFC PFC pin 0 0 near peak region of recified AC line near zero-crossing region of recified AC line Figure 15: On-ime modulaion circui iming diagram DC Bus Over-volage Proecion Should over-volage occur on he DC bus and he VBUS pin exceeds he inernal 4.3 V hreshold (V BUSOV+, he PFC oupu is disabled (se o a logic low. When he DC bus decreases again and he V BUS pin decreases below he inernal 4.15 V hreshold (V BUSOV-, a wach-dog pulse is forced on he PFC pin and normal PFC operaion is resumed. DC Bus Undervolage ese When he inpu line volage decreases, he on-ime of M PFC increases o keep he DC bus consan. The onime will coninue o increase as he line volage coninues o decrease unil he OC pin exceeds he inernal 1.2 V over-curren hreshold (V OCTH+. A his ime, he on-ime can no longer increase and he PFC can no longer supply enough curren o keep he DC bus fixed for he given load power. This will cause he DC bus o begin o decrease. The decreasing DC bus will cause he V BUS pin o decrease below he inernal 3.0 V hreshold (V BUSUV- (Fig Page 16

17 When his occurs, V CC is discharged inernally o UV. The IS2168D eners UV mode and boh he PFC and ballas secions are disabled. The sar-up supply resisor o V CC, ogeher wih he micro-power sar-up curren, should be se such ha he ballas urns on a an AC line inpu volage above he level a which he DC bus begins o drop. The curren-sensing resisor a he OC pin ses he maximum PFC curren and herefore ses he maximum on-ime of M PFC. This prevens sauraion of he PFC inducor and programs he minimum low-line inpu volage for he ballas. The micro-power supply resisor o V CC and he curren-sensing resisor a he OC pin program he on and off inpu line volage hresholds for he ballas. Wih hese hresholds correcly se, he ballas will urn off due o he 3.0 V undervolage hreshold (V BUSUV- on he V BUS pin, and on again a a higher volage (hyserisis due o he supply resisor o V CC. III. Ballas Design Equaions Noe: The resuls from he following design equaions can differ slighly from acual measuremens due o IC olerances, componen olerances, and oscillaor over- and under-shoo due o inernal comparaor response ime. Sep 1: Program un Frequency The run frequency is programmed wih he iming resisor FMIN a he FMIN pin. Use graph in Fig. 16 ( FMIN vs. Frequency o selec FMIN value for desired run frequency. Frequency (khz FMIN (kw Figure 16: f OSC vs FMIN Sep 2: Program Prehea Frequency The prehea frequency is programmed wih iming resisors FMIN and PH. The iming resisors are conneced in parallel for he duraion of he prehea ime. Use graph in Fig. 14 ( FMIN vs. Frequency o selec EQUIV value for desired prehea frequency. Then PH is given as: Sep 3: Program Prehea Time and Igniion Time The prehea ime is defined by he ime i akes for he exernal capacior on pin C PH o charge up o V CPHEOP+. An exernal resisor ( CPH conneced o V CC charges capacior C PH. The prehea ime is herefore given as: or PH CPH CPH [s] (2 PH CPH [F] (3 CPH The igniion ime is defined by he ime i akes for he exernal capacior on pin C PH o charge up he second ime from V CPHSOI- o V CPHUN. The igniion ime is herefore given as: IGN 0. 4 PH [s] (4 Sep 4: Program Igniion amp Time The igniion ramp ime is defined by he ime i akes for he exernal capacior on pin VCO o charge up o 2 V. The exernal iming resisor ( PH conneced o F MIN charges capacior C VCO. The igniion ramp ime is herefore given as: or AMP = PH C [s] (5 VCO AMP CVCO [F] (6 PH Sep 5: Program Maximum Igniion Curren The maximum igniion curren is programmed wih he exernal resisor and an inernal hreshold of 1.2 V (V TH+. This hreshold deermines he over-curren limi of he ballas, which will be reached when he frequency ramps down owards resonance during igniion and he lamp does no ignie. The maximum igniion curren is given as: or I IGN [A] (peak ( [Ω] (8 IIGN PH FMIN EQUIV = [Ω] (1 FMIN EQUIV Page 17

18 IV. PFC Design Equaions Sep1: Calculae PFC inducor value: L PFC = ( 8e 6 ( VBUS VACMS 2 VACMS η [H] (1 2 2 P OUT where, = DC bus volage VBUS VAC = Nominal rms AC inpu volage MS η = PFC efficiency (ypically 0.95 P OUT = Ballas oupu power Sep 2: Calculae peak PFC inducor curren: i PK 2 2 POUT = [A] (peak (2 VAC η MIN where, VAC = Minimum rms AC inpu volage MIN Noe: The PFC inducor mus no saurae a i PK over he specified ballas operaing emperaure range. Proper core sizing and air-gapping should be considered in he inducor design. Sep 3: Calculae PFC over-curren resisor OC value: 1.2 OC = [Ω] (3 ipk Sep 4: Calculae sar-up resisor value: VACMIN +10 PK = [Ω] (4 IQCCUV Page 18

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20 ADED TAPE FEED DIECTION B A H D F C NOTE : CONTOLLING DIMENSION IN MM E G CAIE TAPE DIMENSION FO 16SOICN Meric Imperial Code Min Max Min Max A B C D E F G 1.50 n/a n/a H F D E C B A G H EEL DIMENSIONS FO 16SOICN Meric Imperial Code Min Max Min Max A B C D E F n/a n/a G H Page 20

21 ODE INFOMATION 16-Lead PDIP IS2168DPbF 16-Lead SOIC IS2168DSPbF 16-Lead SOIC Tape & eel IS2168DSTPbF The SOIC-16 is MSL2 qualified. This produc has been designed and qualified for he indusrial level. Qualificaion sandards can be found a <hp:// I WOLD HEADQUATES: 233 Kansas S., El Segundo, California 90245, Tel: ( Daa and specificaions subjec o change wihou noice. 1/26/ Page 21