BTS SFA. Datasheet. Automotive. Smart High-Side Power Switch Dual Channel, 2x 4mΩ. High Current PROFET TM V2.0,

Transcription

1 Smar High-Side Power Swich Dual Channel, 2x 4mΩ Daashee V2.0, Auomoive

2 1 Overview Block Diagram and Terms Block Diagram Terms Pin Configuraion Pin Assignmen Pin Definiions and Funcions General Produc Characerisics Absolue Maximum Raings Funcional Range Thermal Resisance Package Funcional Descripion Power Sages Oupu On-Sae Resisance Oupu Timing Oupu Inducive Clamp Inverse Operaion Capabiliy Inpu Circui Proecion Funcions Infineon INTELLIGENT LATCH - faul acknowledge and lach rese Shor Circui and Overemperaure Proecion Reverse Polariy Proecion - ReverSave TM Undervolage shudown and resar Loss of Ground Proecion Loss of Load Proecion, Loss of VS Proecion Diagnosic Funcions Sense Enable Diagnosis during ON Elecrical characerisics Elecrical Characerisics Table Applicaion schemaic Hins for PCB layou Furher Applicaion Informaion Package Oulines Revision Hisory Daashee 1 V2.0,

3 Dual Channel, 2x 4mΩ 1 Overview Feaures 3.3 and 5V compaible, ground referenced CMOS compaible inpus for each channel Opimized elecromagneic compaibiliy (EMC) Very low sandby curren Slew rae configurable via exernal circuiry or signal Secure load urn-off while device ground disconneced ReverSave TM - Reverse baery proecion wihou exernal componens Inverse load curren capabiliy Infineon INTELLIGENT LATCH Green Produc (RoHS complian) and halogen free package AEC qualified PG-DSO Exended Supply Volage Range for Operaion V S(ex) 6..28V Logic Supply Volage V DD V Minimum power sage over-volage proecion V DS(CL)) 40 V Typical on-sae resisance a T j = 25 C (channel 0, 1) R DS(ON) 4.0 mω Maximum on-sae resisance a T j = 150 C (channel 0, 1) R DS(ON) 8.2 mω Typical nominal load curren per channel, boh channel acive I L(nom) 11 A Minimum shor circui shudown hreshold a T j = -40 C I L(SC) 130 A Maximum sand-by curren for whole device wih load for T j 85 C I S(OFF) 12 µa Descripion The is a dual channel high-side power swich in PG-DSO package providing embedded proecive funcions including ReverSave TM and Infineon INTELLIGENT LATCH. I is mos suiable for loads wih high inrush curren, such as glow plugs, PTC heaers, or lamps. The power ransisors are buil by a dual N-channel verical power MOSFET wih charge pump. The design is based on Smar power chip by chip echnology. The has ground referenced CMOS compaible inpus. ReverSave TM is a proecion feaure ha causes he power ransisor o swich on in case of reverse polariy. As a resul, he power dissipaion is reduced. Infineon INTELLIGENT LATCH ensures a lached swich-off and reporing in case of faul condiion. Type Package Marking PG-DSO S A Daashee 1 V2.0,

4 Overview Power Sage Four differen slew raes selecable via pin SRS0 and SRS1 Proecive Funcions Shor circui proecion wih lach Thermal shudown wih lach Infineon INTELLIGENT LATCH - rese able lach resuling from proecive swich-off ReverSave TM - Reverse baery proecion by self urn on of power MOSFET Inverse load curren capabiliy - Inverse operaion funcion Sable behavior a under volage on V S or V dd Over volage proecion (including load dump) Loss of ground proecion Loss of proecion (wih exernal diode for charged inducive loads) Elecrosaic discharge proecion (ESD) Diagnosic Funcions Muliplexed proporional load curren sense signal (IS) Seperae enable funcion for curren sense signal of each channel via pin SEN0 and SEN1 Provides analog sense signal of load curren in normal operaion mode Provides low signal in case of over emperaure and shor circui o ground Open load deecion in ON-sae by load curren sense Applicaions µc compaible high-side power swich wih diagnosic feedback for 12 V sysem grounded loads in auomoive applicaions All ypes of resisive, inducive and capaciive loads Mos suiable for loads wih high inrush currens, such as glow plugs, PTC heaers, or lamps Replaces elecromechanical relays, fuses and discree circuis Daashee 2 V2.0,

5 Block Diagram and Terms 2 Block Diagram and Terms 2.1 Block Diagram V dd IN1 IN0 SRS0 SRS1 SEN0 SEN1 conrol chip ESD proecion Logic supply driver logic analog supply gae conrol & charge pump over over curren swich-off over emperaure V ON( CL) V OUT(CL) channel 1 channel 0 power chip T T 1 0 OUT1 OUT0 IS load curren sense GND Overview.emf Figure 1 Block Diagram 2.2 Terms V S I S I dd V dd V dd I SRS0 SRS0 V SRS0 I SRS1 SRS1 V SRS1 I IN0 IN0 OUT0 I L0 V DS0 V IN0 V IN1 V SEN0 I IN1 I SEN0 I SEN1 IN1 SEN0 SEN1 OUT1 IS I L1 I IS V IS V DS1 V OUT 1 V OUT 0 V SEN1 GND R IS I GND Figure 2 Terms Terms.emf Daashee 3 V2.0,

6 Pin Configuraion 3 Pin Configuraion 3.1 Pin Assignmen GND GNDR IN0 IN1 IS NC GND OUT1 OUT1 OUT1 OUT1 OUT NC SEN1 SEN0 SRS0 SRS1 V dd GND OUT0 OUT0 OUT0 OUT0 OUT0 Pin_Descripion.vsd Figure 3 Pin Configuraion 3.2 Pin Definiions and Funcions Pin Symbol I/O Funcion 1, 7, 30 GND Ground; Ground connecion for conrol chip 1) 2 GNDR Ground reference; Needs o be conneced o GND. 3 IN0 I Inpu 0; acivaes channel 0. Has an inernal pull down resisor. 4 IN1 I Inpu 1; acivaes channel 1. Has an inernal pull down resisor. 5 IS O Sense Oupu; analog sense curren signal proporional o I L0 or I L1. 6, 36 NC No conneced; For handling of NC pins, please see Chaper , , Supply volage; Posiive power supply for power oupus 1) 11, 12, 13, 14, 15 OUT1 O Oupu of channel 1; power oupu 1 1) 22, 23, 24, 25, 26 OUT0 O Oupu of channel 0; power oupu 0 1) 31 Vdd Logic supply (5V) 32 SRS1 I Slew rae selecor pin 1. See secion Timings on Page 23 for seeings. 33 SRS0 I Slew rae selecor pin 0. See secion Timings on Page 23 for seeings. 34 SEN0 I Sense Enable for channel 0. See Table 1 Truh Table for Power Sages. 35 SEN1 I Sense Enable for channel 1. See Table 1 Truh Table for Power Sages. 1) All GND pins have o be conneced exernally. All pins have o be conneced exernally. All OUT pins of a channel have o be conneced exernally. Daashee 4 V2.0,

7 General Produc Characerisics 4 General Produc Characerisics 4.1 Absolue Maximum Raings Operaion ouside he parameers lised here may cause permanen damage o he device. Exposure o maximum raing condiions for exended periods may affec device reliabiliy Absolue Maximum Raings 1) Tj = -40 C o +150 C (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Max. Supply Volage Supply volage V S 0 28 V Logic supply volage V dd V Reverse polariy volage -V S(rev) 0 16 V 2) T j(0) = 25 C 2min Supply volage for shor circui proecion (single pulse) V ba(sc) 0 24 V 3) R SUPPLY =10mΩ L SUPPLY =5µH [R CABLE ; L CABLE ]= [20 mω; 0µH] or [50 mω; 5µH] Supply Volage for Load Dump proecion V S(LD) 40 V R I = 2 Ω 4), d =400 ms Curren hrough ground pin I GND ma 2min Curren hrough Vdd pin I dd ma 2min Inpu Pins Volage a digial inpu pins V DIO V IN0, IN1, SRS0, SRS1, SEN0, SEN Curren hrough digial inpu pins IN0, IN1, SRS0, SRS1, SEN0, SEN1 I DIO ma 2min Oupu Pins Volage a sense pin V IS V Curren hrough sense pin IS I IS 20 ma Power Sages Load curren 5) I L I L(SC) A Inducive load swich-off energy (single pulse) E AS 411 mj V S =13.5V 6) I L(0) =20A, T j(0) 150 C Inducive load swich-off energy (repeiive pulses) E AR 64 mj V S = 13.5V 7) I L(0) = 20A T j(0) 105 C Temperaures Juncion emperaure T j C Dynamic emperaure increase while ΔT j 60 K swiching Sorage emperaure T sg C Daashee 5 V2.0,

8 General Produc Characerisics Absolue Maximum Raings (con d) 1) Tj = -40 C o +150 C (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Max. ESD Suscepibiliy ESD suscepibiliy HBM all pins pins versus OUT ESD suscepibiliy CDM all pins Pin 1, 18, 19, 36 (corner pins) V ESD V ESD kv V 7) HBM 8) CDM 1) No subjec o producion es, specified by design. 2) A negaive baery volages (V S < 0V) logic pins can reach negaive poenials (V S V pin GND). In his case, oo high currens hrough affeced pins have o be avoided by means of series resisors. 3) Seup in accordance wih AEC Q and AEC Q ) V S(LD) is seup wihou he DUT conneced o he generaor per ISO and DIN R I is he inernal resisance of he Load Dump pulse generaor 5) Shor circui shudown is a proecion feaure. Proecion feaures are no designed for coninuous repeiive operaion. 6) See also Chaper Resuls for E AR from simulaion of emperaure swing. 7) ESD resisiviy, HBM according o ANSI/ESDA/JEDEC JS-001 (1.5 kω, 100 pf). 8) ESD suscepibiliy, Charged Device Model CDM according JEDEC JESD22-C V S = 13.5 V E A 100 mj 10 Figure 4 Maximum energy dissipaion 1) 1 10 A 100 E_AR (Tj(0) = 105 C) E_AS (Tj(0) = 150 C) Noe: Clamping overrides all proecion funcionaliies. In order o avoid device desrucion resuling from inducive swich-off or over volage he device has o be operaed wihin he maximum raings. Noe: Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. I L 1) No subjec o producion es, specified by design. Resuls for E AR from simulaion of emperaure swing. Daashee 6 V2.0,

9 General Produc Characerisics Noe: Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. 4.2 Funcional Range Pos. Parameer Symbol Limi Values Uni Condiions Min. Max. Supply Volage Nominal Supply Volage Range for V S(NOM) 9 16 V Operaion Exended Supply Volage Range for Operaion 1) V S(EXT) 6 28 V 2) V dd = V dd(nom) Logic Supply Volage Range for V dd(nom) V Operaion Load curren range for sense I L(IS) 2 40 A I IS - I IS(LH) >30µA funcionaliy 1) I IS < I IS(lim) V IS < V IS(lim) V S = V S(NOM) V INx = V SENx =5V Juncion emperaure T j C 1) No subjec o producion es, specified by design 2) In exended supply volage range, he device is funcional bu elecrical parameers are no specified. Noe: Wihin he funcional or operaing range, he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he Elecrical Characerisics able. 4.3 Thermal Resisance Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Juncion o Soldering poin one channel acive all channels acive Juncion o Ambien one channel acive all channels acive R hjsp 1) R hja 1) 1) No subjec o producion es, specified by design 2) Specified R hja values is according o Jedec JESD51-2,-5,-7 a naural convecion on FR4 2s2p board; The produc (chip+package) was simulaed on a 76.4 x x 1.5 mm board wih 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu). Where applicable, a hermal via array under he package conaced he firs inner copper layer K/W K/W 2) juncion o pins (8, 9, 10, 16, 17, 18, 19,20,21,27,28, 29) T a = 105 C P loss =1W per channel cooling area I Figure 5 is showing he ypical hermal impedance of mouned according o Jedec JESD51-2,- 5,-7 a naural convecion on FR4 1s and 2s2p board. The produc (chip + package) was simulaed on a 76,4 x 114,3 x 1,5 mm board wih 2 inner copper layers (2x 70µm Cu, 2 x 35µm Cu). Where applicable, a hermal via Daashee 7 V2.0,

10 General Produc Characerisics array under he exposed pad conaced he firs inner copper layer. The PCB layer srucure is shown in Figure 6. The PCB op view is shown in Figure s + area I 1s + 600mm² 2s2p + area I 10 Z hja [K/W] 1 0,1 0,001 0,01 0, P [sec.] Figure 5 Typical ransien hermal impedance Zh(JA) = f(p) for differen cooling areas 1s PCB 2s2p PCB 70µm 70µm 1.5mm 1.5mm GND Vba 35µm 0.3mm PCB_cross.emf Figure 6 Cross secion and fron view of 1s and 2s2p PCB used for ZhJA simulaion Daashee 8 V2.0,

11 General Produc Characerisics PCB wih 600mm² cooling area PCB wih cooling area I deail on cooling area I Figure 7 Top view of PCB wih differen cooling areas used for ZhJA simulaion 4.4 Package Pos. Parameer Value Tes Condiions Jedec humidiy caegory acc. J-STD-020-D MSL Jedec classificaion emperaure acc. J-STD-020-D 260 C Daashee 9 V2.0,

12 Funcional Descripion 5 Funcional Descripion 5.1 Power Sages The is a high side swich wih wo independen oupus OUT0 and OUT1, made ou of a dual N- channel power MOSFET wih charge pump. For each channel, he provides sophisicaed proecion and diagnosic feaures. Table 1 Truh Table for Power Sages Operaion Mode Inpu (INx) Oupu Level Diagnosic Oupu (IS) Level (OUTx) SENx = H SENx = L Normal Operaion (ON) H ~V S I IS = I L / k ILIS Z Inverse Operaion (-I L ) >V S Z Shor Circui o V S V S < I L / k ILIS Open Load ~V S Z Proecive swich-off resuling from X Z Z Z Shor Circui o GND or Over Temperaure 1) Undervolage swich-off 2) Normal Operaion (OFF) L Z Z Z Inverse Operaion (-I L ) >V S Z Shor Circui o V S Z Z Open Load L = Low Level, H = High Level, X = don care, Z = high impedance, only leakage provided, poenial depends on exernal circui 1) Oupu sae and faul reporing remains lached unil rese signal (SEN0=SEN1=High). 2) Afer undervolage shudown, undervolage resar is delayed ( delay(uv) ) if V dd = V dd(nom), V IN = HIGH Oupu On-Sae Resisance The on-sae resisance R DS(ON) of each channel depends on he supply volage V S and he juncion emperaure T j. Figure 8 shows hese dependencies for he ypical on-sae resisance. The on-sae resisance in reverse polariy mode is described in Chaper Daashee 10 V2.0,

13 Funcional Descripion R DS(ON) V S = 13.5 V R DS(ON) T j = 25 C 7,5 m 7,5 m yp. yp ,5 2, C 160 Figure 8 Typical On-Sae Resisance T j V 28 V S Oupu Timing The power sage is designed for high side configuraion (Figure 10). The offers 4 pre-defined swiching behavior for he power sage. Defined slew raes as well as edge shaping suppor PWM ing of he load while achieving lowes EMC emission a minimum swiching losses. The differen swiching speeds can be seleced by using slew rae selecor pins SRS0 and SRS1. Please look a chaper Chaper 6.1 Elecrical Characerisics Table parameer (dv/ d) ON and -(dv/ d) OFF on page 24 on seing up SRS0 and SRS1. V IN V OUT 90% ON r OFF f 50% 30% dv/d ON dv/d OFF Figure 9 10% Swiching a Load (resisive) SwichOn _power.emf Oupu Inducive Clamp When swiching off inducive loads, he oupu volage V OUT drops below ground poenial due o he inducive properies of he load ( -di L /d = -v L /L ; -V OUT -V L ). To preven desrucion of he device, here is a volage clamp mechanism implemened ha keeps he volage drop across he device a a cerain level. A nominal baery volage he oupu is clamped o V OUT(CL). A over volages Daashee 11 V2.0,

14 Funcional Descripion he oupu is clamped o V DS(CL). See Figure 10 and Figure 11 for deails. The maximum allowed load inducance is limied. conrol chip V ba charge pump GND OUT power chip V DS(CL) i L V OUT(CL) LOAD OupuClamp.emf Figure 10 Oupu Clamp V OUT V S ON OFF V DS(CL) V OUT V DS(CL) =f(v S ) V S V DS(CL) V OUT(CL) I L V S V OUT(CL) InduciveLoad.emf Figure 11 Swiching an Inducance Maximum Load Inducance While de-energizing inducive loads, energy has o be dissipaed in he. This energy can be calculaed by he following equaion: E A = ( V S + V OUT( CL) ) V OUT( CL) R L R L I L ln V OUT(CL) + I L L R L In he even of de-energizing very low ohmic inducances (R L 0) he following, simplified equaion can be used: V DS(CL) 1 2 E A = --LI 2 L V DS(CL) V S The energy, which is convered ino hea, is limied by he hermal design of he componen. See Figure 4 for he maximum allowed energy dissipaion. Daashee 12 V2.0,

15 Funcional Descripion Inverse Operaion Capabiliy The can be operaed in inverse load curren condiion (V OUT > V S ). Inverse load curren is a negaive load curren, e.g. caused by a load operaing as a generaor. The device does no block he curren flow during inverse mode. In ON condiion, a volage drop across he acivaed channel of -V ON(INV) = -I L x R DS(ON) can be observed. As long as he inverse curren does no exceed -IL < -IL(inv), he logic will operae normally. In OFF condiion, a volage drop across he inacive channel of -V OFF(INV) = f(-i L ) can be observed. Also he accuracy of he sense funcion of he non-invered channel may no be wihin specified range under his condiion. conrol chip power chip +V S -V ON(inv) V ba logic GND -I L OUT + - Figure 12 Inverse curren capabiliy Noe: Acivaion of any proecion mechanism will no block he curren flow. Over emperaure deecion and curren sense is no funcional during inverse mode. 5.2 Inpu Circui Inverse_capabiliy.emf Figure 13 shows he inpu circui of he. The circuiry is equivalen for all inpu pins of he device (IN0, IN1, SEN0, SEN1, SRS0, SRS1). The inpu resisor o ground ensures ha he inpu signal is low in case of open inpu pin. The z-diode proecs he inpu circui agains ESD pulses. The funcion which is linked o each pin can be found in Chaper 3.2 Pin Definiions and Funcions. IN GND R IN Inpu.emf Figure 13 Inpu Circui Daashee 13 V2.0,

16 Funcional Descripion 5.3 Proecion Funcions The provides embedded proecive funcions. Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are neiher designed for coninuous nor repeiive operaion Infineon INTELLIGENT LATCH - faul acknowledge and lach rese The provides Infineon INTELLIGENT LATCH o avoid permanen reseing of a proecive, lached swich off in PWM applicaions, in case of overemperaure or shor circui. To rese a lached proecive swich off he faul has o be acknowledged by a HIGH signal a boh sense enable pins SEN0 and SEN1 (RESET = (SEN0&SEN1=HIGH)), or by an undervolage rese of he inernal logic supply. Please refer o Figure 14 and Figure 15 for deails. To avoid inerferrence of rese signal and proecive swichoff, eiher IN0 and IN1 mus be low during rese signal, or rese signal mus be shorer han 50µs ((SEN0&SEN1=HIGH) only for < 50µs). IN0 & SEN0 SEN1 logic supply rese & 1 INTELLIGENT LATCH I L>I L( SC) 1 S Τ j >T j R Q Q Channel 1 Channel 0 OUT1 OUT0 driver-logic.emf Figure 14 Driver logic Daashee 14 V2.0,

17 Funcional Descripion Figure 15 SEN0 + SEN1 INx over emp. / shor circui V OUTx I S I IS I IS(LL) V dd lach lach rese rese Infineon INTELLIGENT LATCH - faul acknowledge and lach rese I Lx /k ILISx faul _acknowledge.emf Shor Circui and Overemperaure Proecion The inernal logic permanenly moniors he load curren I L and he juncion emperaure T j. In he even he shor circui shudown hreshold (I L(SC) ) or overemperaure shudown hreshold (T j ) is exceeded, he device will swich off he affeced channel immediaely. Shor circui shudown and overemperaure shudown will be lached. Please refer o Figure 16 for deails. A RESET signal will override emperaure shudown hyseresis even if T j > T j - ΔT j. See also Chaper In case of a shor circui beween OUT and ground, an impedance beween V ba and V S pin of he device may cause he device s supply volage o drop below V S(UV)ON -ΔV S(UV) before shor circui shudown hreshold is reached. In ha case, device urns off in undervolage. If V S drops below 4.5V before device has swiched off, channels will be deacivaed by passive gae discharge, which may ake several milliseconds. In his ransien condiion of passive gae discharge during V S < 4.5V, overemperaure shudown is no funcional. The resars auomaically from undervolage when V S > V S(UV)ON and delay ime delay(uv) has passed and no faul signal was lached. shor circui overemperaure V IN SEN0 2 + SEN1 1 0 V IN SEN0 2 + SEN1 1 0 I L I L(SC) T j T j lach rese lach rese lach lach rese lach rese lach faul_deec.emf Figure 16 Shudown by shor circui curren and overemperaure deecion Daashee 15 V2.0,

18 Funcional Descripion Reverse Polariy Proecion - ReverSave TM The device can no block a curren flow in reverse baery condiion. In order o minimize power dissipaion, he device offers ReverSave TM funcionaliy. Under reverse polariy condiion, he oupu sage will be swiched on, provided a sufficien volage -V S is applied beween pin and pin GND. Please refer o Figure 17 for deails. conrol chip power chip -V S -V ON(rev) -V ba OUT Figure 17 Reverse baery proecion GND Use he following formula for esimaion of overall power dissipaion P diss(rev) in reverse polariy mode. Noe: No proecion mechanism is acive during reverse polariy. The conrol chip is no funcional. Poenials of logic pins can become negaive. Affeced pins have o be proeced by means of series resisors Undervolage shudown and resar Reverse.emf The is supplied by wo supply volages V S and V dd. Wih applied V S and V dd volages he channels can be acivaed via he according inpu pins. The device is in normal operaion mode. The V S supply line is used by he driver circuiry and he power sage, providing supply for analog and logic circuiry, a normal condiions (V S(NOM) ). If V S is below V S(NOM), he inernal logic supply is swiched over o V dd line. There is a power-on rese funcion implemened for he inernal logic supply. Afer sar-up of he logic power supply (via V S or V dd.), all laches are rese. If V dd is close o V dd(reset), he swich-over may acivae logic supply rese of he INTELLIGENT LATCH funcion. See Figure 1 and Figure 14. A capacior beween V dd and GND is recommended for filering purpose as shown in Figure 23. If V S drops below V S(UV)ON - ΔV S(UV), power oupus of will be deacivaed. If an inpu pin INx is HIGH and V dd = V dd(nom), he power oupus will resar auomaically when V S increases o V S(UV)ON and a delay ime of delay(uv) has passed. Please see Figure 18 for deails. In he ime beween undervolage shudown and undervolage resar, IS signal is deacivaed, wih leakage curren only. Sand-by mode is enered as soon as V S volage is available, bu no V dd supply volage is applied. If he V dd volage is applied oo, bu no channel is swiched on, he device is in idle mode. If V dd is applied before V S is available, a rese via SEN0=SEN1=HIGH may be necessary for enabling he power sages. -I L 2 P R I diss(rev) ON(rev) L LOAD Daashee 16 V2.0,

19 Funcional Descripion V IN, V dd HIGH V S V S(UV)ON ΔV S(UV) V OUT ON delay(uv) Figure 18 Z Undervolage shudown and resar undervolage.emf Loss of Ground Proecion In case of complee loss of he device ground connecions, bu load sill being conneced o ground, he securely changes o or remains in OFF sae Loss of Load Proecion, Loss of V S Proecion In case of loss of load wih charged primary inducances he maximum supply volage has o be limied. I is recommended o use a Z-diode, a varisor (V Za <42V) or V S clamping power swiches wih conneced loads in parallel. In case of loss of V S connecion wih charged inducive loads, a curren pah wih load curren capabiliy has o be provided, o demagneize he charged inducances. I is recommended o use a diode, a Z-diode or a varisor (V Zb <16V, V ZL +V D <16V, ). For higher clamp volages currens hrough all pins have o be limied according o he maximum raings. Please refer o Figure 19 for deails. Daashee 17 V2.0,

20 Funcional Descripion conrol chip power chip conrol chip power chip V Zb V Za logic GND OUT LOAD logic GND OUT LOAD V D V ZL _load _disconnec.emf _disconnec.emf Figure 19 Loss of V S In case of complee loss of V S he remains in OFF sae. 5.4 Diagnosic Funcions For diagnosis purposes, he provides an analog load curren sense signal a he pin IS Sense Enable Providing a low signal a he SENx pin will disable he reporing of channel x. The pin IS will be se o ri-sae mode when boh SEN pins are low or high. A HIGH signal a SEN0 and SEN1 a he same ime reses a preceding lached oupu condiion. Please see Figure 15, Figure 20 and Table 1 Truh Table for Power Sages for deails. In order o achieve minimum sandby curren, SEN0 and SEN1 have o be low level. Vdd I L/k ILIS 0 1 SEN0 Ch 0 SEN1 IS 0 1 OUT1 OUT0 Figure 20 Curren sense curren-sense.emf Daashee 18 V2.0,

21 Funcional Descripion Table 2 Truh Table for Sense Enable SEN0 SEN1 IS Commen H H I IS(LL) faul lach rese L H I IS =I L1 /k ILIS channel 1 H L I IS =I L0 /k ILIS channel 0 L L I IS(LL) L = Low Level, H = High Level Diagnosis during ON During normal operaion, an enabled IS pin provides a sense curren, which is proporional o he load curren as long as V IS < V S - 5 V and as long as I IS *R IS <V IS(lim). The raio of he oupu curren is defined as k ILIS =I L /I IS. During swich-on sense curren is provided afer a sense seling ime sis(on). During inverse operaion and swich-off no curren is provided. The oupu sense curren is limied o I IS,lim. Please refer o Figure 21 for deails. V INx normal operaion V SENx V ONx I Lx I L(1) I L(2) I L(1) Figure 21 I ISx 0.9*I IS(1) I IS(LL) sis(on) I IS(1) I IS(2) sis(lc) I IS(lim) Timing of Diagnosis Signal in ON-sae 0.1*I IS(1) sis(off ) sis(sen) The accuracy of he provided curren sense raio (k ILIS = I L / I IS ) depends on he load curren. Please refer o Figure 22 for deails. A ypical resisor R IS of 1 kω is recommended (see also Chaper 5.3.5). I IS(1) dis(sen) 0.1*I IS(1) SwichON _sense.emf Daashee 19 V2.0,

22 Funcional Descripion k ILIS max. yp. min A 40 I L Figure 22 Curren sense raio k ILIS 1) 1) The curves show he behavior based on characerizaion daa. The marked poins are described in his Daashee in Chaper 6.1 (Posiion ). Daashee 20 V2.0,

23 Elecrical characerisics 6 Elecrical characerisics 6.1 Elecrical Characerisics Table Noe: Characerisics show he deviaion of parameers a he given supply volage and juncion emperaure. Typical values show he ypical parameers expeced from manufacuring. V S = 9 V o 16 V, V dd = 4.5 V o 5.5 V, T j = -40 C o +150 C (unless oherwise specified) ypical values: V S = 13.5 V, T j = 25 C, V dd = 5 V Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max. Oupu characerisics On-sae resisance per channel T j =25 C 1) T j =150 C V S =6V, T j =25 C 1) V S =6V, T j =150 C Nominal load curren per channel 1)2) Oupu leakage curren per channel T j = -40 C, T j = 25 C 1) T j 85 C 1) T j = 150 C Oupu clamp during swich-off I L = 40 ma I L = 10 A 1) Oupu clamp during over volage I L =40mA I L = 20 A 1) Inverse operaion oupu volage drop T j =25 C 1) T j =150 C R DS(ON) mω V IN =5V, I L =+/-10A I L(nom) 11 A T A = 85 C T j 150 C I L(OFF) -V OUT(CL) V DS(CL) V OFF(inv) µa V IN0 = V IN1 = 0V V OUT =0V V V OUT V S V DS(CL) 3) V V DS V S -V OUT(CL) 3) mv V IN =0V I L = -10 A Inverse curren capabiliy 1) -I L(inv) 25 A Timings Turn-on ime o 90%V S SRS1 = 1, SRS0 = 1 SRS1 = 1, SRS0 = 0 SRS1 = 0, SRS0 = 1 SRS1 = 0, SRS0 = Turn-off ime o 10%V S SRS1 = 1, SRS0 = 1 SRS1 = 1, SRS0 = 0 SRS1 = 0, SRS0 = 1 SRS1 = 0, SRS0 = 0 ON OFF µs V S = 13.5 V R L = 2.7 Ω µs V S = 13.5 V R L = 2.7 Ω Daashee 21 V2.0,

24 Elecrical characerisics V S = 9 V o 16 V, V dd = 4.5 V o 5.5 V, T j = -40 C o +150 C (unless oherwise specified) ypical values: V S = 13.5 V, T j = 25 C, V dd = 5 V Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Slew rae On 30 50% V OUT SRS1 = 1, SRS0 = 1 SRS1 = 1, SRS0 = 0 SRS1 = 0, SRS0 = 1 SRS1 = 0, SRS0 = Slew rae Off 50 30% V OUT SRS1 = 1, SRS0 = 1 SRS1 = 1, SRS0 = 0 SRS1 = 0, SRS0 = 1 SRS1 = 0, SRS0 = 0 Power supply Sand-by curren T j = -40 C, T j = 25 C 1) T j 85 C 1) T j = 150 C (dv/ d) ON -(dv/ d) OFF I S(OFF) V/µs V/µs µa V S = 13.5 V R L = 2.7 Ω V S = 13.5 V R L = 2.7 Ω 4) V IN0 = V IN1 =0V V SEN0 = V SEN1 =0V V dd =0V no faul condiion Idle curren for whole device wih loads, boh channel OFF I S(idle) 800 µa 4) V IN0 = V IN1 =0V V SEN0 = V SEN1 =0V V dd =5V no faul condiion Logic supply rese hreshold 1) V dd(reset) 4.5 V V S = 0V Logic supply curren V S = 9 V o 16 V V S = 6V Operaing curren for whole device acive I dd µa V IN0 = V IN1 =5V V SEN0 = V SEN1 =5V V dd =5V I GND ma V IN0 = V IN1 =5V V SEN0 = V SEN1 =5V V dd =5V, I L =0A Inpu characerisics L-inpu level V IN(L) V H-inpu level V IN(H) V inpu hyseresis V IN(hys) 175 mv 1) inpu pull down resisor R IN kω Over-Load Proecion Shor circui shudown hreshold T j = -40 C T j = 150 C I L(SC) Thermal shudown emperaure T j ) A C Daashee 22 V2.0,

25 Elecrical characerisics V S = 9 V o 16 V, V dd = 4.5 V o 5.5 V, T j = -40 C o +150 C (unless oherwise specified) ypical values: V S = 13.5 V, T j = 25 C, V dd = 5 V Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max. Reverse Baery On-Sae resisance in case of reverse polariy V S =-8V 1) V S =-12V Diagnosis signal Curren sense raio, saic oncondiion I Lx =20A I Lx =10A I Lx =5A I Lx =2A V INx = 0 (e.g. during de energizing of inducive loads) R ON(rev) k ILIS disabled mω I L = -10A T j = 150 C V IS < V IS(lim), V IS < V S -5V V INx =High V SENx = High V SENy =Low I Ly 0A V 1.08 x V Curren sense volage limiaion 1) V IS(lim) 0.92 x V dd dd V dd Sense sauraion curren 1) I IS(lim) ma V SENx =5V V IS < V S -5V Curren sense leakage curren I IS(LL) μa V INx =V SENx =0V Curren sense offse curren I IS(LH) μa V INx =V SENx =5V I Lx 0A Curren sense seling ime o 90% I IS_sa. afer swich-on 1) Curren sense seling ime o 10% sis(on) sis(off) μs μs V S = 13.5V V SENx =5V R L =2.7Ω I IS_sa. afer swich-off 1) Curren sense seling ime o 90% I IS_sa. afer changing load 1) sis(lc) μs V S = 13.5V V SENx =5V I L =10 20A Curren sense seling ime o 90% I IS_sa. afer sense enable 1) sis(sen) 7 35 μs V S = 13.5V V SENx =5V R L =2.7Ω 7 35 μs Curren sense deacivaion ime o 10% I IS_sa. afer sense disable 1) dis(sen) Undervolage shudown and resar Undervolage resar hreshold V S(UV)ON V V INx =High Undervolage hyseresis 1) ΔV S(UV) 10 mv V INx =High Undervolage resar delay ime 1) delay(uv) ms V INx =High 1) No subjec o producion es, specified by design 2) according JESD51_7, FR4 2s2p board, 76.2 x x 1.6 mm, 2x70µm Cu, 2x35µm Cu. 3) See Figure 11. 4) In case of proecive swich-off STANDBY is only reached if he faul was acknowledged by a RESET signal (SEN0&SEN1=High). See also Chaper for deails. Daashee 23 V2.0,

26 Applicaion schemaic 7 Applicaion schemaic Figure 23 shows an example for an applicaion schemaic. V ba R+L supply +5V µc 47nF 500R 10K 10K 10K 10K 10K 10K 10K 1k Vdd IN0 IN1 SEN0 OUT0 SEN1 SRS0 OUT1 SRS1 IS GND 100nF 470nF 10nF 10nF R+L cable R+L cable LOAD0 GND LOAD1 applicaion_diagram.emf Figure 23 applicaion example Noe: This is a simplified example of an applicaion circui. The funcion mus be verified in he real applicaion. 7.1 Hins for PCB layou Handling of NC pins: I is recommended o connec all NC pins on a defined poenial. E.g. pin 6 and pin 36 could be conneced o GND poenial. EMC filer cap beween and GND, Vdd and GND: I is recommended o place he filer cap as close as possible o he device o minimize he inducance of he loop. GNDR pin: in case of open GNDR pin, ransien volage disurbances may lead o reducion of delay(uv) o ypically 1.9ms. The resisors connecing µc and inpu pins INx, SENx, SRSx, are recommended for proecion of pins agains fas elecrical ransiens. Ground shif: I is recommended o avoid a ground shif beween µc ground and device pin GND of more han 0.3V during normal operaion. 7.2 Furher Applicaion Informaion Please conac us o ge he Pin FMEA Please conac us o ge a es repor on shor circui robusness according o AEC Q For furher informaion you may conac hp:// Daashee 24 V2.0,

27 Package Oulines 8 Package Oulines MAX M C A-B D 36x ±0.08 2) C ) x 45 ± ±0.2 D 8 MAX. A Boom View Index Marking 1 18 B 1) Ejecor Mark Index Marking 1) Does no include plasic or meal prorusion of 0.15 max. per side 2) Does no include dambar prorusion of 0.05 max. per side GPS HLGF1145 Figure 24 PG-DSO (Plasic Dual Small Ouline Package) Green Produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions he device is available as a green produc. Green producs are RoHS-Complian (i.e Pb-free finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). You can find all of our packages, sors of packing and ohers in our Infineon Inerne Page Producs : hp:// Dimensions in mm Daashee 25 V2.0,

28 Revision Hisory 9 Revision Hisory Revision Hisory: V2.0, Version Dae Changes DS V Inroducion of undervolage shudown and resar delay funcion Chaper 4.1 Absolue Maximum Raings: parameer V ba(sc) se o maximum 24V for T j = -40 C C, condiion descripion improved; parameer I GND and I dd minimum raing added; parameer V ESD1 and V ESD2 ESD suscepibiliy descripion updaed; parameer V ESD2 esed according JEDEC JESD22-C101 Chaper 5.1 Table 1 Truh Table for Power Sages: undervolage condiion added Chaper Shor Circui and Overemperaure Proecion reworked; noe on supply volage breakdown during shorcircui removed. Chaper Undervolage shudown and resar reworked; descipion of undervolage shudown on supply line added; Chaper 3.2: seing of SRS0 and SRS1 correced Chaper 6.1: parameer ON, OFF, (dv/d) ON, (dv/d) OFF : seing of SRS0 and SRS1 correced parameer I dd : low volage condiion =6V added parameer I S(idle) reduced o ypically 800uA parameer V S(UV)ON, ΔV S(UV), delay(uv) added parameer sis(lc) descripion of condiion improved Chaper 7 Applicaion schemaic: Figure 23 adding R+L_supply and R+L_cable, fiing o improved descripion of V ba(sc). Chaper 7.1 Hins for PCB layou: Hin on open GNDR pin added. Hin on filer capacior Vdd o GND added. DS V Chaper 6: Specificaion limis for parameer k ILIS ighened. Figure 22 updaed. DS V Chaper 1: Typing error correced on Page 1, parameer I L(SC). DS V Iniial version of daashee Daashee 26 V2.0,

29 Ediion Published by Infineon Technologies AG Munich, Germany 2016 Infineon Technologies AG All Righs Reserved. Legal Disclaimer The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics. Wih respec o any examples or hins given herein, any ypical values saed herein and/or any informaion regarding he applicaion of he device, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion, warranies of non-infringemen of inellecual propery righs of any hird pary. Informaion For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office ( Warnings Due o echnical requiremens, componens may conain dangerous subsances. For informaion on he ypes in quesion, please conac he neares Infineon Technologies Office. Infineon Technologies componens may be used in life-suppor devices or sysems only wih he express wrien approval of Infineon Technologies, if a failure of such componens can reasonably be expeced o cause he failure of ha life-suppor device or sysem or o affec he safey or effeciveness of ha device or sysem. Life suppor devices or sysems are inended o be implaned in he human body or o suppor and/or mainain and susain and/or proec human life. If hey fail, i is reasonable o assume ha he healh of he user or oher persons may be endangered.