500 V, 1 A to 3 A High Voltage 3-phase Motor Driver ICs SLA6870MH, SMA/SLA6860MH Series. Packages

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1 5 V, 1 A o 3 A High Volage 3-phase Moor Driver ICs SLA687MH, SMA/SLA686MH Series Daa Shee Descripion The SLA687MH and he SMA/SLA686MH series are high volage 3-phase moor driver ICs in which ransisors, pre-driver ICs (MICs), and boosrap circuis (diodes and resisors) are highly inegraed. Selecable ZIP24 packages (fully-molded or heasink ype) wih various leadforms enable opimum mounabiliy o a wide range of applicaions. These producs can opimally conrol he inverer sysems of small- o medium-capaciy moors. Feaures Buil-in Boosrap Diodes wih Curren Limiing Resisors (21 Ω) CMOS-compaible Inpu (5 V) Shudown Funcion Bare Lead Frame: Pb-free (RoHS Complian) Proecions Include: Undervolage Lockou for Power Supply VBx Pin (UVLO_VB): Auo-resar VCC1 Pin (UVLO_VCC1): Auo-resar VCC2 Pin (UVLO_VCC2): Auo-resar Overcurren Limi (OCL) Overcurren Proecion (OCP): Auo-resar wih Adjusable OCP Hold Time Thermal Shudown (TSD): Auo-resar Typical Applicaion VCC Conroller HIN3 HIN2 HIN1 LIN3 LIN2 LIN1 Faul RCL CCL 5 V 5 V RSD2 RRC 5 V VCC1 COM1 HIN3 HIN2 HIN1 SD1 OCL 17 LIN3 18 LIN2 19 LIN1 2 COM2 21 SD2 VCC RC 15 High-side MIC Low-side MIC VB1 1 2 VB2 3 VB3 1VBB 24 U W V 13 W2 14 LS2 16 LS1 M CBOOT1 CBOOT2 CBOOT3 VDC Packages ZIP24 Fully-molded ype (SMA686xMH) Selecion Guide Heasink ype (SLA686xMH/7xMH) Leadform 2451 Leadform 2175 Leadform 2452 Leadform 2171 No o scale Package V DSS I O Par Number Fullymolded Type Heasink Type Applicaions 5 V 5 V For moor drives such as: 1. A SMA686MH 1.5 A SMA6862MH 2.5 A SMA6863MH SMA6865MH 2.5 A SLA6868MH 3. A SLA687MH Fan Moor and Pump Moor for Washer and Dryer Fan Moor for Air Condiioner Fan Moor for Air Purifier and Elecric Fan CSD2 CRC CSB CDC RS GND SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 1 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

2 SLA687MH, SMA/SLA686MH Series Conens Descripion Conens Absolue Maximum Raings Recommended Operaing Condiions Elecrical Characerisics Characerisics of Conrol Pars Boosrap Diode Characerisics Thermal Resisance Characerisics Power MOSFET Characerisics SMA686MH SMA6862MH SMA6863MH SMA6865MH SLA6868MH SLA687MH Mechanical Characerisics Truh Table Block Diagram Pin Configuraion Definiions Typical Applicaion Physical Dimensions ZIP24 Fully-molded Type (Leadform 2451) ZIP24 Fully-molded Type (Leadform 2452) ZIP24 Heasink Type (Leadform 2175) ZIP24 Heasink Type (Leadform 2171) Marking Diagram ZIP24 Fully-molded Type ZIP24 Heasink Type Funcional Descripions Turning On and Off he IC Pin Descripions U, V, W1, and W VBB LS1 and LS VB1, VB2, and VB VCC1 and VCC COM1 and COM HIN1, HIN2, and HIN3; LIN1, LIN2, and LIN OCL RC SD1 and SD Proecion Funcions Faul Signal Oupu Shudown Signal Inpu Undervolage Lockou for Power Supply (UVLO) Overcurren Limi (OCL) Overcurren Proecion (OCP) Thermal Shudown (TSD) Design Noes PCB Paern Layou SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 2 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

3 SLA687MH, SMA/SLA686MH Series 12.2 Consideraions in Heasink Mouning Consideraions in IC Characerisics Measuremen Calculaing Power Losses and Esimaing Juncion Temperaure Power MOSFET Seady-sae Loss, P RON Power MOSFET Swiching Loss, P SW Body Diode Seady-sae Loss, P SD Esimaing Juncion Temperaure of Power MOSFET Performance Curves Transien Thermal Resisance Curves Performance Curves of Conrol Pars Performance Curves of Oupu Pars Oupu Transisor Performance Curves Swiching Losses Allowable Effecive Curren Curves SMA686MH SMA6862MH SMA6863MH SMA6865MH SLA6868MH SLA687MH Paern Layou Example Typical Moor Driver Applicaion Imporan Noes SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 3 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

4 SLA687MH, SMA/SLA686MH Series 1. Absolue Maximum Raings Curren polariies are defined as follows: curren going ino he IC (sinking) is posiive curren (+); curren coming ou of he IC (sourcing) is negaive curren ( ). Unless specifically noed, T A = 25 C, COM1 = COM2 = COM. Parameer Symbol Condiions Raing Uni Remarks Main Supply Volage (DC) V DC VBB LSx 4 V Main Supply Volage (Surge) V DC(SURGE) VBB LSx 45 V Power MOSFET Breakdown Volage Logic Supply Volage V DSS V CC V BS Oupu Curren (DC) (1) I O T C = 25 C Oupu Curren (Pulse) Inpu Volage SD Pin Volage I OP V IN V SD VBB LSx, V CC = 15 V, I D = 1 μa, V IN = V VCC1 COM, VCC2 COM VB1 U, VB2 V, VB3 W1 T C = 25 C, P W 1 μs, duy cycle = 1% HIN1 COM, HIN2 COM, HIN3 COM; LIN1 COM, LIN2 COM, LIN3 COM SD1 COM, SD2 COM 5 V 2 2 V 1. SMA686MH 1.5 SMA6862MH 2.5 A SMA6863MH/65MH SLA6868MH 3. SLA687MH 1.5 SMA686MH 2.25 SMA6862MH 3.75 A SMA6863MH/65MH SLA6868MH 4.5 SLA687MH.5 o 7 V.5 o 7 V 28 SMA686MH/62MH/ 63MH/65MH Allowable Power Dissipaion P D T C = 25 C W 32.8 SLA6868MH/7MH Operaing Case Temperaure (2) T C(OP) 3 o 1 C Juncion Temperaure (3) T J 15 C Sorage Temperaure T STG 4 o 15 C Isolaion Volage (4) V ISO(RMS) Beween surface of he case and each pin; AC, 6 Hz, 1 min 12 V SLA6868MH/7MH (1) Should be deraed depending on an acual case emperaure. See Secion (2) Refers o a case emperaure measured during IC operaion. (3) Refers o he juncion emperaure of each chip buil in he IC, including he conroller ICs (MICs) and power MOSFETs. (4) Refers o volage condiions o be applied beween he case and all pins. All pins have o be shored. SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 4 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

5 SLA687MH, SMA/SLA686MH Series 2. Recommended Operaing Condiions Unless specifically noed, COM1 = COM2 = COM. Parameer Symbol Condiions Min. Typ. Max. Uni Remarks Main Supply Volage Snubber Capacior for Main Power Supply V DC VBB LS1, VBB LS2 VCC1 COM, V CC VCC2 COM Logic Supply Volage VB1 U, V BS VB2 V, VB3 W1 VCC1 COM, Proecive Zener Volage V Z VCC2 COM Inpu Volage (HINx, LINx, SDx) 3 4 V C SB.1.1 μf V V 18 2 V V IN 5.5 V SDx Pin Pull-up Volage V SD V OCL Pin Pull-up Volage V CL V SDx Pin Pull-up Resisor R SD kω OCL Pin Pull-up Resisor R CL 1 1 kω SDx Pin Capacior C SDx 1 1 nf OCL Pin Capacior C CL 1 1 nf RC Pin Capacior C RC nf RC Pin Pull-up Resisor R RC kω Minimum Inpu Pulse Widh IN(MIN)ON T J = 25 o 15 C.5 μs IN(MIN)OFF T J = 25 o 15 C.5 μs Dead Time of Inpu Signal DEAD 1.5 μs Swiching Frequency f c 2 khz Boosrap Capacior C BOOT 1 22 μf Shun Resisor R S I P 1.5A 73 SMA686MH I P 2.25 A 49 SMA6862MH mω SMA6863MH I P 3.75A 29 SMA6865MH SLA6868MH I P 4.5 A 24 SLA687MH PWM Carrier Frequency f C 2 khz Operaing Case Temperaure T C(OP) 1 C SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 5 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

6 SLA687MH, SMA/SLA686MH Series 3. Elecrical Characerisics Curren polariies are defined as follows: curren going ino he IC (sinking) is posiive curren (+); curren coming ou of he IC (sourcing) is negaive curren ( ). Unless specifically noed, T A = 25 C, V CC = 15 V, COM1 = COM2 = COM. 3.1 Characerisics of Conrol Pars Parameer Symbol Condiions Min. Typ. Max. Uni Remarks Power Supply Operaion Logic Operaion Sar Volage Logic Operaion Sop Volage Logic Supply Curren Inpu Signal High Level Inpu Threshold Volage (HINx, LINx, SDx) Low Level Inpu Threshold Volage (HINx, LINx, SDx) Inpu Threshold Volage Hyseresis V CC(ON) V BS(ON) V CC(OFF) V BS(OFF) VCC1 COM, VCC2 COM VB1 U, VB2 V, VB3 W1 VCC1 COM, VCC2 COM VB1 U, VB2 V, VB3 W V V V V I CC I REG = A ma I BS VBx = 15 V, HINx = 5 V μa V IH V V IL V V HYS.8 Inpu Volage I IH V IN = 5 V 23 5 μa Proecion SDx Pin, OCL Pin Low Level Oupu Volage Curren Limi Reference Volage V SD(ON) V SD = V CL = 5 V, R UP = 3.3 kω.6 V V LIM V OCP Threshold Volage V TRIP V OCP Hold Time P V RC = 5 V, R RC = 33 kω, C RC =.47 µf V RC = 5 V, R RC = 36 kω, C RC =.47 µf 1. ms 1.1 ms OCP Blanking Time BK 2. μs TSD Operaing Temperaure T DH C TSD Releasing Temperaure T DL C TSD Operaing Temperaure Hyseresis T D_HYS 3 C Oupu ransisors ON Oupu ransisors OFF SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 6 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

7 SLA687MH, SMA/SLA686MH Series 3.2 Boosrap Diode Characerisics Parameer Symbol Condiions Min. Typ. Max. Uni Remarks Boosrap Diode Leakage Curren Boosrap Diode Forward Volage Boosrap Diode Series Resisor I LBD V R = 5 V, V IN = V 1 μa V FB I FB =.5 A, V IN = V V R BOOT Ω 3.3 Thermal Resisance Characerisics Parameer Symbol Condiions Min. Typ. Max. Uni Remarks Juncion-o-Case Thermal Resisance (1) R (J-C) (2) All power MOSFETs operaing Juncion-o-Ambien Thermal Resisance R (J-A) All power MOSFETs operaing C/W C/W SMA686MH/ 62MH/63MH/ 65MH SLA6868MH/ 7MH SMA686MH/ 62MH/63MH/ 65MH (1) Refers o a case emperaure a he measuremen poin described in Figure 3-1, below. (2) Refers o seady-sae hermal resisance beween he juncion of he buil-in ransisors and he case. For ransien hermal characerisics, see Secion Fully-molded Type Measuremen poin 5 mm Heasink Type Measuremen poin 5 mm Figure 3-1. Case Temperaure Measuremen Poins SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 7 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

8 SLA687MH, SMA/SLA686MH Series 3.4 Power MOSFET Characerisics Figure 3-2 provides he definiions of swiching characerisics described in his and he following secions. HINx/ LINx off I D / I C d(on) rr on d(off) f r 9% V DS / V CE 1% Figure 3-2. Swiching Characerisics Definiions SMA686MH Parameer Symbol Condiions Min. Typ. Max. Uni Drain-o-Source Leakage Curren I DSS V DS = 5 V, V IN = V 1 µa Drain-o-Source On-resisance R DS(ON) I D =.5 A, V IN = 5 V Ω Source-o-Drain Diode Forward Volage V SD I SD =.5 A, V IN = V V High-side Swiching Source-o-Drain Diode Reverse Recovery Time rr V DC = 3 V, 1 ns Turn-on Delay Time d(on) I D = 1 A, 72 ns Rise Time V IN = V o 5 V, r 4 ns T J = 25 C, Turn-off Delay Time d(off) inducive load 64 ns Fall Time f 4 ns Low-side Swiching Source-o-Drain Diode Reverse Recovery Time rr V DC = 3 V, 1 ns Turn-on Delay Time d(on) I D = 1 A, 64 ns Rise Time V IN = V o 5 V, r 4 ns T J = 25 C, Turn-off Delay Time d(off) inducive load 62 ns Fall Time f 4 ns SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 8 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

9 SLA687MH, SMA/SLA686MH Series SMA6862MH Parameer Symbol Condiions Min. Typ. Max. 単位 Drain-o-Source Leakage Curren I DSS V DS = 5 V, V IN = V 1 µa Drain-o-Source On-resisance R DS(ON) I D =.75 A, V IN = 5 V Ω Source-o-Drain Diode Forward Volage High-side Swiching V SD I SD =.75 A, V IN = V V Source-o-Drain Diode Reverse Recovery Time rr 11 ns V DC = 3 V, Turn-on Delay Time d(on) I D = 1.5 A, 72 ns Rise Time r V IN = V o 5 V, T J = 25 C, 6 ns Turn-off Delay Time d(off) inducive load 69 ns Fall Time f 3 ns Low-side Swiching Source-o-Drain Diode Reverse Recovery Time rr 12 ns V DC = 3 V, Turn-on Delay Time d(on) I D = 1.5 A, 67 ns Rise Time r V IN = V o 5 V, T J = 25 C, 7 ns Turn-off Delay Time d(off) inducive load 59 ns Fall Time f 3 ns SMA6863MH Parameer Symbol Condiions Min. Typ. Max. Uni Drain-o-Source Leakage Curren I DSS V DS = 5 V, V IN = V 1 µa Drain-o-Source On-resisance R DS(ON) I D = 1.25 A, V IN = 5 V Ω Source-o-Drain Diode Forward Volage High-side Swiching V SD I SD = 1.25 A, V IN = V V Source-o-Drain Diode Reverse Recovery Time rr 12 ns V DC = 3 V, Turn-on Delay Time d(on) I D = 2.5 A, 82 ns Rise Time r V IN = V o 5 V, 1 ns T J = 25 C, Turn-off Delay Time d(off) inducive load 74 ns Fall Time f 3 ns Low-side Swiching Source-o-Drain Diode Reverse Recovery Time rr 13 ns V DC = 3 V, Turn-on Delay Time d(on) I D = 2.5 A, 79 ns Rise Time r V IN = V o 5 V, T J = 25 C, 11 ns Turn-off Delay Time d(off) inducive load 7 ns Fall Time f 3 ns SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 9 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

10 SLA687MH, SMA/SLA686MH Series SMA6865MH Parameer Symbol Condiions Min. Typ. Max. Uni Drain-o-Source Leakage Curren I DSS V DS = 5 V, V IN = V 1 µa Drain-o-Source On-resisance R DS(ON) I D = 1.25 A, V IN = 5 V Ω Source-o-Drain Diode Forward Volage High-side Swiching V SD I SD = 1.25 A, V IN = V V Source-o-Drain Diode Reverse Recovery Time rr 1 ns V DC = 3 V, Turn-on Delay Time d(on) I D = 2.5 A, 75 ns Rise Time V IN r = V o 5 V, 6 ns T J = 25 C, Turn-off Delay Time d(off) inducive load 68 ns Fall Time f 2 ns Low-side Swiching Source-o-Drain Diode Reverse Recovery Time rr 1 ns V DC = 3 V, Turn-on Delay Time d(on) I D = 2.5 A, 64 ns Rise Time r V IN = V o 5 V, T J = 25 C, 65 ns Turn-off Delay Time d(off) inducive load 56 ns Fall Time f 2 ns SLA6868MH Parameer Symbol Condiions Min. Typ. Max. Uni Drain-o-Source Leakage Curren I DSS V DS = 5 V, V IN = V 1 µa Drain-o-Source On-resisance R DS(ON) I D = 1.25 A, V IN = 5 V Ω Source-o-Drain Diode Forward Volage High-side Swiching V SD I SD = 1.25 A, V IN = V V Source-o-Drain Diode Reverse Recovery Time rr 12 ns V DC = 3 V, Turn-on Delay Time d(on) I D = 2.5 A, 82 ns Rise Time V IN r = V o 5 V, 1 ns T J = 25 C, Turn-off Delay Time d(off) inducive load 74 ns Fall Time f 3 ns Low-side Swiching Source-o-Drain Diode Reverse Recovery Time rr 13 ns V DC = 3 V, Turn-on Delay Time d(on) I D = 2.5 A, 79 ns Rise Time r V IN = V o 5 V, T J = 25 C, 11 ns Turn-off Delay Time d(off) inducive load 7 ns Fall Time f 3 ns SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 1 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

11 SLA687MH, SMA/SLA686MH Series SLA687MH Parameer Symbol Condiions Min. Typ. Max. Uni Drain-o-Source Leakage Curren I DSS V DS = 5 V, V IN = V 1 µa Drain-o-Source On-resisance R DS(ON) I D = 1.5 A, V IN = 5 V Ω Source-o-Drain Diode Forward Volage High-side Swiching V SD I SD = 1.5 A, V IN = V V Source-o-Drain Diode Reverse Recovery Time rr 1 ns V DC = 3 V, Turn-on Delay Time d(on) I D = 3 A, 755 ns Rise Time V IN r = V o 5 V, 65 ns T J = 25 C, Turn-off Delay Time d(off) inducive load 68 ns Fall Time f 15 ns Low-side Swiching Source-o-Drain Diode Reverse Recovery Time rr 15 ns V DC = 3 V, Turn-on Delay Time d(on) I D = 3 A, 645 ns Rise Time r V IN = V o 5 V, T J = 25 C, 7 ns Turn-off Delay Time d(off) inducive load 56 ns Fall Time f 2 ns 4. Mechanical Characerisics Parameer Min. Typ. Max. Uni Remarks SLA6868MH/ Heasink Mouning Screw Torque N cm 7MH SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 11 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

12 SLA687MH, SMA/SLA686MH Series 5. Truh Table Table 5-1 is a ruh able ha provides he logic level definiions of operaion modes. In he case where HINx and LINx signals in each phase are high a he same ime, boh he high- and low-side ransisors become on (simulaneous on-sae). Therefore, HINx and LINx signals, he inpu signals for he HINx and LINx pins, require dead ime seing so ha such a simulaneous on-sae even can be avoided. Afer he IC recovers from a UVLO_VCC2 condiion, he low-side ransisors resume swiching in accordance wih he inpu logic levels of he LINx signals (level-riggered), whereas he high-side ransisors resume swiching a he nex rising edge of an HINx signal (edge-riggered). Afer he IC recovers from a UVLO_VB or UVLO_VCC1 condiion, he high-side ransisors resume swiching a he nex rising edge of an HINx signal (edge-riggered). Normal Operaion Shudown Signal Inpu (SD2 = L ) Table 5-1. Truh Table for Operaion Modes Mode HINx LINx High-side Transisor Low-side Transisor VBx Pin Undervolage Lockou (UVLO_VB) VCC1 Pin Undervolage Lockou (UVLO_VCC1) VCC2 Pin Undervolage Lockou (UVLO_VCC2) Overcurren Proecion (OCP) Overcurren Limi (OCL) (OCL = SD1) Thermal Shudown (TSD) L L OFF OFF H L ON OFF L H OFF ON H H ON ON L L OFF OFF H L ON OFF L H OFF OFF H H ON OFF L L OFF OFF H L OFF OFF L H OFF ON H H OFF ON L L OFF OFF H L ON OFF L H OFF OFF H H ON OFF L L OFF OFF H L ON OFF L H OFF OFF H H ON OFF L L OFF OFF H L OFF OFF L H OFF ON H H OFF ON L L OFF OFF H L ON OFF L H OFF OFF H H ON OFF SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 12 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

13 SLA687MH, SMA/SLA686MH Series 6. Block Diagram VCC1 4 Boosrap Diode R B VB1 VB2 VB UVLO UVLO UVLO UVLO 1 VBB HIN1 HIN2 HIN3 COM1 SD Inpu Logic High-side Level Shif Driver W1 W2 V VCC2 23 UVLO 24 U LIN1 LIN2 LIN Inpu Logic (OCP rese) Low-side Driver COM2 SD Thermal Shudown OCP OCP, OCL 14 LS2 16 LS1 OCL 17 RC 15 SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 13 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

14 SLA687MH, SMA/SLA686MH Series 7. Pin Configuraion Definiions Fully-molded Type (SMA686xMH) Heasink Type (SLA686xMH/7xMH) Leadform 2451 Leadform 2452 Leadform 2175 Leadform Pin Number Pin Name Descripion 1 VB1 U-phase high-side floaing supply volage inpu 2 VB2 V-phase high-side floaing supply volage inpu 3 VB3 W-phase high-side floaing supply volage inpu 4 VCC1 High-side logic supply volage inpu 5 SD1 High-side shudown signal inpu; faul signal oupu a UVLO_VCC1 acivaion 6 COM1 High-side logic ground 7 HIN3 Logic inpu for W-phase high-side gae driver 8 HIN2 Logic inpu for V-phase high-side gae driver 9 HIN1 Logic inpu for U-phase high-side gae driver 1 VBB Posiive DC bus supply volage 11 W1 W-phase oupu (conneced o W2 exernally) 12 V V-phase oupu 13 W2 W-phase oupu (conneced o W1 exernally) 14 LS2 W-phase low-side power MOSFET source (conneced o LS1 exernally) 15 RC OCP hold ime seing 16 LS1 U- and W-phase low-side power MOSFET source (conneced o LS2 exernally) 17 OCL Overcurren limi signal inpu 18 LIN3 Logic inpu for W-phase low-side gae driver 19 LIN2 Logic inpu for V-phase low-side gae driver 2 LIN1 Logic inpu for U-phase low-side gae driver 21 COM2 Low-side logic ground 22 SD2 Low-side shudown signal inpu; faul signal oupu a UVLO_VCC2, OCP, or TSD acivaion 23 VCC2 Low-side logic supply volage inpu 24 U U-phase oupu SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 14 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

15 SLA687MH, SMA/SLA686MH Series 8. Typical Applicaion CR filers and Zener diodes should be added o your applicaion as needed. This is o proec each pin agains surge volages causing malfuncions, and o avoid he IC being used under he condiions exceeding he absolue maximum raings where criical damage is ineviable. Then, check all he pins horoughly under acual operaing condiions o ensure ha your applicaion works flawlessly. VCC VCC1 4 1 VB1 C BOOT1 2 VB2 C BOOT2 HIN3 HIN2 HIN1 5 V COM1 HIN3 HIN2 HIN High-side MIC 3 VB3 1VBB C BOOT3 V DC Conroller LIN3 LIN2 LIN1 Faul R CL C CL 5 V R SD2 5 V SD1 OCL LIN3 LIN2 LIN1 COM2 SD2 VCC Low-side MIC 24 U W V 13 W2 M R RC RC LS2 LS1 C SD2 C RC C SB C DC R S GND Figure8-1. Typical Applicaion (OCL = SD1) SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 15 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

16 SLA687MH, SMA/SLA686MH Series 9. Physical Dimensions 9.1 ZIP24 Fully-molded Type (Leadform 2451) 31 ±.2 Gae burr 4 ±.2 23xP1.27±.1=(29.21) (Roos of pins) 1.2 ± (4.4) 2.2 ± ±.7 (End of pin) (End of pin) D o.55 D o.55 C B 3 ± ±.1 A (End of pin) (Roo of pin) 23xP1.27±.6=29.21±.7 (Ends of pins) 31.3 ±.2 o.55 Seaing plane D D o.55 Enlarged view of A NOTES: - Dimensions in millimeers - Bare lead frame: Pb-free (RoHS complian) - Maximum gae burr heigh is.3 mm. - B depics a pin whose plaed surface may be cracked. - C shows pins wih a minimum inside radius (R) of.65 mm. - D represens a pin illusraed for reference only, no he acual sae of a bend. SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 16 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

17 SLA687MH, SMA/SLA686MH Series 9.2 ZIP24 Fully-molded Type (Leadform 2452) 31±.2 4 ±.2 Gae burr ± ± ±.1 (Roo of pin) R-end XP1.27±.5=29.21±.6 (Ends of pins) (4.5) (4-R1) ±.5 (End of pin) 31.3±.2 (Includes mold flash) NOTES: Dimensions in millimeers - Bare lead frame: Pb-free (RoHS complian) - Maximum gae burr heigh is.3 mm. SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 17 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

18 SLA687MH, SMA/SLA686MH Series 9.3 ZIP24 Heasink Type (Leadform 2175) 31 ± ± ±.2 φ3.2 ±.15 Gae burr φ3.2±.15x ±.2 1.7±.1 C P1.27±.1=(29.21) (Roos of pins) 12.9 ±.2 16 ±.2 (4.4) 2.2 ± ±.6 (End of pin) (End of pin) D o.55 D 9.9 ±.2 o.55 B 2.45 ±.2 A (End of pin) (Roo of pin) 23 P1.27±.6=(29.21) 31.3 ±.2 (Includes mold flash) D o.55 D o.55 Enlarged view of A NOTES: - Dimensions in millimeers - Bare lead frame: Pb-free (RoHS complian) - Maximum gae burr heigh is.3 mm. - B depics a pin whose plaed surface may be cracked. - C shows pins wih a minimum inside radius (R) of.65 mm. - D represens a pin illusraed for reference only, no he acual sae of a bend. SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 18 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

19 SLA687MH, SMA/SLA686MH Series 9.4 ZIP24 Heasink Type (Leadform 2171) 31± ± ± ± ±.1 Gae burr φ3.2± φ3.2 ±.15 ± ± ±.2 5± ±.2 (Roo of pin) R-end (4-R1) (4.5) P1.27±.7=29.21±1 (Ends of pins) (End of pin) 4.5± ±.2 (Includes mold flash) NOTES: Dimensions in millimeers - Bare lead frame: Pb-free (RoHS complian) - Maximum gae burr heigh is.3 mm SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 19 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

20 SLA687MH, SMA/SLA686MH Series 1. Marking Diagram 1.1 ZIP24 Fully-molded Type JAPAN YMDDX S M A x M H Lo Number: Y is he las digi of he year of manufacure ( o 9) M is he monh of he year (1 o 9, O, N, or D) DD is he day of he monh (1 o 31) X is he conrol number Par Number 1.2 ZIP24 Heasink Type JAPAN S L A 6 8 x x M H Y M D D X Par Number Lo Number: Y is he las digi of he year of manufacure ( o 9) M is he monh of he year (1 o 9, O, N, or D) DD is he day of he monh (1 o 31) X is he conrol number SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 2 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

21 SLA687MH, SMA/SLA686MH Series 11. Funcional Descripions Unless specifically noed, his secion uses he following definiions: All he characerisic values given in his secion are ypical values. For pin and peripheral componen descripions, his secion employs a noaion sysem ha denoes a pin name wih he arbirary leer x, depending on conex. Thus, he VCCx pin is used when referring o eiher or boh of he VCC1 and VCC2 pins. The COM1 pin is always conneced o he COM2 pin Turning On and Off he IC The procedures lised below provide recommended sarup and shudown sequences. To urn on he IC properly, do no apply any volage on he VBB, HINx, and LINx pins unil he VCCx pin volage has reached a sable sae (V CC(ON) 12.5 V). I is required o fully charge boosrap capaciors, C BOOTx, a sarup (see Secion ). To urn off he IC, se he HINx and LINx pins o logic low (or L ), and hen decrease he VCCx pin volage Pin Descripions U, V, W1, and W2 These pins are he oupus of he hree phases, and serve as he connecion erminals o he 3-phase moor. The W1 and W2 pins mus be conneced o each oher on a PCB. The U, V, and W1 pins are he grounds for he VB1, VB2, and VB3 pins. The U, V, and W1 pins are conneced o he negaive nodes of boosrap capaciors, C BOOTx. Since high volages are applied o hese oupu pins (U, V, W1, and W2), i is required o ake measures for insulaing as follows: Keep enough disance beween he oupu pins and low-volage races. Coa he oupu pins wih insulaing resin VBB This is he inpu pin for he main supply volage, i.e., he posiive DC bus. All of he power MOSFET drains of he high-side are conneced o his pin. Volage beween he VBB and COMx pins should be se wihin he recommended range of he main supply volage, V DC, given in Secion 2. To suppress surge volages, pu a.1 μf o.1 μf bypass capacior, C S, near he VBB pin and an elecrolyic capacior, C DC, wih a minimal lengh of PCB races o he VBB pin LS1 and LS2 The LS1 pin is conneced o he power MOSFET sources of he U- and V-phases; he LS2 pin is conneced o he power MOSFET source of he W phase. The LS1 and LS2 pins mus be conneced o each oher on a PCB. For curren deecion, hese pins should be conneced o an exernal shun resisor, R S. When connecing he shun resisor, place i as near as possible o he IC wih a minimum lengh of races o he LSx and COMx pins. Oherwise, malfuncion may occur because a longer circui race increases is inducance and hus increases is suscepibiliy o improper operaions. In applicaions where long PCB races are required, add a fas recovery diode, D RS, beween he LSx and COMx pins in order o preven he IC from malfuncioning. U1 6 COM1 21 COM2 VBB LS1 LS C S Add a fas recovery diode o a long race. D RS R S C DC V DC Pu a shun resisor near he IC wih a minimum lengh o he LSx pin. Figure Connecions o LSx Pin VB1, VB2, and VB3 These pins are conneced o boosrap capaciors for he high-side floaing supply. Volages across he VBx and hese oupu pins should be mainained wihin he recommended range (i.e., he Logic Supply Volage, V BS ) given in Secion 2. A boosrap capacior, C BOOTx, should be conneced in each of he races beween he VB1 and U pins, he VB2 and V pins, and he VB3 and W1 pins. For proper sarup, urn on he low-side ransisors firs, hen fully charge he boosrap capacior, C BOOTx. For he capaciance of he boosrap capaciors, C BOOTx, choose he values ha saisfy Equaions (1) and (2). Noe ha capaciance olerance and DC bias characerisics mus be aken ino accoun when you choose appropriae values for C BOOTx. C BOOTx (µf) > 8 L(OFF) (1) 1 µf C BOOTx 22 µf (2) In Equaion (1), le L(OFF) be he maximum off-ime of he low-side ransisor (i.e., he non-charging ime of C BOOTx ), measured in seconds. SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 21 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

22 SLA687MH, SMA/SLA686MH Series Even while he high-side ransisor is no on, volage across he boosrap capacior keeps decreasing due o power dissipaion in he IC. When he VBx pin volage decreases o V BS(OFF) or less, he high-side undervolage lockou (UVLO_VB) sars operaing (see Secion ). Therefore, acual board checking should be done horoughly o validae ha volage across he VBx pin mainains over 11. V (V BS > V BS(OFF) ) during a low-frequency operaion such as a sarup period. As Figure 11-2 shows, a boosrap diode, D BOOTx, and a curren-limiing resisor, R BOOTx, are inernally placed in series beween he VCC1 and VBx pins. Time consan for he charging ime of C BOOTx, τ, can be compued by Equaion (3): τ = C BOOTx R BOOTx, (3) where C BOOTx is he opimized capaciance of he boosrap capacior, and R BOOTx is he resisance of he curren-limiing resisor (21 Ω ± 2%). V CC 4 VCC1 6 COM1 23 VCC2 21 COM2 D BOOT1 R BOOT1 D BOOT2 R BOOT2 D BOOT3 R BOOT3 High-side MIC Low-side MIC HO3 HO2 HO1 VB1 1 VB2 2 VB3 3 VBB 1 24 U 12 V 11 W1 Figure Boosrap Circui M C BOOT1 C BOOT2 C BOOT3 Figure 11-3 shows an inernal level-shifing circui. A high-side oupu signal, HOx, is generaed according o an inpu signal on he HINx pin. When an inpu signal on he HINx pin ransis from low o high (rising edge), a Se signal is generaed. When he HINx inpu signal ransis from high o low (falling edge), a Rese signal is generaed. These wo signals are hen ransmied o he high-side by he level-shifing circui and are inpu o he SR flip-flop circui. Finally, he SR flip-flop circui feeds an oupu signal, Q (i.e., HOx). Figure 11-4 is a iming diagram describing how noise or oher derimenal effecs will improperly influence he level-shifing process. When a noise-induced rapid volage drop beween he VBx and oupu pins (U, V, or W1; hereafer VBx HSx ) occurs afer he Se signal generaion, he nex Rese signal canno be sen o he SR flip-flop circui. And he sae of an HOx signal says logic high (or H ) because he SR flip-flop does no respond. Wih he HOx sae being held high (i.e., V DC he high-side ransisor is in an on-sae), he nex LINx signal urns on he low-side ransisor and causes a simulaneously-on condiion, which may resul in criical damage o he IC. To proec he VBx pin agains such a noise effec, add a boosrap capacior, C BOOTx, in each phase. C BOOTx mus be placed near he IC, and be conneced beween he VBx and HSx pins wih a minimal lengh of races. To use an elecrolyic capacior, add a.1 μf o.1 μf bypass capacior, C Px, in parallel near hese pins used for he same phase. HINx COM1 U1 6 Inpu logic Pulse generaor Se Rese HOx Figure Inernal Level-shifing Circui HINx Se Rese VBx HSx Q S R V BS(ON) Q VBx HSx V BS(OFF) Says logic high Figure Waveforms a VBx HSx Volage Drop VCC1 and VCC2 These are he power supply pins for he buil-in conrol IC. The VCC1 and VCC2 pins mus be exernally conneced on a PCB because hey are no inernally conneced. To preven malfuncion induced by supply ripples or oher facors, pu a.1 μf o.1 μf ceramic capacior, C VCC, near hese pins. To preven damage caused by surge volages, pu an 18 V o 2 V Zener diode, DZ, beween he VCCx and COMx pins. Volages o be applied beween he VCCx and COMx pins should be regulaed wihin he recommended operaional range of V CC, given in Secion 2. SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 22 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

23 SLA687MH, SMA/SLA686MH Series C VCC1 4 VCC1 emperaures and juncion emperaures have sufficien margins agains he absolue maximum ranges, specified in Secion 1. V CC DZ 6 COM1 23 VCC2 C VCC2 21 COM2 Figure VCCx Pin Peripheral Circui COM1 and COM2 These are he logic ground pins for he buil-in conrol IC. The COM1 and COM2 pins should be conneced exernally on a PCB because hey are no inernally conneced. Varying elecric poenial of he logic ground can be a cause of improper operaions. Therefore, connec he logic ground as close and shor as possible o a shun resisor, R S, a a single-poin ground (or sar ground) which is separaed from he power ground (see Figure 11-6). U1 6 COM1 21 COM2 VBB LS1 LS Connec he COM1 and COM2 pins on a PCB. C S R S C DC V DC Creae a single-poin ground (a sar ground) near R S, bu keep i separaed from he power ground. Figure Connecions o Logic Ground HIN1, HIN2, and HIN3; LIN1, LIN2, and LIN3 These are he inpu pins of he inernal moor drivers for each phase. The HINx pin acs as a high-side conroller; he LINx pin acs as a low-side conroller. Figure 11-7 shows an inernal circui diagram of he HINx or LINx pin. This is a CMOS Schmi rigger circui wih a buil-in 2 kω pull-down resisor, and is inpu logic is acive high. Inpu signals applied across he HINx COMx and he LINx COMx pins in each phase should be se wihin he ranges provided in Table 11-1, below. Noe ha dead ime seing mus be done for HINx and LINx signals because he IC does no have a dead ime generaor. The higher PWM carrier frequency rises, he more swiching loss increases. Hence, he PWM carrier frequency mus be se so ha operaional case Table Inpu Signals for HINx and LINx Pins Parameer High Level Signal Low Level Signal Inpu Volage 3 V < V IN < 5.5 V V < V IN <.5 V Inpu Pulse Widh.5 μs.5 μs PWM Carrier 2 khz Frequency Dead Time 1.5 μs HINx (LINx) COM1 (COM2) U1 2 kω 2 kω 2 kω 5 V Figure Inernal Circui Diagram of HINx or LINx Pin Inpu signal Conroller R IN1x R IN2x U1 C INx HINx/ LINx Figure Filer Circui for HINx or LINx Pin If he signals from he microconroller become unsable, he IC may resul in malfuncions. To avoid his even, he oupus from he microconroller oupu line should no be high impedance. Also, if he races from he microconroller o he HINx or LINx pin (or boh) are oo long, he races may be inerfered by noise. Therefore, i is recommended o add an addiional filer or a pull-down resisor near he HINx or LINx pin as needed (see Figure 11-8). Here are filer circui consans for reference: R IN1x : 33 Ω o 1 Ω R IN2x : 1 kω o 1 kω C INx : 1 pf o 1 pf Care should be aken when adding R IN1x and R IN2x o he races. When hey are conneced o each oher, he inpu volage of he HINx and LINx pins becomes slighly lower han he oupu volage of he microconroller. SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 23 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

24 SLA687MH, SMA/SLA686MH Series OCL During OCL operaion, he OCL pin logic level is low. To urn off he high- or low-side ransisors during he OCL operaion, connec he OCL pin o he SD1 or SD2 pin according o which side of ransisors are o be urned off. Figure 11-9 illusraes an inernal circui diagram of he OCL pin and is peripheral circui. Because of is open-collecor naure, he OCL pin should be ied by a pull-up resisor, R CL, o he exernal power supply, which should range from 3. V o 5.5 V. When connecing he OCL and SDx pins, i is recommended o use a 1 kω o 1 kω pull-up resisor. To suppress noise, add a filer capacior, C CL, near he IC wih minimizing a race lengh beween he OCL and COM2 pins. C CL should have a capaciance of.1 μf o.1 µf. Leave he OCL pin open if no used. For more deails on he OCL, see Secion V CL R CL C CL SDx OCL COM2 5 Ω BK Filer 2 kω U1.53 V 2 kω 16 LS1 Figure Inernal Circui Diagram of OCL Pin and Is Peripheral Circui RC Figure 11-1 is an inernal circui diagram describing he RC pin and is peripheral circui. o 5.5 V. R RC should have a resisance of 33 kω o 68 kω; C RC should have a capaciance of 1 pf o.47 μf. If R RC is lef open, he IC canno release he OCP operaion. Conversely, if R RC is shored, he IC canno acivae he OCP circui. If C RC is lef open, P becomes shorer and he IC releases he OCP operaion in a shorer ime correspondingly. Therefore, care should be aken when seing hese componens. Figure is a iming char showing he RC pin waveform during he OCP operaion. The enabled OCP circui urns off he low-side ransisors and pus he SD2 pin ino a low sae. (Secion provides more deails on he OCP.) A he same ime, he inernal power MOSFET of he RC pin, Q RC, urns on, hen he RC pin becomes logic low. Q RC urns off abou 5 μs afer he Q RC urn-on. Subsequenly, he RC pin volage increases wih he ime consan which is deermined by R RC and C RC. When he RC pin volage reaches 2.46 V, he IC releases he OCP operaion. The OCP Hold Time, P, depends on he exernal power supply volage, V RC. The approximae value of P is calculaed by he following equaions: When Exernal Power Supply Volage, V RC = 3.3 V: P = 1.35 R RC C RC. (4) When Exernal Power Supply Volage, V RC = 5 V: RC =.65 R RC C RC. (5) Here is an example: when V RC = 5 V, R RC = 33 kω, and C RC =.47 μf, we find ha RC = 1 ms. LS1 V TRIP BK V RC R RC C RC U1 RC 15 5 Ω 2.46 V RC SD1 5 µs P 2.46 V COM2 21 Q RC Figure Inernal Circui Diagram of RC Pin and Is Peripheral Circui Figure RC Pin Waveform during OCP Operaion The RC pin should be conneced o a pull-up resisor, R RC, and a capacior, C RC, which deermine a ime from OCP acivaion unil OCP release (i.e., he OCP Hold Time, P ). Because of is open-drain naure, he RC pin should be ied by he pull-up resisor, R RC, o he exernal power supply, which should range from 3. V SD1 and SD2 These pins operae as he faul signal oupus and he shudown signal inpus. Secion provides deailed funcional descripions on he faul signal oupu; Secion describes he shudown funcion. SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 24 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

25 SLA687MH, SMA/SLA686MH Series Figure illusraes an inernal circui diagram of he SDx pin and is peripheral circui. Noe ha he SDx pin does no respond o a pulse shorer han an inernal filer of 3.3 μs (yp.). Because of is open-collecor naure, he SDx pin should be ied by a pull-up resisor, R SDx, o he exernal power supply, which should range from 3. V o 5.5 V. I is recommended o use a 3.3 kω o 1 kω pull-up resisor. To suppress noise, add a filer capacior, C SDx, near he IC wih minimizing a race lengh beween he SDx and COMx pins. C SDx should have a capaciance of.1 μf o.1 µf. INT V SDx R SDx C SDx U1 SD1 (SD2) COM1 (COM2) 5 Ω Q SDx 3.3 µs (yp.) Blanking filer Oupu SW urn-off and Q SDx urn-on Figure Inernal Circui Diagram of SDx Pin and Is Peripheral Circui 11.3 Proecion Funcions This secion describes he various proecion circuis provided in he IC. The proecion circuis are as follows: he undervolage lockou for power supplies (UVLO) of he VBx, VCC1, and VCC2 pins; he overcurren proecion (OCP); he hermal shudown (TSD). In case one or more of he following proecions are acuaed, he SD1 or SD2 pin becomes logic low. By receiving a faul signal from he SDx pin, he exernal microconroller can ake a proecive sep such as urning off all he ransisors. The exernal microconroller can also shu down IC operaions by inpuing a faul signal o he SDx pin. In he following funcional descripions, HOx denoes a gae inpu signal on he high-side ransisor, whereas LOx denoes a gae inpu signal on he lowside ransisor. VBx HSx refers o he volages beween he VBx pin and oupu pins (U, V, and W1) Faul Signal Oupu The SDx pin is logic high in normal operaion and is logic low in faul signal oupu operaion. SD1 The SD1 pin becomes logic low while he VCC1 pin undervolage lockou for power supply (UVLO_VCC1) is operaing. SD2 The SD2 pin becomes logic low while one or more of he following proecions are operaing: he VCC2 pin undervolage lockou for power supply (UVLO_VCC2), he overcurren proecion (OCP), and he hermal shudown (TSD). While he SD2 pin is in a low sae, all he low-side ransisors urn off. The exernal microconroller receives he faul signals wih is inerrup pin (INT), and mus be programmed o pu he HINx and LINx pins o logic low wihin he predeermined OCP hold ime, P. P is deermined by he value of he pull-up resisor and capacior which are exernally conneced o he RC pin (see Secion ) Shudown Signal Inpu The SDx pin also acs as he inpu pin of shudown signals. When he SD1 pin becomes logic low, all he high-side ransisors urn off. When he SD2 pin becomes logic low, all he low-side ransisors urn off. The volages and pulse widhs of he shudown signals o be applied are lised in Table Table Shudown Signals Parameer High Level Signal Low Level Signal Inpu Volage Inpu Pulse Widh 3 V < V IN < 5.5 V V < V IN <.5 V 6 μs Connecing he SD1 or SD2 pin o he OCL pin allows he IC o urn off he high- or low-side ransisors a OCL acivaion (see Secion ) Undervolage Lockou for Power Supply (UVLO) In case he gae-driving volages of he oupu ransisors decrease, heir seady-sae power dissipaions increase. This overheaing condiion may cause permanen damage o he IC in he wors case. To preven his even, he IC has he undervolage lockou (UVLO) circuis for each of he VBx, VCC1, and VCC2 pins VBx Pin (UVLO_VB) Figure shows operaional waveforms of he VBx pin undervolage lockou for power supply (i.e., UVLO_VB). When he volage beween he VBx and oupu pins (VBx HSx) decreases o he Logic Operaion Sop Volage (V BS(OFF), 1. V) or less, he UVLO_VB circui in he corresponding phase ges acivaed and ses an HOx signal o logic low. When he volage beween he VBx and HSx pins increases o he Logic Operaion Sar Volage (V BS(ON), 1.5 V) or more, he IC releases he UVLO_VB operaion. Then, he HOx signal becomes logic high a he rising edge of he firs SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 25 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

26 SLA687MH, SMA/SLA686MH Series inpu command afer he UVLO_VB release. Any faul signals are no oupu from he SDx pin during he UVLO_VB operaion. The VBx pin has an inernal filer circui o preven noise-induced malfuncions. HINx LINx increases o he Logic Operaion Sar Volage (V CC(ON), 11.5 V) or more, he IC releases he UVLO_VCC2 operaion. The IC hen resumes ransmiing an LOx signal according o an inpu command on he LINx pin. During he UVLO_VCC2 operaion, he SD2 pin becomes logic low and sends faul signals. The VCC2 pin has an inernal filer circui o preven noise-induced malfuncions. HINx VBx HSx UVLO_VB operaion LINx HOx LOx V BS(OFF) V BS(ON) UVLO release HOx resars a posiive edge afer UVLO_VB release. VCC1 HOx V CC(OFF) UVLO_VCC1 operaion V CC(ON) UVLO release HOx resars a posiive edge afer UVLO_VCC1 release. SDx No SDx oupu a UVLO_VB. LOx Figure UVLO_VB Operaional Waveforms VCC1 Pin (UVLO_VCC1) Figure shows operaional waveforms of he VCC1 pin undervolage lockou for power supply (i.e., UVLO_VCC1). When he VCC1 pin volage decreases o he Logic Operaion Sop Volage (V CC(OFF), 11. V) or less, he UVLO_VCC1 circui ges acivaed and ses an HOx signal o logic low. When he VCC1 pin volage increases o he Logic Operaion Sar Volage (V CC(ON), 11.5 V) or more, he IC releases he UVLO_VCC1 operaion. Then, he HOx signal becomes logic high a he rising edge of he firs inpu command afer he UVLO_VCC1 release. During he UVLO_VCC1 operaion, he SD1 pin becomes logic low and sends faul signals. The VCC1 pin has an inernal filer circui o preven noise-induced malfuncions VCC2 Pin (UVLO_VCC2) Figure shows operaional waveforms of he VCC2 pin undervolage lockou for power supply (i.e., UVLO_VCC2). When he VCC2 pin volage decreases o he Logic Operaion Sop Volage (V CC(OFF), 11. V) or less, he UVLO_VCC2 circui ges acivaed and ses an LOx signal o logic low. When he VCC2 pin volage SD1 Figure UVLO_VCC1 Operaional Waveforms HINx LINx VCC2 HOx LOx SD2 V CC(OFF) UVLO_VCC2 operaion V CC(ON) LOx responds o inpu signal. Figure UVLO_VCC2 Operaional Waveforms SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 26 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

27 SLA687MH, SMA/SLA686MH Series Overcurren Limi (OCL) The overcurren limi (OCL) is a proecion agains relaively low overcurren condiions. When he LS1 pin volage increases o he Curren Limi Reference Volage (V LIM,.53 V) or more, and remains in his condiion for a period of he Curren Limi Blanking Time ( BK, 2. μs) or longer, he OCL circui is acivaed. Then, he OCL pin goes logic low. When he LS1 pin volage falls below V LIM (.53 V), he OCL pin logic level becomes high. Figure is a iming char ha represens operaional waveforms during he OCL operaion where he OCL and SD1 pins are exernally conneced on a PCB. The SD1-OCL pin connecion allows he IC o urn off he high-side ransisors a OCL acivaion. During he OCL operaion, he gae logic levels of he low-side ransisors respond o an inpu command on he LINx pin. The SD1 pin has an inernal filer of 3.3 μs (yp.). Afer he SD1 and OCL pins have become logic high, he high-side ransisors remain urned off unil he firs low-o-high ransiion on an HINx inpu signal occurs (i.e., edge-riggered). HINx LINx LS1 V LIM a rise in he curren running hrough he exernal shun resisor, R S. The buil-in dedicaed circui moniors changes in he LS1 pin volage o deec overcurrens. Figure is a iming char ha represens operaional waveforms during OCP operaion. When he LS1 pin volage increases o he OCP Threshold Volage (V TRIP, 1. V) or more, and remains in his condiion for a period of he OCP Blanking Time ( BK, 2. μs) or longer, he OCP circui is acivaed. When he OCP is acivaed, he IC pus boh he LOx and SD2 oupus o a low sae. The curren flowing hrough R S decreases while he LOx signal is in he low sae. Even if he LS1 pin volage falls below V TRIP, he IC holds he SD2 pin in he low sae for a fixed OCP hold ime ( P ). Then, he oupu ransisors operae according o inpu signals. P is deermined by he RC pin. For deails on he RC pin seing, see Secion U1 BK Filer 2 kω HOU HOV HOW LOU LOV LOW 1 V 2 kω VBB 1 W1 11 U 24 V 12 W2 13 LS2 14 LS COM2 M R S OCL SD1 BK Figure Inernal Circui Diagram of LS1 Pin and Is Peripheral Circui HOx 3.3 µs (yp.) HOx resars a posiive edge afer OCL release. HINx LINx LOx BK BK BK LS1 V TRIP V LIM Figure OCL Operaional Waveforms (OCL = SD) HOx Overcurren Proecion (OCP) The overcurren proecion (OCP) is a proecion agains large inrush currens (i.e., high di/d). Figure is an inernal circui diagram describing he LS1 pin and is peripheral circui. The LS1 pin should be conneced o an exernal shun resisor, R S, on a PCB. The LS1 pin volage increases proporionally o LOx SD1 P LOx responds o inpu signal. SD1 resars auomaically afer P. Figure OCP Operaional Waveforms SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 27 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

28 SLA687MH, SMA/SLA686MH Series The OCP is used for deecing abnormal condiions, such as an oupu ransisor shored. In case shor-circui condiions occur repeaedly, he oupu ransisors can be desroyed. To preven such even, he exernal microconroller, where a faul signal from he SD2 pin is inpu via is inerrup pin (INT), mus be programmed o pu he HINx and LINx pins o logic low wihin a predeermined OCP hold ime, P. For proper shun resisor seing, your applicaion mus mee he following: Use he shun resisor ha has a recommended resisance, R S (see Secion 2). Keep he curren hrough he oupu ransisors below he raed oupu curren (pulse), I OP (see Secion 1). I is required o use a resisor wih low inernal inducance because high-frequency swiching curren will flow hrough he shun resisor, R S. In addiion, choose a resisor wih allowable power dissipaion according o your applicaion. Noe ha overcurrens are undeecable when one or more of he U, V, and W1/W2 pins or heir races are shored o ground (ground faul). In case any of hese pins falls ino a sae of ground faul, he oupu ransisors may be desroyed Thermal Shudown (TSD) The IC incorporaes a hermal shudown (TSD) circui. Figure shows TSD operaional waveforms. In case of overheaing (e.g., increased power dissipaion due o overload, a rise in ambien emperaure a he device, ec.), he IC pus boh he LOx and SD2 oupus o a low sae. The TSD circui in he monolihic IC moniors emperaures (see Secion 6). When he emperaure of he monolihic IC exceeds he TSD Operaing Temperaure (T DH, 135 C), he corresponding TSD circui is acivaed. When he emperaure of he monolihic IC decreases o he TSD Releasing Temperaure (T DL, 15 C) or less, he shudown condiion is released. The ransisors hen resume operaing according o inpu signals. Noe ha juncion emperaures of he oupu ransisors hemselves are no moniored; herefore, do no use he TSD funcion as an overemperaure prevenion for he oupu ransisors. 12. Design Noes 12.1 PCB Paern Layou Figure 12-1 shows a schemaic diagram of a moor driver circui. The moor driver circui consiss of curren pahs having high frequencies and high volages, which also bring abou negaive influences on IC operaion, noise inerference, and power dissipaion. Therefore, PCB race layous and componen placemens play an imporan role in circui designing. Curren loops, which have high frequencies and high volages, should be as small and wide as possible, in order o mainain a low-impedance sae. In addiion, ground races should be as wide and shor as possible so ha radiaed EMI levels can be reduced. VBB 1 V DC HINx High-side MIC C DC LINx T j(mic) HOx LOx T DH TSD operaion T DL LOx responds o inpu signal. Low-side MIC U V W1 11 W2 13 LS LS1 Ground races should be wide and shor. M High-frequency, highvolage curren loops should be as small and wide as possible. Figure High-frequency, High-volage Curren Pahs R S SD2 Figure TSD Operaional Waveforms SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 28 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

29 SLA687MH, SMA/SLA686MH Series 12.2 Consideraions in Heasink Mouning The following are he key consideraions and he guidelines for mouning a heasink: I is recommended o use a meric screw of M2.5. To ighen he screws, use a orque screwdriver. Tighen he wo screws firsly up o abou 3% of he maximum screw orque, hen finally up o 1% of he prescribed maximum screw orque. Perform appropriae ighening wihin he range of screw orque defined in Secion 4. When mouning a heasink, i is recommended o use silicone greases. If a hermally conducive shee or an elecrically insulaing shee is used, package cracks may be occurred due o creases a screw ighening. Therefore, you should conduc horough evaluaions before using hese maerials. When applying a silicone grease, make sure ha here mus be no foreign subsances beween he IC and a heasink. Exreme care should be aken no o apply a silicone grease ono any device pins as much as possible Consideraions in IC Characerisics Measuremen When measuring he breakdown volage or leakage curren of he ransisors incorporaed in he IC, noe ha he gae and source of each ransisor should have he same poenial. Moreover, care should be aken when performing he measuremens, because each ransisor is conneced as follows: All he high-side drains are inernally conneced o he VBB pin. In he U-phase, he high-side source and he low-side drain are inernally conneced, and are also conneced o he U pin. (In he W-phase, he high- and low-side ransisors are unconneced inside he IC.) The gaes of he high-side ransisors are pulled down o he corresponding oupu (U, V, and W1) pins; similarly, he gaes of he low-side ransisors are pulled down o he COM2 pin. When measuring he breakdown volage or leakage curren of he ransisors, noe ha all of he oupu (U, V, and W1), LSx, and COMx pins mus be appropriaely conneced. Oherwise he swiching ransisors may resul in permanen damage. low-side ransisors, connec he LSx pin o be measured o he COM2 pin, hen leave oher unused pins open. COM1 6 COM2 21 High-side MIC Low-side MIC Q 1H Q 1L Q 2L Q 3L VBB 1 Q 2H Q 3H V U W1 12 V 13 W2 LS LS1 Figure Typical Measuremen Circui for Highside Transisor (Q 1H ) in U-phase COM1 6 COM2 21 High-side MIC Low-side MIC Q 1H Q 2H Q 1L Q 2L Q 3L Q 3H VBB 1 U W1 12 V 13 W2 LS LS1 Figure Typical Measuremen Circui for Lowside Transisor (Q 1L ) in U-phase V The following are circui diagrams represening ypical measuremen circuis for breakdown volage: Figure 12-2 shows he high-side ransisor (Q 1H ) in he U-phase; Figure 12-3 shows he low-side ransisor (Q 1L ) in he U-phase. And all he pins ha are no represened in hese figures are open. When measuring he high-side ransisors, leave all he pins no be measured open. When measuring he SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 29 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

30 SLA687MH, SMA/SLA686MH Series 13. Calculaing Power Losses and Esimaing Juncion Temperaure This secion describes he procedures o calculae power losses in all oupu ransisors (power MOSFETs), and o esimae a juncion emperaure. Noe ha he descripions lised here are applicable o he IC, which is conrolled by a 3-phase sine-wave PWM driving sraegy. For quick and easy references, we offer calculaion suppor ools online. Please visi our websie o find ou more. DT42: SLA687xMH and SMA/SLA686xMH Series Calculaion Tool hp:// Toal power loss in a power MOSFET can be obained by aking he sum of he following losses: seady-sae loss, P RON ; swiching loss, P SW ; he seadysae loss of a body diode, P SD. In he calculaion procedure we offer, he recovery loss of a body diode, P RR, is considered negligibly small compared wih he raios of oher losses. The following subsecions conain he mahemaical procedures o calculae hese losses (P RON, P SW, and P SD ) and he juncion emperaure of all power MOSFETs operaing Power MOSFET Seady-sae Loss, P RON Seady-sae loss in a power MOSFET can be compued by using he R DS(ON) vs. I D curves, lised in Secion As expressed by he curves in Figure 13-1, linear approximaions a a range he I D is acually used are obained by: R DS(ON) = α I D + β. R DS(ON) (Ω) y = 2.2x VCC = 15 V 125 C 75 C 25 C I D (A) The values gained by he above calculaion are hen applied as parameers in Equaion (6), below. Hence, he equaion o obain he power MOSFET seady-sae loss, P RON, is: π P RON = 1 2π I D (φ) 2 R DS(ON) (φ) DT dφ = 2 2α 1 3π M cos θ I M 3 + 2β π M cos θ I M 2. (6) Where: I D is he drain curren of he power MOSFET (A), R DS(ON) is he drain-o-source on-resisance of he power MOSFET (Ω), DT is he duy cycle, which is given by DT = 1 + M sin(φ + θ), 2 M is he modulaion index ( o 1), cosθ is he moor power facor ( o 1), I M is he effecive moor curren (A), α is he slope of he linear approximaion in he R DS(ON) vs. I D curve, and β is he inercep of he linear approximaion in he R DS(ON) vs. I D curve Power MOSFET Swiching Loss, P SW Swiching loss in a power MOSFET can be calculaed by Equaion (7), leing I M be he effecive curren value of he moor: P SW = 2 π f C α E I M V DC 3. (7) Where: f C is he PWM carrier frequency (Hz), V DC is he main power supply volage (V), i.e., he VBB pin inpu volage, and α E is he slope on he swiching loss curve (see Secion ). Figure Linear Approximae Equaion of R DS(ON) vs. I D Curve SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 3 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

31 SLA687MH, SMA/SLA686MH Series 13.3 Body Diode Seady-sae Loss, P SD Seady-sae loss in he body diode of a power MOSFET can be compued by using he V SD vs. I SD curves, lised in Secion As expressed by he curves in Figure 13-2, linear approximaions a a range he I SD is acually used are obained by: V SD = α I SD + β. V SD (V) C 75 C 125 C y =.22x +.7 VCC = 15 V 13.4 Esimaing Juncion Temperaure of Power MOSFET The juncion emperaure of all power MOSFETs operaing, T J, can be esimaed wih Equaion (9): T J = R J C {(P ON + P SW + P SD ) 6} + T C. (9) Where: R J-C is he juncion-o-case hermal resisance ( C/W) of all he power MOSFETs operaing, and T C is he case emperaure ( C), measured a he poin defined in Figure I SD (A) Figure Linear Approximae Equaion of V SD vs. I SD Curve The values gained by he above calculaion are hen applied as parameers in Equaion (8), below. Hence, he equaion o obain he body diode seady-sae loss, P SD, is: P SD = 1 π 2π V SD (φ) I SD (φ) (1 DT) dφ = 1 2 α π M cos θ I M π β 1 2 π 8 M cos θ I M. (8) Where: V SD is he source-o-drain diode forward volage of he power MOSFET (V), I SD is he source-o-drain diode forward curren of he power MOSFET (A), DT is he duy cycle, which is given by DT = 1 + M sin(φ + θ), 2 M is he modulaion index ( o 1), cosθ is he moor power facor ( o 1), I M is he effecive moor curren (A), α is he slope of he linear approximaion in he V SD vs. I SD curve, and βis he inercep of he linear approximaion in he V SD vs. I SD curve. SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 31 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

32 SLA687MH, SMA/SLA686MH Series 14. Performance Curves 14.1 Transien Thermal Resisance Curves The following graphs represen ransien hermal resisance (he raios of ransien hermal resisance), wih seadysae hermal resisance = Raio of Transien Thermal Resisance Time (s) Figure Transien Thermal Resisance Curve: SMA686xMH 1. Raio of Transien Thermal Resisance Time (s) Figure Transien Thermal Resisance Curve: SLA6868MH and SLA687MH SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 32 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

33 SLA687MH, SMA/SLA686MH Series 14.2 Performance Curves of Conrol Pars Figure 14-3 o Figure provide performance curves of he conrol pars inegraed in he SLA687MH and he SMA/SLA686MH series, including variey-dependen characerisics and hermal characerisics. T J represens he juncion emperaure of he conrol pars. Table Typical Characerisics of Conrol Pars Figure Number Figure Capion Figure 14-3 Logic Supply Curren, I CC vs. T C (HINx = V, LINx = V) Figure 14-4 Logic Supply Curren, I CC vs. T C (HINx = 5 V, LINx = 5 V) Figure 14-5 Logic Supply Curren, I CC vs. VCCx Pin Volage, V CC Figure 14-6 Logic Supply Curren in 1-phase Operaion (HINx = V), I BS vs. T C Figure 14-7 Logic Supply Curren in 1-phase Operaion (HINx = 5 V), I BS vs. T C Figure 14-8 VBx Pin Volage, V B vs. Logic Supply Curren, I BS (HINx = V) Figure 14-9 Logic Operaion Sar Volage, V BS(ON) vs. T C Figure 14-1 Logic Operaion Sop Volage, V BS(OFF) vs. T C Figure Logic Operaion Sar Volage, V CC(ON) vs. T C Figure Logic Operaion Sop Volage, V CC(OFF) vs. T C Figure UVLO_VB Filering Time vs. T C Figure UVLO_VCC1 Filering Time vs. T C Figure UVLO_VCC2 Filering Time vs. T C Figure High Level Inpu Signal Threshold Volage, V IH vs. T C Figure Low Level Inpu Signal Threshold Volage, V IL vs. T C Figure Inpu Curren a High Level (HINx or LINx), I IN vs. T C Figure High-side Turn-on Propagaion Delay vs. T C (from HINx o HOx) Figure 14-2 Low-side Turn-on Propagaion Delay vs. T C (from LINx o LOx) Figure Minimum Transmiable Pulse Widh for High-side Swiching, HIN(MIN) vs. T C Figure Minimum Transmiable Pulse Widh for Low-side Swiching, LIN(MIN) vs. T C Figure SD1 Pin Filering Time vs. T C Figure SD2 Pin Filering Time vs. T C Figure Curren Limi Reference Volage, V LIM vs. T C Figure OCP Threshold Volage, V TRIP vs. T C Figure OCP Hold Time, P vs. T C Figure OCP Blanking Time, BK(OCP) vs. T C ; Curren Limi Blanking Time, BK(OCL) vs. T C SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 33 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

34 SLA687MH, SMA/SLA686MH Series I CC (ma) VCCx = 15 V, HINx = V, LINx = V Max. 2.5 Typ. 2. Min I CC (ma) VCCx = 15 V, HINx = 5 V, LINx = 5 V Max. 3. Typ. 2.5 Min Figure Logic Supply Curren, I CC vs. T C (HINx = V, LINx = V) Figure Logic Supply Curren, I CC vs. T C (HINx = 5 V, LINx = 5 V) 3. HINx = V, LINx = V 25 VBx = 15 V, HINx = V I CC (ma) C 25 C 3 C I BS (µa) Max. Typ. Min V CC (V) Figure Logic Supply Curren, I CC vs. VCCx Pin Volage, V CC Figure Logic Supply Curren in 1-phase Operaion (HINx = V), I BS vs. T C I BS (µa) VBx = 15 V, HINx = 5 V Max Typ. Min. I BS (µa) VBx = 15 V, HINx = V V CC (V) 125 C -3 C 25 C Figure Logic Supply Curren in 1-phase Operaion (HINx = 5 V), I BS vs. T C Figure VBx Pin Volage, V B vs. Logic Supply Curren, I BS (HINx = V) SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 34 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

35 SLA687MH, SMA/SLA686MH Series Max. Typ Max. Typ. V BS(ON) (V) Min. V BS(OFF) (V) Min Figure Logic Operaion Sar Volage, V BS(ON) vs. T C Figure Logic Operaion Sop Volage, V BS(OFF) vs. T C V CC(ON) (V) Max. Typ. Min. V CC(OFF) (V) Max. Typ. Min Figure Logic Operaion Sar Volage, V CC(ON) vs. T C Figure Logic Operaion Sop Volage, V CC(OFF) vs. T C UVLO_VB Filering Time (µs) Max Typ Min UVLO_VCC1 Filering Time (µs) Max Typ Min Figure UVLO_VB Filering Time vs. T C Figure UVLO_VCC1 Filering Time vs. T C SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 35 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

36 SLA687MH, SMA/SLA686MH Series UVLO_VCC2 Filering Time (µs) Max Typ Min V IH (V) Max. 2. Typ. 1.8 Min Figure UVLO_VCC2 Filering Time vs. T C Figure High Level Inpu Signal Threshold Volage, V IH vs. T C V IL (V) Max. Typ. Min. I IN (µa) 4 INHx/INLx = 5 V 35 Max Typ. 2 Min Figure Low Level Inpu Signal Threshold Volage, V IL vs. T C Figure Inpu Curren a High Level (HINx or LINx), I IN vs. T C 8 7 Max. 8 7 Max. HIN(MIN) (ns) Typ. Min. HIN(MIN) (ns) Typ. Min Figure High-side Turn-on Propagaion Delay vs. T C (from HINx o HOx) Figure Low-side Turn-on Propagaion Delay vs. T C (from LINx o LOx) SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 36 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

37 SLA687MH, SMA/SLA686MH Series HIN(MIN) (ns) 4 35 Max. 3 Typ. 25 Min LIN(MIN) (ns) 45 4 Max Typ. 25 Min Figure Minimum Transmiable Pulse Widh for High-side Swiching, HIN(MIN) vs. T C Figure Minimum Transmiable Pulse Widh for Low-side Swiching, LIN(MIN) vs. T C DS1 (µs) Max. Typ. Min. SD2 (µs) Max. Typ. Min Figure SD1 Pin Filering Time vs. T C Figure SD2 Pin Filering Time vs. T C V LIM (V) Max. Typ. Min. V TRIP (V) Max. Typ. Min Figure Curren Limi Reference Volage, V LIM vs. T C Figure OCP Threshold Volage, V TRIP vs. T C SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 37 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

38 SLA687MH, SMA/SLA686MH Series 3. V RC = 3.3 V, R RC = 36 kω, C RC =.47 μf Max. Typ Max. P (µs) 2.4 Min BK (µs) 2. Typ. 1.5 Min T j ( C) Figure OCP Hold Time, P vs. T C Figure OCP Blanking Time, BK(OCP) vs. T C ; Curren Limi Blanking Time, BK(OCL) vs. T C SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 38 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

39 SLA687MH, SMA/SLA686MH Series 14.3 Performance Curves of Oupu Pars Oupu Transisor Performance Curves SMA686MH R DS(ON) (Ω) VCC = 15 V C C C I D (A) SMA686MH V SD (V) C 75 C 125 C VCC = 15 V I SD (A) SMA686MH Figure Power MOSFET R DS(ON) vs. I D Figure Power MOSFET V SD vs. I SD SMA6862MH R DS(ON) (Ω) 9. VCC = 15 V C C C I D (A) SMA6862MH V SD (V) C 75 C 125 C VCC = 15 V I SD (A) SMA6862MH Figure Power MOSFET R DS(ON) vs. I D Figure Power MOSFET V SD vs. I SD SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 39 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

40 SLA687MH, SMA/SLA686MH Series SMA6863MH, SLA6868MH R DS(ON) (Ω) 6. VCC = 15 V C C C I D (A) SMA6863MH SLA6868MH V SD (V) C 75 C 125 C VCC = 15 V I SD (A) SMA6863MH SLA6868MH Figure Power MOSFET R DS(ON) vs. I D Figure Power MOSFET V SD vs. I SD SMA6865MH, SLA687MH R DS(ON) (Ω) VCC = 15 V 125 C 75 C 25 C SMA6865MH SLA687MH V SD (V) C 75 C 125 C VCC = 15 V SMA6865MH SLA687MH I D (A) I SD (A) Figure Power MOSFET R DS(ON) vs. I D Figure Power MOSFET V SD vs. I SD SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 4 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

41 SLA687MH, SMA/SLA686MH Series Swiching Losses Condiions: VBB = 3 V, half-bridge circui wih inducive load. Swiching Loss, E, is he sum of urn-on loss and urn-off loss SMA686MH T J = 125 C VB = 15 V SMA686MH T J = 125 C VCC = 15 V SMA686MH E (µj) 4 E (µj) 4 2 T J = 25 C 2 T J = 25 C I D (A) Figure High-side Swiching Loss I D (A) Figure Low-side Swiching Loss SMA6862MH T J = 125 C VB = 15 V SMA6862MH T J = 125 C VCC = 15 V SMA6862MH E (µj) T J = 25 C E (µj) T J = 25 C I D (A) Figure High-side Swiching Loss I D (A) Figure Low-side Swiching Loss SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 41 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

42 SLA687MH, SMA/SLA686MH Series SMA6863MH, SLA6868MH E (µj) VB = 15 V T J = 125 C T J = 25 C I D (A) SMA6863MH, SLA6868MH E (µj) VCC = 15 V T J = 125 C T J = 25 C I D (A) SMA6863MH, SLA6868MH Figure High-side Swiching Loss Figure Low-side Swiching Loss SMA6865MH, SLA687MH E (µj) VB = 15 V T J = 125 C T J = 25 C I D (A) SMA6865MH, SLA687MH E (µj) VCC = 15 V T J = 125 C T 5 J = 25 C I D (A) SMA6865MH, SLA687MH Figure High-side Swiching Loss Figure Low-side Swiching Loss SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 42 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

43 SLA687MH, SMA/SLA686MH Series 14.4 Allowable Effecive Curren Curves The following curves represen allowable effecive currens in 3-phase sine-wave PWM driving wih parameers such as ypical R DS(ON) or V CE(SAT), and ypical swiching losses. Operaing condiions: VBB pin inpu volage, V DC = 3 V; VCCx pin inpu volage, V CC = 15 V; modulaion index, M =.9; moor power facor, cosθ =.8; juncion emperaure, T J = 15 C SMA686MH Allowable Effecive Curren (Arms) f C = 2 khz Figure Allowable Effecive Curren (f C = 2 khz): SMA686MH Allowable Effecive Curren (Arms) f C = 16 khz Figure Allowable Effecive Curren (f C = 16 khz): SMA686MH SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 43 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

44 SLA687MH, SMA/SLA686MH Series SMA6862MH Allowable Effecive Curren (Arms) f C = 2 khz Figure Allowable Effecive Curren (f C = 2 khz): SMA6862MH Allowable Effecive Curren (Arms) f C = 16 khz Figure Allowable Effecive Curren (f C = 16 khz): SMA6862MH SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 44 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

45 SLA687MH, SMA/SLA686MH Series SMA6863MH 2.5 f C = 2 khz Allowable Effecive Curren (Arms) Figure Allowable Effecive Curren (f C = 2 khz): SMA6863MH 2.5 f C = 16 khz Allowable Effecive Curren (Arms) Figure Allowable Effecive Curren (f C = 16 khz): SMA6863MH SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 45 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

46 SLA687MH, SMA/SLA686MH Series SMA6865MH 2.5 f C = 2 khz Allowable Effecive Curren (Arms) Figure Allowable Effecive Curren (f C = 2 khz): SMA6865MH 2.5 f C = 16 khz Allowable Effecive Curren (Arms) Figure Allowable Effecive Curren (f C = 16 khz): SMA6865MH SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 46 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

47 SLA687MH, SMA/SLA686MH Series SLA6868MH 2.5 f C = 2 khz Allowable Effecive Curren (Arms) Figure Allowable Effecive Curren (f C = 2 khz): SLA6868MH 2.5 f C = 16 khz Allowable Effecive Curren (Arms) Figure Allowable Effecive Curren (f C = 16 khz): SLA6868MH SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 47 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

48 SLA687MH, SMA/SLA686MH Series SLA687MH 2.5 f C = 2 khz Allowable Effecive Curren (Arms) Figure Allowable Effecive Curren (f C = 2 khz): SLA687MH 2.5 f C = 16 khz Allowable Effecive Curren (Arms) Figure Allowable Effecive Curren (f C = 16 khz): SLA687MH SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 48 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218

49 SLA687MH, SMA/SLA686MH Series 15. Paern Layou Example This secion conains he schemaic diagrams of a PCB paern layou example using an IC from he devices lised in his documen. Figure Top View Figure Boom View SLA687MH, SMA/SLA686MH-DSE Rev.1. SANKEN ELECTRIC CO., LTD 49 Nov. 3, 218 SANKEN ELECTRIC CO., LTD. 218