Fixed-Frequency, 800V CoolSET in DS0-12 Package

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1 ICE3AR1080JG Fixed-Frequency, 800V CoolSET in DS0-12 Package Produc Highlighs 800 V avalanche rugged CoolMOS wih sarup cell Acive Burs Mode o reach he lowes Sandby Power <100 mw Selecable enry and exi burs mode level Adjusable blanking Window for high load jumps Frequency jier and sof driving for low EMI Adjusable brownou feaure Auo Resar proecion for over load, over emperaure, over volage and exernal proecion enable funcion Pb-free lead plaing; RoHS complian Feaures 800 V avalanche rugged CoolMOS wih Sarup Cell Acive Burs Mode for lowes Sandby Power Selecable enry and exi burs mode level 100 khz inernally fixed swiching frequency wih jiering feaure Auo Resar Proecion for Over load, Open Loop, VCC Under volage & Over volage and Over emperaure Exernal auo-resar enable pin Over emperaure proecion wih 50 C hyseresis Buil-in 10 ms Sof Sar Buil-in 20 ms and exendable blanking ime for shor duraion peak power Propagaion delay compensaion for boh maximum load and burs mode Adjusable brownou feaure Overall olerance of Curren Limiing < ±5% BiCMOS echnology for low power consumpion and wide VCC volage range Sof gae drive wih 50 Ω urn on resisor VAC C Bulk Typical Applicaion PG-DSO-12 Applicaions Adaper/Charger, Blue Ray/DVD player, Se-op Box, Digial Phoo Frame Auxiliary power supply of Server, PC, Priner, TV, Home heaer/audio Sysem, Whie Goods, ec Descripion The ICE3AR1080JG (CoolSET -F3R80) is an enhanced 800 V MOSFET version of ICE3BRxx65J (CoolSET -F3R 650V) in DSO-12 package. In paricular i is running a 100 khz, implemened wih brownou feaure, insalling 800 V CoolMOS wih sarup cell. I arges for he low power SMPS wih increased MOSFET volage margin requiremen such as Off-Line baery adapers, DVD R/W, DVD Combi, Blue ray, se op box, auxiliary power supply for Whie Goods, PC and server, ec. In summary, he CoolSET F3R80 provides good volage margin of MOSFET, lowes sandby power, selecable burs level, reduced oupu ripple during burs mode, reliable oupu wih brownou feaure, accurae maximum power conrol for boh maximum power and burs power, low EMI wih frequency jiering and sof gae drive, buil-in and flexible proecions, ec. Therefore, CoolSET F3R80 is a complee soluion for he low power SMPS applicaion. Snubber + Converer DC Oupu - VCC C VCC Drain Power Managemen Sarup Cell R BO1 BBA PWM Conroller Curren Mode Precise Low Tolerance Peak Curren Limiaion Conrol Uni Brownou mode Acive Burs Mode Auo Resar Mode CoolMOS CoolSET -F3R80 (Brownou & Jier) CS FBB GND R Sense R BO2 Figure 1 Typical applicaion Type Package Marking VDS FOSC RDSon 1 230VAC ±15% VAC 2 ICE3AR1080JG PG-DSO-12 3AR1080JG 800 V 100 khz 1.00 Ω 62 W 39 W 1 yp a T=25 C 2 Calculaed maximum inpu power raing a Ta=50 C, Tj=125 C and wihou copper area as hea sink. Daa Shee Please read he Imporan Noice and Warnings a he end of his documen Revision 1.1

2 Table of Conens 1 Pin Configuraion and Funcionaliy Represenaive Block Diagram Funcional Descripion Inroducion Power Managemen Improved Curren Mode PWM-OP PWM-Comparaor Sarup Phase PWM Secion Oscillaor PWM-Lach FF Gae Driver Curren Limiing Leading Edge Blanking Propagaion Delay Compensaion (paened) Conrol Uni Basic and Exendable Blanking Mode Acive Burs Mode (paened) Selecable burs enry level Enering Acive Burs Mode Working in Acive Burs Mode Leaving Acive Burs Mode Proecion Modes VCC OVP, OTP and VCC under volage Over load, open loop proecion Brown ou Mode Acion sequence a BBA pin Elecrical Characerisics Absolue Maximum Raings Absolue Maximum Raings Characerisics Supply Secion Inernal Volage Reference PWM Secion Sof Sar ime Conrol Uni Curren Limiing CoolMOS Secion CoolMOS Performance Characerisics Inpu Power Curve Ouline Dimension Marking Schemaic for recommended PCB layou Revision Hisory Daa Shee 2 Revision 1.1

3 Pin Configuraion and Funcionaliy 1 Pin Configuraion and Funcionaliy Table 1 Pin definiions and funcions Pin Symbol Funcion 1 BBA 2 FBB 3, 9, 10 n.c. no conneced 4 CS 5, 6, 7, 8 Drain 11 VCC 12 GND BBA (Brownou, exended blanking Blanking ime & Auo-resar enable) The BBA pin combines he funcions of brownou, exendable blanking ime for over load proecion and he exernal auo-resar enable. The brownou feaure is o sop he swiching pulse when he inpu volage is dropped o a prese low level. The exendable blanking ime funcion is o exend he buil-in 20 ms blanking ime for over load proecion by adding an exernal capacior o ground. The exernal auo-resar enable funcion is an exernal access o sop he gae swiching and force he IC o ener auo-resar mode. I is riggered by pulling he pin volage o less han 0.4 V. FBB (Feedback & Burs enry conrol) The FBB pin combines he feedback funcion and he burs enry/exi conrol. The regulaion informaion is provided by he FBB pin o he inernal Proecion Uni and he inernal PWM-Comparaor o conrol he duy cycle. The FBB-signal is he only conrol signal in case of ligh load a he Acive Burs Mode. The burs enry/ exi conrol provides an access o selec he enry/exi burs mode level. CS (Curren Sense) The Curren Sense pin senses he volage developed on he shun resisor insered in he source of he inegraed CoolMOS. If CS reaches he inernal hreshold of he Curren Limi Comparaor, he Driver oupu is immediaely swiched off. Furhermore he curren informaion is provided for he PWM comparaor o realize he Curren Mode. Drain (Drain of inegraed CoolMOS ) Pin Drain is he connecion o he Drain of he inegraed CoolMOS. VCC (Power Supply) The VCC pin is he posiive supply of he IC. The operaing range is beween 10.5 V and 25 V. GND (Ground) The GND pin is he ground of he conroller. BBA 1 12 GND FBB 2 11 VCC N.C 3 10 N.C CS 4 9 N.C. Drain 5 8 Drain Drain 6 7 Drain Figure 2 Pin configuraion PG-DSO-12(op view) Daa Shee 3 Revision 1.1

4 Represenaive Block Diagram 2 Represenaive Block Diagram VAC CBulk Snubber Converer DC Oupu VOUT - CVCC VCC Drain Auo-resar Enable Signal #3 TAE #2 RBO1 BBA RBO2 CBK #1 #2 S2 S1 S V Ichg_BO Ichg_EB 0.9V 0.4V VCC 20.5V 4.5V 0.9V C2 C9 C1 C11 C3 Brownou mode & G1 Couner CT1 Thermal Shudown Tj >130 C Power Managemen Inernal Bias Power-Down Rese Sof Sar Block Volage Reference Sof Sar C7 & G7 5.0V Undervolage Lockou 17V 10.5V Sof-Sar Comparaor Oscillaor Duy Cycle max Clock Freq. jier G8 FF1 S R PWM Secion Q CoolMOS Sarup Cell Gae Driver & G9 GND CFB FBB RFB 5.0V 25k 2pF Burs deec and adjus Vcs_burs VFB_burs 4.5V 4.0V VFB_burs 3.5V 3.2V C4 C13 C5 C6a C6b 20ms Blanking Time & G5 20ms Blanking Time 400ns Blanking Time 400ns Blanking Time Spike Blanking 30us Conrol Uni Auo Resar Mode Acive Burs Mode ICE3ARxx80JZ / CoolSET -F3R80 ( Brownou & Jier Mode ) & G V PWM OP C8 Curren Mode PWM Comparaor x3.25 & G10 or G13 Propagaion-Delay Compensaion C10 C12 Vcsh Propagaion-Delay Compensaion-Burs LEB 220ns LEB 180ns Vcsh_burs Curren Limiing S4 1pF 10k D1 CS RSense # : opional exernal componens; #1 : C BK is used o exend he Blanking Time #2 : R BO1 & R BO2 are used for brownou feaure; R BO1 ie o Vcc if no brownou feaure #3 : T AE is used o enable he exernal Auo-resar feaure Figure 3 Represenaive Block Diagram Daa Shee 4 Revision 1.1

5 Funcional Descripion 3 Funcional Descripion All values which are used in he funcional descripion are ypical values. For calculaing he wors cases he min/max values which can be found in secion 4 Elecrical Characerisics have o be considered. 3.1 Inroducion CoolSET -F3R80 brownou and jier 800 V version (ICE3AR1080JG) is he enhanced version of he CoolSET - F3R 650V version (ICE3BRxx65J). I is paricular good for high volage margin low power SMPS applicaion such as auxiliary power supply for PC and server. The major characerisics are ha he IC is developed wih 800 V CoolMOS wih sar up cell, having adjusable brownou feaure, running a 100 khz swiching frequency and packed in DIP-16/12 package. I is derived from F3R 650 V version. Thus mos of he good feaures are reained. Besides, i includes some enhanced feaures and new feaures. The reained good feaures include BiCMOS echnology o reduce power consumpion and increase he Vcc volage range, cycle by cycle curren mode conrol, buil-in 10 ms sof sar o reduce he sress of swiching elemens during sar up, buil-in 20 ms and exended blanking ime for shor period of peak power before enering proecion, acive burs mode for lowes sandby power and propagaion delay compensaion for close power limi beween high line and low line, frequency jiering for low EMI performance, he buil-in auoresar mode proecions for open loop, over load, Vcc OVP, Vcc under volage, ec. and also he mos flexible exernal auo-resar enable, ec. The enhanced feaures include narrowing he feedback volage swing from 0.5V o 0.3V during burs mode so ha he oupu volage ripple can be reduced by 40%, reducion of he fas volage fall ime of he MOSFET by increasing he sof urn-on ime and addiion of 50 Ω urn-on resisor, faser sar up ime by opimizing he VCC capacior o 10 µf and over emperaure proecion wih 50 C hyseresis. The new feaures include adjusable brownou for reliable oupu performance, selecable enry and exi burs mode so ha smaller enry/exi power o burs mode or even no burs mode is possible and he propagaion delay compensaion for burs mode so ha he enry/exi burs mode power is close beween high line and low line. In summary, he CoolSET F3R80 provides good volage margin of MOSFET, lowes sandby power, flexible burs level, reduced oupu ripple during burs mode, reliable oupu wih brownou feaure, accurae power limi for boh maximum power and burs power, low EMI wih frequency jiering and sof gae drive, buil-in and flexible proecions, ec. Therefore, CoolSET F3R80 is a complee soluion for he low power SMPS applicaion. Daa Shee 5 Revision 1.1

6 Funcional Descripion 3.2 Power Managemen Drain VCC Sarup Cell CoolMOS Power Managemen Inernal Bias Undervolage Lockou 17V 10.5V Power-Down Rese Volage Reference 5.0V Sof Sar block Auo Resar Mode Acive Burs Mode Figure 4 Power Managemen The Undervolage Lockou moniors he exernal supply volage V VCC. When he SMPS is plugged o he main line he inernal Sarup Cell is biased and sars o charge he exernal capacior C VCC which is conneced o he VCC pin. This VCC charge curren is conrolled o 0.9 ma by he Sarup Cell. When he V VCC exceeds he onhreshold V VCCon = 17 V he bias circui are swiched on. Then he Sarup Cell is swiched off by he Undervolage Lockou and herefore no power losses presen due o he connecion of he Sarup Cell o he Drain volage. To avoid unconrolled ringing a swich-on, a hyseresis sar up volage is implemened. The swich-off of he conroller can only ake place when V VCC falls below 10.5 V afer normal operaion was enered. The maximum curren consumpion before he conroller is acivaed is abou 200 µa. When V VCC falls below he off-hreshold V VCCoff = 10.5 V, he bias circui is swiched off and he sof sar couner is rese. Thus i ensures ha a every sarup cycle he sof sar sars a zero. The inernal bias circui is swiched off if Auo Resar Mode is enered. The curren consumpion is hen reduced o 320 µa. Once he malfuncion condiion is removed, his block will hen urn back on. The recovery from Auo Resar Mode does no require re-cycling he AC line. When Acive Burs Mode is enered, he inernal Bias is swiched off mos of he ime bu he Volage Reference is kep alive in order o reduce he curren consumpion below 620 µa. Daa Shee 6 Revision 1.1

7 Funcional Descripion 3.3 Improved Curren Mode Sof-Sar Comparaor FBB C8 PWM-Lach R Q Driver S Q 0.6V PWM OP x3.25 Improved Curren Mode CS Figure 5 Curren Mode Curren Mode means he duy cycle is conrolled by he slope of he primary curren. This is done by comparing he FBB signal wih he amplified curren sense signal. Amplified Curren Signal FBB 0.6V Driver on Figure 6 Pulse Widh Modulaion In case he amplified curren sense signal exceeds he FBB signal he on-ime on of he driver is finished by reseing he PWM-Lach (Figure 6). The primary curren is sensed by he exernal series resisor R Sense insered in he source of he inegraed CoolMOS. By means of Curren Mode regulaion, he secondary oupu volage is insensiive o he line variaions. The curren waveform slope will change wih he line variaion, which conrols he duy cycle. The exernal RSense allows an individual adjusmen of he maximum source curren of he inegraed CoolMOS. To improve he Curren Mode during ligh load condiions he amplified curren ramp of he PWM-OP is superimposed on a volage ramp, which is buil by he swich T2, he volage source V1 and a resisor R1 (Figure 6). Every ime he oscillaor shus down for maximum duy cycle limiaion he swich T2 is closed by V OSC. When he oscillaor riggers he Gae Driver, T2 is opened so ha he volage ramp can sar. Daa Shee 7 Revision 1.1

8 Funcional Descripion FBB Sof-Sar Comparaor Oscillaor V OSC T 2 R 1 PWM Comparaor C8 ime delay circui (156ns) 0.6V 10k V 1 PWM-Lach Gae Driver X3.25 PWM OP Volage Ramp Figure 7 Improved Curren Mode In case of ligh load he amplified curren ramp is oo small o ensure a sable regulaion. In ha case he Volage Ramp is a well defined signal for he comparison wih he FBB-signal. The duy cycle is hen conrolled by he slope of he Volage Ramp. By means of he ime delay circui which is riggered by he invered VOSC signal, he Gae Driver is swiched-off unil i reaches approximaely 156 ns delay ime (Figure 8). I allows he duy cycle o be reduced coninuously ill 0% by decreasing V FBB below ha hreshold. V OSC max. Duy Cycle Volage Ramp 0.6V FBB Gae Driver 156ns ime delay Figure 8 Ligh Load Condiions PWM-OP The inpu of he PWM-OP is applied over he inernal leading edge blanking o he exernal sense resisor RSense conneced o pin CS. RSense convers he source curren ino a sense volage. The sense volage is amplified wih a gain of 3.25 by PWM OP. The oupu of he PWM-OP is conneced o he volage source V1. The volage ramp wih he superimposed amplified curren signal is fed ino he posiive inpus of he PWM-- Comparaor C8 and he Sof-Sar-Comparaor (Figure 9). Daa Shee 8 Revision 1.1

9 Funcional Descripion PWM-Comparaor The PWM-Comparaor compares he sensed curren signal of he inegraed CoolMOS wih he feedback signal VFBB (Figure 9). V FBB is creaed by an exernal opocoupler or exernal ransisor in combinaion wih he inernal pull-up resisor RFB and provides he load informaion of he feedback circuiry. When he amplified curren signal of he inegraed CoolMOS exceeds he signal V FBB he PWM-Comparaor swiches off he Gae Driver. 5V RFB Sof-Sar Comparaor FBB C8 PWM-Lach PWM Comparaor Opocoupler 0.6V PWM OP X3.25 CS Improved Curren Mode Figure 9 PWM Conrolling 3.4 Sarup Phase Sof Sar couner Sof Sar finish SofS C7 Sof Sar Sof Sar Sof-Sar Comparaor & Gae Driver G7 0.6V PWM OP x3.25 CS Figure 10 Sof Sar In he Sarup Phase, he IC provides a Sof Sar period o conrol he primary curren by means of a duy cycle limiaion. The Sof Sar funcion is a buil-in funcion and i is conrolled by an inernal couner. Figure 11 Sof Sar Phase Daa Shee 9 Revision 1.1

10 Funcional Descripion When he V VCC exceeds he on-hreshold volage, he IC sars he Sof Sar mode (Figure 11). The funcion is realized by an inernal Sof Sar resisor, a curren sink and a couner. And he ampliude of he curren sink is conrolled by he couner (Figure 12). 5V RSofS SofS Sof Sar Couner 32I 8I 4I 2I I Figure 12 Sof Sar Circui Afer he IC is swiched on, he V SofS volage is conrolled such ha he volage is increased sep-wisely (32 seps) wih he increase of he couns. The Sof Sar couner would send a signal o he curren sink conrol in every 300 µs such ha he curren sink decrease gradually and he duy raio of he gae drive increases gradually. The Sof Sar will be finished in 10 ms ( Sof-Sar) afer he IC is swiched on. A he end of he Sof Sar period, he curren sink is swiched off. Wihin he sof sar period, he duy cycle is increasing from zero o maximum gradually (Figure 13). V SofS VSOFTS32 Sof-Sar Gae Driver Figure 13 Gae drive signal under Sof-Sar Phase In addiion o Sar-Up, Sof-Sar is also acivaed a each resar aemp during Auo Resar. Daa Shee 10 Revision 1.1

11 Funcional Descripion V SofS V SOFTS32 Sof-Sar V FB 4.5V V OUT V OUT Sar-Up Figure 14 Sar Up Phase The Sar-Up ime Sar-Up before he converer oupu volage V OUT is seled mus be shorer han he Sof-Sar Phase Sof-Sar (Figure 14). By means of Sof-Sar here is an effecive minimizaion of curren and volage sresses on he inegraed CoolMOS, he clamp circui and he oupu recifier and i helps o preven sauraion of he ransformer during Sar-Up. 3.5 PWM Secion Oscillaor 0.75 PWM Secion Duy Cycle max Clock Frequency Jier Sof Sar Block Sof Sar Comparaor PWM Comparaor 1 G8 FF1 S R Q Gae Driver & G9 Curren Limiing CoolMOS Gae Figure 15 PWM Secion Block Oscillaor The oscillaor generaes a fixed frequency of 100 khz wih frequency jiering of ±4% (which is ±4 khz) a a jiering period of 4 ms. A capacior, a curren source and curren sink which deermine he frequency are inegraed. The charging and discharging curren of he implemened oscillaor capacior are inernally rimmed in order o achieve a very Daa Shee 11 Revision 1.1

12 Funcional Descripion accurae swiching frequency. The raio of conrolled charge o discharge curren is adjused o reach a maximum duy cycle limiaion of D max = Once he Sof Sar period is over and when he IC goes ino normal operaing mode, he swiching frequency of he clock is varied by he conrol signal from he Sof Sar block. Then he swiching frequency is varied in range of 100 khz ± 4 khz a period of 4 ms PWM-Lach FF1 The oupu of he oscillaor block provides coninuous pulse o he PWM-Lach which urns on/off he inegraed CoolMOS. Afer he PWM-Lach is se, i is rese by he PWM comparaor, he Sof Sar comparaor or he Curren -Limi comparaor. When i is in rese mode, he oupu of he driver is shu down immediaely Gae Driver VCC PWM-Lach 1 50 Gae CoolMOS Gae Driver Figure 16 Gae Driver The driver-sage is opimized o minimize EMI and o provide high circui efficiency. This is done by reducing he swich on slope when exceeding he inegraed CoolMOS hreshold. This is achieved by a slope conrol of he rising edge a he driver s oupu (Figure 17) and adding a 50 Ω gae urn on resisor (Figure 16). Thus he leading swich on spike is minimized. (inernal) V Gae yp. = 160ns 4.6V Figure 17 Gae Rising Slope Furhermore he driver circui is designed o eliminae cross conducion of he oupu sage. During power up, when VCC is below he undervolage lockou hreshold V VCCoff, he oupu of he Gae Driver is se o low in order o disable power ransfer o he secondary side. Daa Shee 12 Revision 1.1

13 Funcional Descripion 3.6 Curren Limiing PWM Lach FF1 Curren Limiing Propagaion-Delay Compensaion PWM-OP & G10 C10 C12 Vcsh LEB 220ns LEB 180ns S4 VCSh_burs Acive Burs Mode Propagaion-Delay Compensaion-Burs or VFB_burs C5 G13 10k D1 1pF FBB CS Figure 18 Curren Limiing Block There is a cycle by cycle peak curren limiing operaion realized by he Curren-Limi comparaor C10. The source curren of he inegraed CoolMOS is sensed via an exernal sense resisor R Sense. By means of RSense he source curren is ransformed o a sense volage V Sense which is fed ino he pin CS. If he volage VSense exceeds he inernal hreshold volage V csh, he comparaor C10 immediaely urns off he gae drive by reseing he PWM Lach FF1. A Propagaion Delay Compensaion is added o suppor he immediae shu down of he inegraed CoolMOS wih very shor propagaion delay. Thus he influence of he AC inpu volage on he maximum oupu power can be reduced o minimal. This compensaion applies o boh he peak load and burs mode. In order o preven he curren limi from disorions caused by leading edge spikes, a Leading Edge Blanking (LEB) is inegraed in he curren sense pah for he comparaors C10, C12 and he PWM-OP. The oupu of comparaor C12 is acivaed by he Gae G10 if Acive Burs Mode is enered. When i is acivaed, he curren limiing is reduced o V csh_burs. This volage level deermines he maximum power level in Acive Burs Mode Leading Edge Blanking V Sense Vcsh LEB = 220ns/180ns Figure 19 Leading Edge Blanking Whenever he inegraed CoolMOS is swiched on, a leading edge spike is generaed due o he primary-side capaciances and reverse recovery ime of he secondary-side recifier. This spike can cause he gae drive o Daa Shee 13 Revision 1.1

14 Funcional Descripion swich off uninenionally. In order o avoid a premaure erminaion of he swiching pulse, his spike is blanked ou wih a ime consan of LEB = 220 ns for normal load and LEB = 180 ns for burs mode Propagaion Delay Compensaion (paened) In case of overcurren deecion, here is always propagaion delay o swich off he inegraed CoolMOS. An overshoo of he peak curren I peak is induced o he delay, which depends on he raio of di/ d of he peak curren (Figure 20). I Sense I peak2 I peak1 I Limi Signal2 I Overshoo2 Signal1 Propagaion Delay I Overshoo1 Figure 20 Curren Limiing The overshoo of Signal 2 is larger han of Signal 1 due o he seeper rising waveform. This change in he slope is depending on he AC inpu volage. Propagaion Delay Compensaion is inegraed o reduce he overshoo due o di/d of he rising primary curren. Thus he propagaion delay ime beween exceeding he curren sense hreshold Vcsh and he swiching off of he inegraed CoolMOS is compensaed over emperaure wihin a wide inpu range. Curren Limiing is hen very accurae. For example, Ipeak = 0.5 A wih R Sense = 2. The curren sense hreshold is se o a saic volage level V csh=1 V wihou Propagaion Delay Compensaion. A curren ramp of di/d = 0.4 A/µs, or dv Sense/d = 0.8 V/µs, and a propagaion delay ime of Propagaion Delay =180 ns leads o an Ipeak overshoo of 14.4%. Wih he propagaion delay compensaion, he overshoo is only around 2% (Figure 21). wih compensaion wihou compensaion V Sense V 1,3 1,25 1,2 1,15 1,1 1,05 1 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 dv Sense d V s Figure 21 Overcurren Shudown The Propagaion Delay Compensaion is realized by means of a dynamic hreshold volage V csh (Figure 21). In case of a seeper slope he swich off of he driver is earlier o compensae he delay. Daa Shee 14 Revision 1.1

15 Funcional Descripion V OSC max. Duy Cycle off ime V Sense Propagaion Delay V csh Signal1 Signal2 Figure 22 Dynamic Volage Threshold V csh Similarly, he same concep of propagaion delay compensaion is also implemened in burs mode wih reduced level, V csh_burs (Figure 18). Wih his implemenaion, he enry and exi burs mode power can be very close beween low line and high line inpu volage. 3.7 Conrol Uni The Conrol Uni conains he funcions for Acive Burs Mode and Auo Resar Mode. The Acive Burs Mode and he Auo Resar Mode boh have 20ms inernal blanking ime. For he over load Auo Resar Mode, he 20 ms blanking ime can be furher exended by adding an exernal capacior a BV pin. Wih he blanking ime, he IC avoids enering ino hose wo modes accidenally. Tha buffer ime is very useful for he applicaion which works in shor duraion of peak power occasionally Basic and Exendable Blanking Mode 5.0V Ichg_EB Auo Resar Mode R OV2 # C BK BV S1 4.5V V C11 C3 Couner CT1 Spike Blanking 30us & G5 S2 FBB 4.5V C4 20ms Blanking Time Conrol Uni Figure 23 Basic and Exendable Blanking Mode There are 2 kinds of Blanking mode; basic mode and he exendable mode. The basic mode is a buil-in 20 ms blanking ime while he exendable mode can exend his blanking ime by connecing an exernal capacior o he BBA pin. For he exendable mode, he gae G5 remains blocked even hough he 20 ms blanking ime is reached. Afer reaching he 20 ms blanking ime he couner is acivaed and he swich S1 is urned on o charge he volage of BBA pin by he consan curren source, I chg_eb. When he volage of BBA pin his 4.5 V, which is sensed by comparaor C11, he couner will increase he couner by 1. Then i swiches off he swich Daa Shee 15 Revision 1.1

16 Funcional Descripion S1 and urns on he swich S2. The volage a BBA pin will be discharged hrough a 500 Ω resisor. When he volage drops o 0.9 V which is sensed by comparaor C3, he swich S2 will be urned off and he swich S1 will be urned on. Then he consan curren I chg_eb will charge he CBK capacior again. When he volage a BBA his 4.5 V which is sensed by comparaor C11, he couner will increase he coun o 2. The process repeas unil i reaches oal coun of 256 (Figure 24). Then he couner will release a high oupu signal. When he AND gae G5 deecs boh high signals a he inpus, i will acivae he 30 ms spike blanking circui and finally he auoresar mode will be acivaed. Figure 24 Waveform a exended blanking ime For example, if C BK=0.1 µf, I chg_eb=720 ma Exended blanking ime = 256*(C BK*(4.5 V-0.9 V)/I chg_eb + C BK*500*ln(4.5/0.9)) = ms Toal blanking ime = 20 ms ms =168.6 ms If here is a resisor R BO2 conneced o BBA pin, he effecive charging curren will be reduced. The blanking ime will be increased. For example, if C BK=0.1 µf, I chg_eb=720 ma, R BO2=12.8 kω, I chg_eb =I chg_eb-(4.5 V+0.9 V)/(2*R BO2)=509 ma Exended blanking ime = 256*(C BK*(4.5 V-0.9 V)/I chg_eb + C BK*500*ln(4.5/0.9)) = ms Toal blanking ime = 20 ms ms = ms where I chg_eb =ne charging curren o C BK Noe: The above calculaion does no include he effec of he brown ou circui where here is exra biasing curren flowing from he inpu. Tha means he exended blanking ime will be shorened wih he line volage change if brown ou circui is implemened Acive Burs Mode (paened) To increase he efficiency of he sysem a ligh load, he mos effecive way is o operae a burs mode. Saring from CoolSET F3, he IC has been employing he acive burs mode and i can achieve he lowes sandby power. ICE3AR1080JG adops he same concep wih some more innovaive improvemens o he feaure. I includes he adjusable enry burs level, close power conrol beween high line and low line and he smaller oupu ripple during burs mode. Mos of he burs mode design in he marke will provide a fixed enry burs mode level which is a raio o he maximum power of he design. ICE3AR1080JG provides a more flexible level which can be seleced exernally. The provision also includes no enering burs mode. Daa Shee 16 Revision 1.1

17 Funcional Descripion Propagaion delay is he major conribuor for he power conrol variaion for DCM flyback converer. I is proved o be effecive in he maximum power conrol. ICE3AR1080JG also apply he same concep in he burs mode. Therefore, he enry and exi burs mode power is also finely conrolled during burs mode. The feedback conrol swing during burs mode will affec he oupu ripple volage direcly. ICE3AR1080JG reduces he swing from 0.5 V o 0.3 V. Therefore, i would have around 40% improvemen for he oupu ripple. CS Vcsh_burs C12 G10 & FF1 Curren Limiing Burs deec and adjus Inernal Bias VFB_burs C5 20 ms Blanking Time FBB C FB 4.0V C13 Acive Burs Mode 3.5V C6a 3.2V C6b & G11 Conrol Uni Figure 25 Acive Burs Mode Selecable burs enry level The burs mode enry level can be seleced by changing he differen capacior C FB a FBB pin. There are 4 levels o be seleced wih differen capacior which are argeed for 10%, 6.67%, 4.38% and 0% of he maximum inpu power. A he same ime, he exi burs levels are argeed o 20%, 13.3%, 9.6% and 0% of he maximum power accordingly. The corresponding capaciance range is from 6.8 nf o 100 pf. The below able is he recommended capaciance range for he enry and exi level wih he C FB capacior. Table 2 C FB C FB versus acive burs mode enry/exi level Enry level Exi level % of P in_max V FB_burs % of P in_max V csh_burs 6.8 nf (5%, X7R) 10% 1.60 V 20% 0.45 V 1nF~2.2 nf (1%, COG) 6.67% 1.42 V 13.3% 0.37 V 220pF~470 pf (1%, COG) 4.38% 1.27 V 9.6% 0.31 V 100 pf (1%, COG) 0% never 0% always The selecion is a he 1s 1 ms of he UVLO ON (V VCC > 17 V) during he 1s sar up bu i does no deec in he subsequen re-sar due o auo-resar proecion. In case here is proecion riggered such as brown ou before sars up, he deecion will be held unil he proecion is removed. When he Vcc reaches he UVLO ON in he 1s sar up, he capacior CFB a FBB pin is charged by a 5V volage source hrough he R FB resisor. When he volage a FBB pin his 4.5 V, he FF4 will be se, he swich S9 is urned ON and he couner will increase by 1. Then he CFB is discharged hrough a 500 Ω resisor. Afer reaching 0.5 V, he FF4 is rese and he swich S9 is urned OFF. Then he CFB capacior is charged by he 5V volage source again unil i reaches 4.5 V. The process repeas unil he end of 1 ms. Then he deecion is ended. Afer ha, he oal number of coun in he couner is compared and he V FB-burs and he V cs_burs are seleced accordingly (Figure 26) Daa Shee 17 Revision 1.1

18 Funcional Descripion 5V VFB_burs VCSh_burs Comparaor logic couner FBB R FB 4.5V C19 UVLO S Q C FB V C20 FF4 R S9 UVLO during 1 s sarup 1ms imer Conrol Uni Figure 26 Acive Burs Mode Enering Acive Burs Mode The FBB signal is kep monioring by he comparaor C5 (Figure 25). During normal operaion, he inernal blanking ime couner is rese o 0. When FBB signal falls below V FB_burs, i sars o coun. When he couner reaches 20 ms and FBB signal is sill below V FB_burs, he sysem eners he Acive Burs Mode. This ime window prevens a sudden enering ino he Acive Burs Mode due o large load jumps. Afer enering Acive Burs Mode, a burs flag is se and he inernal bias is swiched off in order o reduce he curren consumpion of he IC o abou 620 µa. I needs he applicaion o enforce he VCC volage above he Undervolage Lockou level of 10.5 V such ha he Sarup Cell will no be swiched on accidenally. Or oherwise he power loss will increase drasically. The minimum VCC level during Acive Burs Mode depends on he load condiion and he applicaion. The lowes VCC level is reached a no load condiion Working in Acive Burs Mode Afer enering he Acive Burs Mode, he FBB volage rises as V OUT sars o decrease, which is due o he inacive PWM secion. The comparaor C6a moniors he FBB signal. If he volage level is larger han 3.5 V, he inernal circui will be acivaed; he Inernal Bias circui resumes and sars o provide swiching pulse. In Acive Burs Mode he gae G10 is released and he curren limi is reduced o V csh_burs (Figure 3 and Figure 25). In one hand, i can reduce he conducion loss and he oher hand, i can reduce he audible noise. If he load a V OUT is sill kep unchanged, he FBB signal will drop o 3.2 V. A his level he C6b deacivaes he inernal circui again by swiching off he Inernal Bias. The gae G11 is acive again as he burs flag is se afer enering Acive Burs Mode. In Acive Burs Mode, he FBB volage is changing like a saw ooh beween 3.2 V and 3.5 V (Figure 27) Leaving Acive Burs Mode The FBB volage will increase immediaely if here is a high load jump. This is observed by he comparaor C13 (Figure 25). Since he curren limi is reduced o 31%~45% of he maximum curren during acive burs mode, i needs a cerain load jump o raise he FBB signal o exceed 4.0 V. A ha ime he comparaor C5 reses he Acive Burs Mode conrol which in urn blocks he comparaor C12 by he gae G10. The maximum curren can hen be resumed o sabilize V OUT. Daa Shee 18 Revision 1.1

19 Funcional Descripion VFBB 4.0V 3.5V 3.2V Enering Acive Burs Mode Leaving Acive Burs Mode VFB_burs Blanking Timer 20ms Blanking Time V CS Vcsh Curren limi level during Acive Burs Mode Vcsh_burs VVCC 10.5V IVCC 5.7mA 620uA V OUT Figure 27 Signals in Acive Burs Mode Proecion Modes The IC provides Auo Resar mode as he major proecion feaure. Auo Resar mode can preven he SMPS from desrucive saes. There are four kinds of auo resar mode; auo resar mode, non swich auo resar mode, odd skip auo resar mode and odd skip non swich auo resar mode. VVCC 17V Faul deeced Sarup and deec 10.5V VCS Figure 28 Auo resar waveform Daa Shee 19 Revision 1.1

20 Funcional Descripion VVCC 17V Faul deeced Sarup and deec 10.5V VCS No swiching Figure 29 Non swich auo resar waveform The main purpose of he odd skip auo resar is o exend he resar ime such ha he power loss during auo resar proecion can be reduced. This feaure is paricularly good for smaller VCC capacior where he resar ime is shorer. There is no deecing of faul and no swiching pulse for he odd number resar cycle. A he even number of resar cycle he faul deec and sof sar swiching pulses mainained. If he faul persiss, i would coninue he auo-resar mode. However, if he faul is removed, i can release o normal operaion only a he even number auo resar cycle (Figure 29). VVCC Faul deeced No deec Sarup and deec No deec 17V 10.5V VCS Figure 30 Odd skip auo resar waveform Odd skip non swich auo resar mode is similar o odd skip auo resar mode excep he sar up swiching pulses are also suppressed a he even number of he resar cycle. The deecion of faul sill remains a he even number of he resar cycle. When he faul is removed, he IC will resume o normal operaion a he even number of he resar cycle (Figure 30). VVCC Faul deeced No deec Sarup and deec No deec 17V 10.5V VCS No swiching Figure 31 Odd skip non swich auo resar waveform Daa Shee 20 Revision 1.1

21 Funcional Descripion The following able lis down he proecion modes of he CoolSET. Table 3 Proecion funcions Proecion funcion Failure condiion Proecion Mode VCC Overvolage Overemperaure (conroller juncion) Overload / Open loop Vcc Undervolage / Shor Opocoupler Overemperaure (conroller juncion) 1. V CC > 20.5 V and FB > 4.5 V & during sof sar period 2. V CC > 25.5 V T J > 130 C V FBB > 4.5 V, las for 20 ms and exended blanking ime (exended blanking ime couned as 256 imes of V BBA charging and discharging from 0.9 V o 4.5V ) V CC < 10.5 V T J > 130 C Odd skip Auo Resar Odd skip Auo Resar Odd skip Auo Resar Auo Resar Odd skip non swich Auo Resar Exernal proecion enable V AE < 0.4 V Non swich Auo Resar Brownou V BO_ref < 0.9 V and las for 30 ~ 60 µs Non swich Auo Resar VCC OVP, OTP and VCC under volage Thermal Shudown Tj >130 C Auo Resar Mode Rese VVCC < 10.5V 25.5V C2 120μs blanking ime Spike Blanking 30μs Auo Resar mode VCC 20.5V C1 & Volage Reference FBB 4.5V C4 G1 Conrol Uni sofs_period Figure 32 Vcc OVP and OTP There are 2 ypes of VCC over volage proecion; VCC OVP (1) and VCC OVP (2). The VCC OVP (1) akes acion only during he sof sar period. The VCC OVP (2) akes he acion in any condiions. VCC OVP (1) condiion is when V VCC volage is > 20.5 V, V FBB volage is > 4.5 V and during sof sar period, he IC eners ino odd skip Auo Resar Mode. This condiion likely happens during sar up a open loop faul (Figure 30). Vcc OVP (2) condiion is when VVCC volage is > 25.5V, he IC eners ino odd skip Auo Resar Mode (Figure 30). Daa Shee 21 Revision 1.1

22 Funcional Descripion The over emperaure proecion OTP is sensed inside he conroller IC. The Thermal Shudown block keeps on monioring he juncion emperaure of he conroller. Afer deecing a juncion emperaure higher han 130 C, he IC will ener ino he odd skip non swich Auo Resar mode. The ICE3AR1080JG has also implemened wih a 50 C hyseresis. Tha means he IC can only be recovered when he conroller juncion emperaure is dropped 50 C lower han he over emperaure rigger poin (Figure 31). The VCC undervolage and shor opo-coupler will go ino he normal auo resar mode inherenly. In case of VCC undervolage, he Vcc volage drops indefiniely. When i drops below he Vcc under volage lock ou OFF volage (10.5 V), he IC will urn off he IC and he sarup cell will urn on again. Then he Vcc volage will be charged up o UVLO ON volage (17 V) and he IC urns on again provided he sarup cell charge up curren is no drained by he faul. If he faul is no removed, he Vcc will coninue o drop unil i his UVLO OFF volage and he resar cycle repeas. Shor Opocoupler can lead o VCC undervolage because once he opo-coupler (ransisor side) is shored, he feedback volage will drop o zero and here will be no swiching pulse. Then he VCC volage will drop same as he VCC undervolage Over load, open loop proecion 5.0V Volage Reference S1 Ichg_EB Auo Resar Mode Rese VVCC < 10.5V Auo Resar Mode R OV2 # C BK BV 4.5V C11 couner Spike Blanking 30us S V C3 CT1 & G5 FBB 4.5V C4 20ms Blanking Time Conrol Uni Figure 33 Over load, open loop proecion In case of Overload or Open Loop, he V FBB volage exceeds 4.5 V which will be observed by comparaor C4. Then he buil-in blanking ime couner sars o coun. When i reaches 20 ms, he exended blanking ime couner CT1 is acivaed. The swich S2 is urned on and he volage a he BBA pin will be discharged hrough 500 Ω resisor. When i drops o 0.9 V, he swich S2 is urned off and he Swich S1 is urned on. Then a consan curren source Ichg_EB will sar o charge up BBA pin. When he volage his 4.5 V which is moniored by comparaor C11, he swich S1 is urned off and he coun will increase by 1. Then he swich S2 will urn on again and he volage will drop o 0.9 V and rise o 4.5 V again. The coun will hen increase by 1 again. When he oal coun reaches 256, he couner CT1 will sop and i will release a high oupu signal. When boh he inpu signals a AND gae G5 is high, he odd skip Auo Resar Mode is acivaed afer he 30 µs spike blanking ime (Figure 30). The oal blanking ime depends on he addiion of he buil-in and he exended blanking ime. If here is no CBK capacior a BBA pin, he coun will finish wihin 0.1 ms and he equivalen blanking ime is jus he buil-in Daa Shee 22 Revision 1.1

23 Funcional Descripion ime of 20 ms. However, if he C BK capacior is big enough, i can be as long as 1 s. If C BK is 0.1 µf and I chg_eb is 720 µa, he exendable blanking ime is around ms and he oal blanking ime is 168.6ms. Since he BBA pin is a muli-funcion pin, i would share wih differen funcions. The resisor R BO2 from brownou feaure applicaion may however affec he exendable blanking ime (Figure 33). Thus i should ake he R BO2 ino he calculaion of he exendable blanking ime. For example he exended blanking ime would be changed (159.6~191.2 ms) wih differen resisance values of R BO2 resisor. Table 4 shows some examples of C BK, R BO2 vs blanking ime. Table 4 Blanking ime vs C BK and R BO2 C BK R BO2 Exended blanking ime Overall blanking ime 0.1 µf 15 kω ms ms 0.1 µf 37.5 kω ms ms 0.1 µf 47 kω ms ms Noe: R BO2 mus be always 15 kω in enable brownou mode, oherwise overload proecion may no work Brown ou Mode When he AC inpu volage is removed, he volage a he bulk capacior will fall. When i reaches a poin ha he sysem is greaer han he sysem allowed maximum power, he sysem may go ino over load proecion. However, his kind of proecion is no welcome for some of he applicaions such as auxiliary power for PC/server sysem because he oupu is in hiccup mode due o over load proecion (auo resar mode). The brownou mode is o eliminae his phenomenon. The IC will sense he inpu volage hrough he bulk capacior o he BBA pin by 2 poenial divider resisors, R BO1 and R BO2 (Figure 34). When he sysem is powered up, he bulk capacior and he Vcc capacior are charged up a he same ime. When he VCC volage is charged o > 7 V, he brownou circui sars o operae (Figure 34). Since he UVLO is sill a low level as he VCC volage does no reach he 17 V UVLO ON volage. The NAND gae G20 will release a low signal o he flip flop FF5 and he negaive oupu of FF5 will release a high signal o urn on he swich S3. The consan load LD6 will sar o draw consan curren I chg_bo from he BBA pin. Tha means he brownou mode is defaul ON during he sysem sars up. V bulk R BO1 BBA C14 5µs blanking ime G21 S Brownou mode R BO2 0.9V 30µs~60µs blanking ime R Q G22 FF5 S3 UVLO G20 LD6 Ichg_BO Conrol Uni Figure 34 Brown ou deecion circui Daa Shee 23 Revision 1.1

24 Funcional Descripion Once he sysem eners he brown ou mode, here will be no swiching pulse and he IC keeps on monioring he BV signal. If he brown ou signal is no rese, here is no swiching pulse in each resar cycle (Figure 35). VVCC 17V Faul deeced Sarup and deec 10.5V VCS No swiching Figure 35 Brown ou mode waveform The volage a bulk capacior V bulk coninues o increase and so is he volage a BBA. When he BBA volage reaches 0.9 V, he oupu of OPAMP C14 will become low. Through he inverer gae G21, he S inpu of he flip flop FF5 is changed o high. Then he negaive oupu of FF5 is low. The brownou mode is hen OFF and he consan curren load LD6 is also OFF hrough he urn-off of he S3. The sysem will urn on wih sof sar in he coming resar cycle when Vcc reaches he Vcc ON volage 17 V. When here is an inpu volage drop, he BBA volage also drops. When he volage a BBA pin falls below 0.9 V, he oupu of OPAMP C14 is changed o high. The inverer gae G22 will change he high inpu o low oupu. Then he NAND gae G22 will have a high oupu. The negaive oupu of he flip flop FF5 is hen become high. The consan load LD6 is ON again and he IC eners he brownou mode where he Vcc swings beween 10.5 V and 17 V wihou any swiching pulse. The formula o calculae he R BO1 and R BO2 are as below. R BO1=V hys/i chg_bo R BO2=V ref_bo*r BO1/(V BO_l -V ref_bo) where V BO_l: inpu brownou volage (low poin); V hys: inpu brownou hyseresis volage; V ref_bo: IC reference volage for brownou; R BO1 and R BO2: resisors divider from inpu volage o BBA pin For example, I chg_bo=10 µa, V ref_bo=0.9 V, Case 1: if brownou volage is 70 V ACon and 100 V AC off, hen brownou volage, V BO_l=100 V DC, hyseresis volage, V BO_hys=43 V DC, R BO1=4.3 MΩ, R BO2=39 kω Case 2: if brownou volage is 100 V AC on and 120 V AC off, hen brownou volage, V BO_l=141 V DC, hyseresis volage, V BO_hys=28 V DC, R BO1=2.8 MΩ, R BO2=18 kω Daa Shee 24 Revision 1.1

25 Funcional Descripion Case 3: if brownou volage is 120 V AC on and 160 V AC off, hen brownou volage, V BO_l=169 V DC, hyseresis volage, V BO_hys=56 V DC, R BO1=5.6 MΩ, R BO2=30 kω The summary is lised below. Table 5 Brownou resisors vs V BO_hys Case V BO_l V BO_h V BO_hys R BO1 R BO V 143V 43V 4.3MΩ 39KΩ 2 141V 169V 28V 2.8MΩ 18KΩ 3 169V 225V 56V 5.6MΩ 30KΩ Noe: The above calculaion assumes he apping poin (bulk capacior) has a sable volage wih no ripple volage. If here is ripple in he inpu volage, i should ake he highes volage for he calculaion; V BO_l + ripple volage. Besides ha he low side brownou volage V BO_l added wih he ripple volage a he apping poin should always be lower han he high side brownou volage (V BO_h); V BO_h > V BO_l + ripple volage. Oherwise, he brownou feaure canno work properly. In shor, when here is a high load running in sysem before enering brownou, he inpu ripple volage will increase and he brownou volage will increase (V BO_l = V BO_l + ripple volage) a he same ime. If he V BO_hys is se oo small and is close o he ripple volage, hen he brownou feaure canno work properly (V BO_l = V BO_h). If he brownou feaure is no needed, i needs o ie he BBA pin o he Vcc pin hrough a curren limiing resisor, 500 kω~1 MΩ. The BBA pin canno be in floaing condiion. If he brownou feaure is disabled wih a ie up resisor, here is a limiaion of he capacior C BK a he BBA pin. I is as below. Table 6 VCC ie up resisor and C BK_max VCC ie up resisor C BK_max kω 0.47 uf 2 1 MΩ 0.22 uf Acion sequence a BBA pin Since here are 3 funcions a he same BBA pin; brownou, exended blanking ime and he auo-resar enable, he acions of sequence are se as per he below able in case of several feaures happens simulaneously. Table 7 Acion sequence a BBA pin 2 nd 1 s Auo-resar enable Exended blanking ime Brownou Auo-resar enable Auo-resar enable Auo-resar enable Brownou Exended blanking ime Auo-resar enable Exended blanking ime Brownou Brownou Auo-resar enable Exended blanking ime Brownou The op row of he able is he firs happened feaure and he lef column is he second happened feaure. For example, Case 1: Daa Shee 25 Revision 1.1

26 Funcional Descripion The Auo-resar enable feaure happened firs and i follows wih he Exended blanking ime feaure. Then he Auo-resar enable feaure will coninue o hold and he Exended blanking ime feaure is ignored. Case 2: The Exended blanking ime feaure happened firs and i follows wih he Auo-resar enable feaure. Then he Auo-resar enable feaure will ake he prioriy and he Exended blanking ime feaure is overridden. Case 3: The Exended blanking ime feaure happened firs and i follows wih he Brownou feaure. Then he Exended blanking ime feaure will coninue o work unil i ends. Afer ha if he over load faul is removed he Brownou feaure akes he acion. Case 4: The Brownou feaure happened firs and i follows wih he Auo-resar enable feaure. Then he Brownou feaure will coninue o work and he Auo-resar enable feaure is ignored. One ypical case happened is ha he Exended blanking ime feaure happened firs and i follows wih he Brownou feaure. If, however, he over load faul is removed before he end of he exended blanking ime, he Brownou feaure can ake acion only afer 20 ms buffer ime. Daa Shee 26 Revision 1.1

27 Elecrical Characerisics 4 Elecrical Characerisics Noe: All volages are measured wih respec o ground (Pin 12). The volage levels are valid if oher raings are no violaed. 4.1 Absolue Maximum Raings Noe: Absolue maximum raings are defined as raings, which when being exceeded may lead o desrucion of he inegraed circui. For he same reason make sure, ha any capacior ha will be conneced o pin 11 (VCC) is discharged before assembling he applicaion circui. T a=25 C unless oherwise specified. Table 8 Absolue Maximum Raings Parameer Symbol Limi Values Uni Remarks min. max. Drain Source Volage V DS V Pulse drain curren, p limied by Tjmax I D_Puls A Avalanche energy, repeiive AR limied E AR - mj 0.1 by max. T j=150 C 1 Avalanche curren, repeiive AR limied I AR A by max. Tj=150 C VCC Supply Volage V VCC V FBB Volage V FBB V BV Volage V BV V CS Volage V CS V Juncion Temperaure T j C Conroller & CoolMOS Sorage Temperaure T S C Thermal Resisance (Juncion Ambien) R hja K/W Soldering emperaure, wavesoldering T sold C 1.6mm (0.063in.) from case only allowed a leads for 10s ESD Capabiliy (incl. Drain Pin) V ESD - 2 kv Human body model 2 1 Repeiive avalanche causes addiional power losses ha can be calculaed as PAV=EAR*f 2 According o EIA/JESD22-A114-B (discharging a 100pF capacior hrough a 1.5 kω series resisor) Daa Shee 27 Revision 1.1

28 Elecrical Characerisics 4.2 Absolue Maximum Raings Noe: Wihin he operaing range he IC operaes as described in he funcional descripion. Table 9 Absolue Maximum Raings Parameer Symbol Limi Values Uni Remarks min. max. VCC Supply Volage V VCC V VCCoff 25 V Max value limied due o V VCCOVP Juncion Temperaure of Conroller T jcon C Max value limied due o hermal shu down of conroller Juncion Temperaure of CoolMOS T jcoolmos C 4.3 Characerisics Supply Secion Noe: The elecrical characerisics involve he spread of values wihin he specified supply volage and juncion emperaure range TJ from 40 C o 125 C. Typical values represen he median values, which are relaed o 25 C. If no oherwise saed, a supply volage of VCC = 17 V is assumed. Table 10 Supply Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sar Up Curren I VCCsar μ A V VCC =16V VCC Charge Curren I VCCcharge ma V VCC = 0V Leakage Curren of Sar Up Cell and CoolMOS I VCCcharge ma V VCC = 1V I VCCcharge ma V VCC =16V I SarLeak μ A V Drain = 650V a T j=100 C 1 Supply Curren wih Inacive Gae I VCCsup ma Supply Curren wih Acive Gae I VCCsup ma I FBB = 0A Supply Curren in Auo Resar Mode wih Inacive Gae Supply Curren in Acive Burs Mode wih Inacive Gae I VCCresar μ A I FBB = 0A I VCCburs μ A V FBB = 2.5V I VCCburs μ A V VCC = 11.5V, V FBB = 2.5V VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hyseresis V VCCon V VCCoff V VCChys V V V 1 The parameer is no subjeced o producion es - verified by design/characerizaion Daa Shee 28 Revision 1.1

29 Elecrical Characerisics Inernal Volage Reference Table 11 Inernal Volage Reference Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Trimmed Reference Volage V REF V measured a pin FBB I FBB = PWM Secion Table 12 PWM Secion Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Fixed Oscillaor Frequency f OSC khz f OSC khz T j = 25 C Frequency Jiering Range f jier - ±4.0 - khz T j = 25 C Frequency Jiering period T jier ms T j = 25 C Max. Duy Cycle D max Min. Duy Cycle D min V FBB < 0.3 V PWM-OP Gain A V Volage Ramp Offse V Offse V V FBB Operaing Range Min Level V FBmin V V FBB Operaing Range Max level V FBmax V CS=1 V, limied by Comparaor C4 1 FBB Pull-Up Resisor R FB kω Sof Sar ime Table 13 Sof Sar ime Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Sof Sar ime SS ms 1 The parameer is no subjeced o producion es - verified by design/characerizaion Daa Shee 29 Revision 1.1

30 Elecrical Characerisics Conrol Uni Table 14 Conrol Uni Parameer Symbol Limi Values Uni Tes Condiion min. yp. max. Brown ou reference volage for V BO_ref V comparaor C14 Blanking ime volage lower limi for V BKC V Comparaor C3 Blanking ime volage upper limi for V BKC V Comparaor C11 Over Load Limi for Comparaor C4 V FBC V Enry Burs selec High level for V FBC V Comparaor C19 Enry Burs selec Low level for Comparaor C20 V FBC V Acive Burs Mode 10% Pin_max V FB_burs V < 7 couns Enry Level for 6.67% V FB_burs V 8 ~ 39 couns Comparaor C5 4.38% V FB_burs V 40 ~ 191 couns Acive Burs Mode High Level for V FBC6a V In Acive Burs Mode Comparaor C6a Acive Burs Mode Low Level for V FBC6b V Comparaor C6b Acive Burs Mode Level for V FBC V Comparaor C13 Overvolage Deecion Limi for V VCCOVP V V FBB = 5V, during sof sar Comparaor C1 Overvolage Deecion Limi for V VCCOVP V Comparaor C2 Auo-resar enable reference volage V AE V for Comparaor C9 Charging curren for exended I chg_eb μ A blanking ime Charging curren for brownou I chg_bo μ A Thermal Shudown 1 T jsd C Conroller Hyseresis for hermal Shudown 1 T jsd_hys C Buil-in Blanking Time for Overload BK ms Proecion or ener Acive Burs Mode Timer for enry burs selec EBS ms Spike Blanking Time for Auo-Resar Proecion Spike μ s Noe: The rend of all he volage levels in he Conrol Uni is he same regarding he deviaion excep V VCCOVP and V VCCPD 1 The parameer is no subjec o producion es - verified by design/characerizaion. The hermal shudown emperaure refers o he juncion emperaure of he conroller. Daa Shee 30 Revision 1.1

31 Elecrical Characerisics Curren Limiing Table 15 Curren Limiing Parameer Symbol Limi Values Uni Tes Condiion Peak Curren Limiaion (incl. Propagaion Delay) Peak Curren Limiaion during Acive Burs Mode Leading Edge Blanking min. yp. max. V csh V dv sense / d = 0.6V/µs (Figure 21) 20% Pin_max V csh_burs V < 7 couns 13.3% V csh_burs V 8 ~ 39 couns 9.6% Pin_max V csh_burs V 40 ~ 191 couns Normal mode LEB_normal ns Burs mode LEB_burs ns CS Inpu Bias Curren I CSbias μ A V CS =0V CoolMOS Secion Table 16 CoolMOS Secion Parameer Symbol Limi Values Uni Tes Condiion Drain Source Breakdown Volage V (BR)DSS Drain Source On-Resisance R DSon Effecive oupu capaciance, energy relaed Rise Time 2 rise - min. yp. max V V Ω Ω T j = 25 C Tj = 110 C 1 Tj = 25 C Tj=125 C 1 a I D = 1.35 A C o(er) pf V DS = 0 V o 480 V 30 - ns Fall Time 2 fall ns 1 The parameer is no subjeced o producion es - verified by design/characerizaion 2 Measured in a Typical Flyback Converer Applicaion Daa Shee 31 Revision 1.1

32 CoolMOS Performance Characerisics 5 CoolMOS Performance Characerisics Figure 36 Safe Operaing Area (SOA) curve for ICE3AR1080JG Figure 37 SOA emperaure deraing coefficien curve Daa Shee 32 Revision 1.1

33 CoolMOS Performance Characerisics Figure 38 Power dissipaion; P o=f(t a) Figure 39 Drain-source breakdown volage; V BR(DSS)=f(T j), I D=0.25mA Daa Shee 33 Revision 1.1

34 Inpu Power Curve 6 Inpu Power Curve Two inpu power curves giving he ypical inpu power versus ambien emperaure are showed below; V IN=85 V AC~265 V AC (Figure 40) and V IN=230 V AC +/-15% (Figure 41). The curves are derived based on a ypical disconinuous mode flyback model which considers eiher 50% maximum duy raio or 100 V maximum secondary o primary refleced volage (higher prioriy). The calculaion is based on no copper area as heasink for he device. The inpu power already includes he power loss a inpu common mode choke, bridge recifier and he CoolMOS.The device sauraion curren (I T j=125 C) is also considered. To esimae he oupu power of he device, i is simply muliplying he inpu power a a paricular operaing ambien emperaure wih he esimaed efficiency for he applicaion. For example, a wide range inpu volage (Figure 40), operaing emperaure is 50 C, esimaed efficiency is 85%, hen he esimaed oupu power is 33 W (39 W * 85%). Figure 40 Inpu power curve V IN=85~265 V AC; P in=f(t a) Figure 41 Inpu power curve V IN=230 V AC; P in=f(t a) Daa Shee 34 Revision 1.1

35 Ouline Dimension 7 Ouline Dimension Figure 42 PG-DSO-12 (Pb-free lead plaing Plasic Dual-in-Line Ouline) Daa Shee 35 Revision 1.1

36 Marking 8 Marking Figure 43 Marking for ICE3AR1080JG Daa Shee 36 Revision 1.1

37 Schemaic for recommended PCB layou 9 Schemaic for recommended PCB layou Figure 44 Marking for ICE3AR1080JG General guideline for PCB layou design using F3 CoolSET (Figure 44): 1. Sar Ground a bulk capacior ground, C11: Sar Ground means all primary DC grounds should be conneced o he ground of bulk capacior C11 separaely in one poin. I can reduce he swiching noise going ino he sensiive pins of he CoolSET device effecively. The primary DC grounds include he followings. a. DC ground of he primary auxiliary winding in power ransformer, TR1, and ground of C16 and Z11. b. DC ground of he curren sense resisor, R12 c. DC ground of he CoolSET device, GND pin of IC11; he signal grounds from C13, C14, C15 and collecor of IC12 should be conneced o he GND pin of IC11 and hen sar connec o he bulk capacior ground. d. DC ground from bridge recifier, BR1 e. DC ground from he bridging Y-capacior, C4 2. High volage races clearance: High volage races should keep enough spacing o he nearby races. Oherwise, arcing would incur. a. 400 V races (posiive rail of bulk capacior C11) o nearby race: > 2.0 mm b. 600 V races (drain volage of CoolSET IC11) o nearby race: > 2.5 mm 3. Filer capacior close o he conroller ground: Filer capaciors, C13, C14 and C15 should be placed as close o he conroller ground and he conroller pin as possible so as o reduce he swiching noise coupled ino he conroller. Guideline for PCB layou design when > 3 kv lighning surge es applied (Figure 44): 1. Add spark gap Spark gap is a pair of saw-ooh like copper plae facing each oher which can discharge he accumulaed charge during surge es hrough he sharp poin of he saw-ooh plae. Daa Shee 37 Revision 1.1

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