LD7539H 12/24/2012. Green-Mode PWM Controller with BNO and OTP Protections. General Description. Features. Applications. Typical Application. Rev.

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1 12/24/2012 Green-Mode PWM Conroller wih BNO and OTP Proecions Rev. 00 General Descripion The LD7539H is buil-in wih several funcions, proecion and EMI-improved soluion in a iny package. I akes less componens couns or circui space, especially ideal for hose oal soluions of low cos. The implemened funcions include low sarup curren, green-mode power-saving operaion, leading-edge blanking of he curren sensing and inernal slope compensaion. I also feaures more proecions like BNO (Brownou), OTP (Over Temperaure Proecion), OLP (Over Load Proecion) and OVP (Over Volage Proecion) o preven circui damage occurred under abnormal condiions. Furhermore, he Frequency Swapping funcion is o reduce he noise level and hus helps he power circui designers o easily deal wih he EMI filer design by spending minimum amoun of componen cos and developing ime. Feaures High-Volage CMOS Process wih Excellen ESD proecion Very Low Sarup Curren (<14 A) Green Mode Conrol UVLO (Under Volage Lockou) LEB (Leading-Edge Blanking) on CS Pin Inernal Frequency Swapping Inernal Slope Compensaion AC Inpu BNO (Brownou) Proecion OVP (Over Volage Proecion) on Vcc Pin Adjusable OVP (Over Volage Proecion) on CS Pin Adjusable OCP (Over Curren Proecion) on CS Pin OTP (Over Temperaure Proecion) hrough a NTC OLP (Over Load Proecion) 250/-500mA Driving Capabiliy Applicaions Swiching AC/DC Adapor and Baery Charger Open Frame Swiching Power Supply Typical Applicaion AC inpu EMI Filer DC Oupu BNO/ OTP LD7539H COMP CS/OVP phoocoupler GND 1

2 NC CS GND COMP NC BNO/ OTP LD7539H Pin Configuraion DIP-8 (TOP VIEW) SOT-26 (TOP VIEW) CS TOP MARK YYWWPP YWP 39H pp GND COMP BNO/OTP Ordering Informaion YY, Y : Year code (D: 2004, E: ) WW, W : Week code PP : Producion code P39H : LD7539H Par number Package Top Mark Shipping LD7539H GL SOT-26 YWP/39H 3000 /ape & reel LD7539H GN DIP-8 LD7539H GN 3600 /ube /Caron The LD7539H is ROHS complian/ Green Packaged. Proecion Mode Swiching Freq. OVP CS OVP OLP OTP Pin 65kHz Lach Lach Lach Lach Pin Descripions PIN PIN SOT-26 DIP-8 NAME FUNCTION 1 8 GND Ground 2 7 COMP Volage feedback pin (same as he COMP pin in UC384X). Connec a phoo-coupler o close he conrol loop and achieve he regulaion. 3 5 BNO/OTP This pin is conneced o he AC line inpu via wo resisors o achieve brownou funcion. This pin also can achieve he OTP laching funcion by connecing an exernal NTC hermal resisor beween his pin and GND pin. 4 4 CS/OVP Curren sense pin, connec i o sense he MOSFET curren. This pin is also conneced o an auxiliary winding of he PWM ransformer hrough a resisor and a diode for oupu over-volage proecion. 5 2 Supply volage pin 6 1 Gae drive oupu o drive he exernal MOSFET 2

3 Block Diagram 16.0V/ 7.5V In.OSC UVLO PG OK inernal bias & Vref Vref OK All Blocks OVP Lach 26.0V Lach Lach OVP Proecion Proecion2 OVP Driver Sage Green- Mode Conrol Vbias S Q COMP VF RA RB PWM R + Slope Compensaion + VBIAS Leading Edge Blanking 0.85V OCP Duy 4.4V OLP OLP Delay Couner Vbias OLP CS OVP OTP PG S R Q Proecion/ Lach Sample CS BNO/OTP S2 100 ua OTP Lach Delay 0.2V CS OVP GND OTP S1 Logic Conrol 2.55V/ 2.5V BNO S Q Proecion2 A I S1 10uA/ 9uA Brown Ou BNO PG R 3

4 Absolue Maximum Raings Supply Volage -0.3V ~30V COMP, BNO/OTP, CS -0.3V ~6V -0.3V ~Vcc+0.3V Maximum Juncion Temperaure 150 C Sorage Temperaure Range -65 C o 150 C Package Thermal Resisance (SOT-26, JA) 250 C/W Package Thermal Resisance (DIP-8, JA) 100 C/W Power Dissipaion (SOT-26, a Ambien Temperaure = 85 C ) 160mW Power Dissipaion (DIP-8, a Ambien Temperaure = 85 C) 400mW Lead emperaure (Soldering, 10sec) 260 C ESD Volage Proecion, Human Body Model 2.5 KV ESD Volage Proecion, Machine Model 250 V Cauion: Sress exceeding Maximum Raings may damage he device. Maximum Raings are sress raings only. Funcional operaion above he Recommended Operaing Condiions is no implied. Exended exposure o sress above Recommended Operaing Condiions may affec device reliabiliy. Recommended Operaing Condiions Iem Min. Max. Uni Operaing Ambien Temperaure C Operaing Juncion Temperaure C Supply Volage V Capacior F Sar-up resisor Value (AC Side, Half Wave) 400K 1.8M Comp Pin Capacior nf CS Pin Capacior Value pf Noe: 1. I s essenial o connec pin wih a SMD ceramic capacior (0.1 F~0.47 F) o filer ou he undesired swiching noise for sable operaion. This capacior should be placed close o IC pin as possible 2. I s essenial o connec a capacior wih COMP o filer ou he undesired swiching noise for sable operaion. 3. The small signal componens should be placed close o he IC pin as possible. 4

5 Elecrical Characerisics LD7539H (T A = +25 C unless oherwise saed, V CC =15.0V) PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Volage (Vcc Pin) Sarup Curren < UVLO (ON) 9 14 A V COMP =0V ma V COMP =3V 1.85 ma Operaing Curren OLP Tripped/ Lach 0.95 ma (wih 1nF load on pin) BNO Tripped/ Auo 0.45 ma OVP, CS OVP Tripped/ Lach 0.95 ma OTP Pin Tripped/Lach 0.95 ma Holding Curren Vcc=6V (lached) A UVLO (off) V UVLO (on) V BNO Enable Level V OVP Level V OVP pin de-bounce ime * 8 cycle Volage Feedback (Comp Pin) Shor Circui Curren V COMP =0V ma Open Loop Volage COMP pin open V Green Mode Threshold VCOMP * 2.4 V Zero Duy Threshold VCOMP 1.4 V Zero Duy Hyseresis 100 mv Curren Sensing (CS/OVP pin) Maximum Inpu Volage, V CS_OFF V Max. OCP Compensaion Curren, I OCP A Leading Edge Blanking Time, LEB ns Inernal Slope Compensaion 0% o D MAX. (Linearly increase)* 300 mv Inpu impedance 1 M Delay o Oupu * 100 ns Sof Sar Duraion * 6.5 ms Over Volage Proecion (CS/OVP pin) OVP Trip Curren Level V De-bounce Cycle * 8 Cycle 5

6 PARAMETER CONDITIONS MIN TYP MAX UNITS Oscillaor for Swiching Frequency Frequency, FREQ khz Green Mode Frequency, FREQG khz Swapping Frequency V COMP>3V 4.0 khz Temp. Sabiliy (-20 C ~85 C)* 0 5 % Volage Sabiliy (=11V-25V)* 0 1 % Gae Drive Oupu ( Pin) Oupu Low Level =15V, Io=20mA 1 V Oupu High Level =15V, Io=20mA 8 15 V Oupu High Clamp Level V CC =20V 15 V Rising Time Load Capaciance=1000pF ns Falling Time Load Capaciance=1000pF ns Max. Duy % OLP (Over Load Proecion) OLP Trip Level V OLP Delay Time a sar-up OLP+ Sof Sar* 71.5 ms OLP Delay Time afer sar-up ms BNO Pin Proecion (BNO/OTP Pin) Auo Recovery BNO IN Trip Level A BNO Ou Trip Level A BNO IN De-bounce Time V COMP >3V 250 s BNO Ou De-bounce Time V COMP >3V ms OTP Pin Lach Proecion (BNO/OTP Pin) OTP Pin Source Curren A OTP Turn-On Trip Level V OTP Turn-Off Trip Level V OTP pin de-bounce ime V COMP >3V s OTP deec ime * 2 ms *: Guaraneed by design. 6

7 Frequency (KHz) Green Mode Frequency (KHz) Frequency (KHz) Green Mode Frequency (KHz) UVLO (on) (V) UVLO (off) (V) LD7539H Typical Performance Characerisics Fig. 1 UVLO (on) vs. Temperaure Fig. 2 UVLO (off ) vs. Temperaure Fig. 3 Frequency vs. Temperaure Fig. 4 Green Mode Frequency vs. Temperaure Vcc (V) Fig. 5 Frequency vs. Vcc Vcc (V) Fig. 6 Green Mode Frequency vs. Vcc 7

8 OLP (V) Isarup ( A) OVP (V) Max Duy (%) Y Axis Tile LD7539H VCS (off) (V) Fig. 7 Max X Axis Duy Tile vs. Temperaure X Axis Tile Fig. 8 V CS (off) vs. Temperaure Fig. 9 Sarup Curren (Isarup) vs. Temperaure Fig. 10 OVP vs. Temperaure VCOMP (V) Fig. 11 V COMP open loop volage vs. Temperaure Fig. 12 OLP-Trip Level vs. Temperaure 8

9 Applicaion Informaion Operaion Overview The LD7539H mees he green-power requiremen and is inended for he use in hose modern swiching power suppliers and adapors which demand higher power efficiency and power-saving. I inegraes more funcions o reduce he exernal componens couns and he size. Is major feaures are described as below. Under Volage Lockou (UVLO) An UVLO comparaor is implemened in i o deec he volage on he pin. I would assure he supply volage enough o urn on he LD7539H PWM conroller and furher o drive he power MOSFET. As shown in Fig. 13, a hyseresis is buil in o preven he shudown from he volage dip during sarup. Vcc conroller will help o increase he value of R1 and hen reduce he power consumpion on R1. By using CMOS process and he special circui design, he maximum sarup curren for LD7539H is only for 14 A. If a higher resisance value of he R1 is chosen, i will usually spend more ime o sar up. To carefully selec he value of R1 and C1 will opimize he power consumpion and sarup ime. AC inpu EMI Filer Cbulk R1 D1 C1 UVLO(on) UVLO(off) LD7539H CS/OVP GND I(Vcc) operaing curren (~ ma) Fig. 14 sarup curren (~ua) Fig. 13 Sarup Curren and Sarup Circui The ypical sarup circui o generae V CC of he LD7539H is shown in Fig. 14. During he sarup ransien, he V CC is below UVLO hreshold. Before i has sufficien volage o develop pulse o drive he power MOSFET, R1 will provide he sarup curren o charge he capacior C1. Once V CC obains enough volage o urn on he LD7539H and furher o deliver he gae drive signal, i will enable he auxiliary winding of he ransformer o provide supply curren. Lower sarup curren requiremen for he PWM Curren Sensing and Leading-edge Blanking The ypical curren mode of PWM conroller feedbacks boh curren signal and volage signal o close he conrol loop and achieve regulaion. As shown in Fig. 15, he LD7539H deecs he primary MOSFET curren across he CS pin, which is no only for he peak curren mode conrol bu also for he pulse-by-pulse curren limi. The maximum volage hreshold of he curren sensing pin is se a 0.85V. From above, he MOSFET peak curren can be obained from below. 0.85V IPEAK (MAX) RS 9

10 A leading-edge blanking (LEB) ime is included in he inpu of CS pin o preven he false-rigger from he curren spike. Oscillaor and Swiching Frequency The LD7539H is implemened wih Frequency Swapping funcion which helps he power supply designers boh o opimize EMI performance and lower sysem cos. The swiching frequency subsanially ceners a 65KHz, and swap beween a range of ±4KHz. AC Line LD7539H LEB ime Green-Mode Operaion By using he green-mode conrol, he swiching frequency can be reduced a ligh load. The green-mode conrol is Leadrend Technology s own propery. Fig. 16 shows he characerisics of he swiching frequency vs. he comp pin volage (V COMP) CS/OVP GND RS Fig. 15 Oupu Sage and Maximum Duy-Cycle An oupu sage of a CMOS buffer, wih ypical 250/-500mA driving capabiliy, is incorporaed o drive a power MOSFET direcly. And he maximum duy-cycle of LD7539H is limied o 75% o avoid he ransformer sauraion. On/Off Conrol The LD7539H will be urned off if COMP pin is pulled below 1.4V. The oupu of he LD7539H will be disabled immediaely under such condiion. The off-mode will no be released unil he pull-low signal is removed. Fs 65kHz 25kHz Volage Feedback Loop The volage feedback signal is provided from he TL431 a he secondary side hrough he phoo-coupler o he COMP pin of he LD7539H. Similar o UC3842, he LD7539H would carry a diode volage offse a he sage o feed he volage divider a he raio of RA and RB, ha is, R V ( PWM ) (VCOMP VF ) COMPARATOR R 2R A pull-high resisor is embedded inernally and herefore no exra componen is required V COMP (V) Fig. 16 Inernal Slope Compensaion In he convenional applicaions, he problem of he sabiliy is a criical issue for curren mode conrolling, when i operaes over 50% duy-cycle. As UC384X, I akes slope compensaion from injecing he ramp signal of he RT/CT pin hrough a coupling capacior. I herefore requires no exra design for he LD7539H since i has inegraed i already. 10

11 Brownou and OTP Proecion LD7539H is implemened wih BNO and OTP proecion in one pin. As shown in Fig. 17. I deecs BNO signal during posiive cycle of AC inpu volage and OTP signal during negaive cycle, working wih an unfilered AC inpu (Line or Neural). During he posiive cycle, S1 will urn on and BNO comparaor will sense he inpu volage S1. Then, BNO/OTP pin volage will drop o 0.3V, less han he forward conduced volage of D1, D2. Meanwhile, here s no more curren flowing hrough NTC o affec BNO funcion. However, he D1 and D2 will leak a lile a high emperaure. So, he BNO level will be affeced. I s suggesed o choose low leakage curren ype of D1 and D2 (EX: BAS116WS) o increase BNO accuracy. While S1 s curren says a low level (<BNO ou rip level) for more han a de-bounce ime, he BNO comparaor will urn off he conroller and will hiccup beween UVLO-ON and UVLO-OFF unil he S1 s curren draws back above BNO in rip level. The brownou proecion is auo recovery. During negaive cycle, he S1 curren will sink o 2 A and S1 is disabled, leaving S2 enabled o deec OTP funcion. Afer 2ms of OTP deecing ime, he OTP funcion will be disabled and BNO funcion enabled. When S2 is on, a consan curren (I OTP) flows hrough NTC resisor and produces volage over BNO/OTP pin. If he BNO/OTP pin volage is lower han OTP urn-off rip level and lass for a de-bounce ime, lach mode is acivaed and sops PWM swiching. There are wo condiions required o resar i successfully. Firs, cool down he circui so ha NTC resisance will increase and raise BNO/OTP pin volage up above OTP urn-on rip level. Then, remove he AC power cord and resar AC power-on recycling. AC side R BNO1 R BNO2 D1 D2 BNO/OTP NTC S1 I S1 Logic Conrol Fig. 17 S2 Vbias 10uA/ 9uA I OTP 2.55V/ 2.5V OTP Lach OTP Brown Ou BNO Adjusable Over Curren Compensaion (CS/OVP Pin) In general, he power converer can deliver more curren wih high inpu volage han low inpu volage. To compensae his, an offse volage is added o he CS signal by an inernal curren source (I OCP) and an exernal resisor (R OCP) in series beween he sense resisor (Rs) and he CS/OVP pin, as shown in Fig. 18. Differen values of resisors in series wih he CS pin may adjus he amoun of compensaion. The value of I OCP depends on he duy cycle of pin. The equaion of I OCP is decreased as: (0.5 Duy) 600uA(0.1 Duy 0.5) I OCP 0uA (Duy 0.5) 240uA (Duy 0.1) A ligh load, his offse is in same level of magniude as he curren sense signal, i shall be canceled. Therefore he compensaion curren will be fully added once he COMP volage is above 2.9V. R OCP:470 ~1.2k ; C OCP:47pF~390pF 11

12 0.85V OCP I OCP VBIAS Duy/V COMP Ou LEB CS/OVP R OCP AUX Winding C OCP R S Fig. 18 Oupu Over Volage Proecion (CS/OVP Pin) - Lach mode An oupu overvolage proecion is implemened in he LD7539H, as shown in Fig. 19 and 20. The auxiliary winding volage is refleced o secondary winding and herefore he fla volage on he CS/OVP pin is proporional o he oupu volage. By sensing he auxiliary volage via he divided resisors, LD7539H can sample his fla volage level afer some delay ime o perform oupu over-volage proecion. This delay ime is used o ignore he volage ringing from leakage inducance of PWM ransformer. The sampling volage level is compared wih inernal hreshold volage 0.2V. If he sampling volage exceeds he OVP rip level, an inernal couner sars couning subsequen OVP evens. The couner has been added o preven incorrec OVP deecion which migh occur from ESD or lighning evens. However, if ypically 8 cycles of subsequen OVP evens are deeced, he OVP circui swiches he power MOSFET off. As he proecion is lached, he converer resars only afer he inernal lach is rese. Delay Sample OVP Debouce 8 cycle 0.2V CS AUX ROCP Sample Delay CS/OVP Fig. 20 Over Load Proecion (OLP) - Lach mode To proec he circui from damage due o over-load condiion and shor or open-loop condiion, he LD7539H is implemened wih smar OLP funcion. I also feaures lach funcion, see Fig. 21 for he waveform. In case of faul condiion, he feedback sysem will force he volage loop oward he sauraion and hen pull he volage high on COMP pin (VCOMP). When he V COMP ramps up o he OLP hreshold and coninues over OLP delay ime, he proecion will be acivaed and hen urn off he gae oupu o sop he swiching of power circui. As soon as he OLP is ripped, he conroller will lach off unil AC power is removed. Wih he proecion mechanism, he average inpu power will be minimized o remain he componen emperaure and sress wihin he safe operaing area. RS Fig

13 COMP OLP Delay Time OVP Level OLP UVLO(on) OLP rip Level UVLO( off) Lach Released AC inpu Volage AC Off AC On ( Recycle) UVLO(on) UVLO( off) Lach Released AC inpu Volage AC Off AC On ( Recycle) Swiching Non- Swiching Swiching Fig. 21 OVP (Over Volage Proecion) on Vcc - Lach mode LD7539H feaures Vcc OVP in lach mode. As soon as he volage over he Vcc pin rises above OVP hreshold, he oupu gae drive circui will be shudown simulaneous o lach off he power MOSFET. On he conras, if he volage on Vcc pin drops below OVP hreshold and sars AC-recycling again, i will soon resume o normal operaion. Fig. 22 shows is operaion. Swiching Non- Swiching Swiching MOSFET Characerisic Fig. 22 The MOSFET is divided ino hree operaion regions, ohmic region, sauraion region, and he cu-off region, shown as Fig. 23. For swiching power supply applicaions, i shall operae in ohmic and cu-off region. Never reach he region of sauraion; i would cause damage for acing beyond he maximum safey operaing area. I s necessary o check he characerisic of MOSFET. Fig. 24 shows a oem pole archiecure for he circui of. The oupu high level of is a around -1.5V. Refer o on-region characerisics of he MOSFET, check he sauraion curren of VGS H(MIN) o make sure he sauraion curren is high enough o acivae MOSFET o operae in ohmic region. In order no o decrease he volage across VG, i s recommended no o connec a forward diode beween he gae of he MOSFET and pin, for example like Fig 25. In addiion, pull level high o mainain VGSH in high level, for example: 1. Increase N X value o pull level high. 2. Increase capaciance o improve s performance in dropping a sarup ransien, shown as Fig

14 ID VGS5 > VGS4 > VGS3 > VGS2 > VGS1 Ohmic Region Sauraion Region VGS5 C VGS4 N X VGS3 VGS2 VGS1 VG Cu-off region VDS Fig. 23 CS GND RS Fig. 25 C N X VD Large Capaciance of Cap VG VDS UVLO(on) VGS Small Capaciance of Cap GND CS VS RS Fig. 26 Fig

15 Reference Applicaion Circui W (19V/3.42A) Adaper L N F001 R008 L001 C001 D002 C002 PC817 R001 R002 C004 NTC R009 L002 R004 R005 C003 R006 D003 1 D001 C006 C007 2 R007 COMP 6 LD7539H D004 3 CS/OVP BNO/OTP 4 GND C008 D006 5 R011 D005 R014 R016 R017 R018 R012 R015 C009 R013 Q001 R019 RM10 3 F2 5 F1 C101 CY1 R101 D101 C102 C103 R104 IC101 R102 PC817 C105 R103 R105 R106 C104 +Vo GND 15

16 Package Informaion SOT-26 Symbol Dimension in Millimeers Dimensions in Inches Min Max Min Max A B C D F 0.95 TYP TYP H I J M θ

17 Package Informaion DIP-8 Symbol Dimension in Millimeers Dimensions in Inches Min Max Min Max A B C D E F I J L Imporan Noice Leadrend Technology Corp. reserves he righ o make changes or correcions o is producs a any ime wihou noice. Cusomers should verify he daashees are curren and complee before placing order. 17

18 Revision Hisory Rev. Dae Change Noice 00 12/24/2012 Original Specificaion. 18

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