HI-8585, HI ARINC 429 Line Driver PIN CONFIGURATION DESCRIPTION SUPPLY VOLTAGES FUNCTION TABLE FEATURES PIN DESCRIPTION TABLE

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1 February DESCRIPTION The HI-8585 and HI-858 are CMOS inegraed circuis designed o direcly drive he ARINC 49 bus in an 8-pin package. Two logic inpus conrol a differenial volage beween he oupu pins producing a + vol One, a - vol Zero, and a vol Null. The CMOS/TTL conrol inpus are ranslaed o ARINC specified ampliudes using on board band-gap reference. A logic inpu is provided o conrol he slope of he differenial oupu signal. Timing is se by on-chip resisor and capacior and esed o be wihin ARINC requiremens. The HI-8585 has.5 ohms in series wih each line driver oupu. The HI-858 provides he opion o bypass par of he oupu resisance so ha series resisance can be used in exernal proecion circuiry. The HI-8585 or he HI-858 along wih he HI-8588 or he Hi-859 line receivers offer he smalles opions available o ge on and off hearinc bus. FEATURES Direc ARINC 49 line driver inerface in a small package On-chip band-gap reference o se oupu levels On-chip line driver slope conrol and selecion by logic inpu Low curren o 5 vol supplies CMOS / TTL logic pins Plasic and ceramic package opions - surface moun and DIP Thermally enhanced SOIC packages Indusrial & exended emperaure ranges HI-8585, HI-858 PIN CONFIGURATION SUPPLY VOLTAGES V+ = V o V- = -V o - FUNCTION TABLE TXIN TXIN SLP.5 TXAOUT TXBOUT SLOPE X X V - - V V - - V N/A s.5s s.5s N/A PIN DESCRIPTION TABLE PIN SYMBOL SLP.5 TXIN TXIN GND V- TXAOUT TXBOUT V+ SLP.5 8 V+ TXIN TXIN GND 4 5 TXBOUT TXAOUT V- FUNCTION LOGIC INPUT LOGIC INPUT LOGIC INPUT POWER POWER OUTPUT OUTPUT POWER ARINC 49 Line Driver DESCRIPTION CMOS OR TTL, V+ IS OK CMOS OR TTL CMOS OR TTL GROUND - TO -5 VOLTS LINE DRIVER TERMINAL A LINE DRIVER TERMINAL B + TO +5 VOLTS ( DS8585 Rev. O) /

2 HI-8585, HI-858 FUNCTIONAL DESCRIPTION Figure is a block diagram of he line driver. The + and - levels are generaed inernally using a on-chip bandgap reference. Currens for slope conrol are se by zener volages across on-chip resisors. The TXIN and TXIN inpus receive logic signals from a conrol ransmier chip such as he HI-, HI-8 or HI-88. TXAOUT and TXBOUT hold each side of he ARINC bus a Ground unil one of he inpus becomes a One. If for example TXIN goes high, a charging pah is enabled o on an A side inernal capacior while he B side is enabled o -. The charging curren is seleced by he SLP.5 pin. If he SLP.5 pin is high, he capacior is nominally charged from % o 9% in.5µs. If SLP.5 is low, he rise and fall imes are µs. A uniy gain buffer receives he inernally generaed slopes and differenially drives he ARINC line. Curren is limied by he series oupu resisors a each pin. There are no fuses a he oupus of he HI-8585 as exiss on he Hi-88. The HI-8585 has.5 ohms in series wih each oupu and he HI-858 has ohms in series wih each oupu. The HI-858 is for applicaions where exernal series resisance is required, ypically for lighning proecion devices. Boh he HI-8585 and HI-858 are buil using high-speed CMOS echnology. Care should be aken o ensure he V+ and V- supplies are locally decoupled and ha he inpu waveforms are free from negaive volage spikes which may upse he chip s inernal slope conrol circuiry. ONE NULL CURRENT CONTROL A SIDE HI-8585 =.5 OHMS HI-858 = OHMS TXAOUT ZERO - TXIN TXIN ESD PROTECTION AND VOLTAGE TRANSLATION CONTROL LOGIC ONE NULL SLP.5 CURRENT CONTROL B SIDE HI-8585 =.5 OHMS HI-858 = OHMS TXBOUT ZERO CONTROL LOGIC - FIGURE - LINE DRIVER BLOCK DIAGRAM APPLICATION INFORMATION Figure shows a possible applicaion of he HI-8585/8 inerfacing an ARINC ransmi channel from he HI-. HARDWIRED OR DRIVEN FROM LOGIC ARINC Channel ARINC Channel { 8 4 VCC TESTA ROUTA TESTB ROUTB RINA RINB 5 8 SLP.5 V+ TXAOUT HI-8588 HI-8585 TXIN TXBOUT TXIN RXD RXD HI- 8 BIT BUS TXD TXD GND V FIGURE - APPLICATION DIAGRAM

3 HI-8585, HI-858 ABSOLUTE MAXIMUM RATINGS Volages referenced o Ground Supply volages V+... V V-... -V DC curren per inpu pin... +ma Power dissipaion a 5 C plasic DIP....W, derae mw/ C ceramic DIP....5W, derae mw/ C Solder Temperaure (Reflow)... C Sorage Temperaure C o +5 C RECOMMENDED OPERATING CONDITIONS Supply Volages V V o +. V V o -. Temperaure Range Indusrial...-4 C o +85 C Exended C o +5 C NOTE: Sresses above absolue maximum raings or ouside recommended operaing condiions may cause permanen damage o he device. These are sress raings only. Operaion a he limis is no recommended. DC ELECTRICAL CHARACTERISTICS V+ = +V o +, V- = -V o -, T A= Operaing Temperaure Range (unless oherwise saed) PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Inpu volage (TXIN, TXIN, SLP.5) high VIH. - V+ vols low VIL vols Inpu curren (TXIN, TXIN, SLP.5) source IIH V IN = V - -. A sink I IL VIN = - -. A ARINC oupu volage (Differenial) one VDIFF no load; TXAOUT - TXBOUT 9... vols zero VDIFF no load; TXAOUT - TXBOUT vols null VDIFFN no load; TXAOUT - TXBOUT vols ARINC oupu volage (Ref. o GND) one or zero VDOUT no load & magniude a pin vols null VNOUT no load vols Operaing supply curren SLP.5 = V+ V+ IDD TXIN & TXIN = V: no load ma V- IEE TXIN & TXIN = V: no load ma ARINC oupu impedence ZOUT HI ohms HI ohms

4 AC ELECTRICAL CHARACTERISTICS HI-8585, HI-858 V+ = 5.V, V- = -, T = Operaing Temperaure Range (unless oherwise saed) A PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Line Driver propagaion delay Oupu high o low Oupu low o high phlx plhx defined in Figure, no load ns ns Line Driver ransiion imes High Speed Oupu high o low Oupu low o high Low Speed Oupu high o low Oupu low o high fx rx fx rx SLP.5 = V+ pin = logic pin = logic SLP.5 = GND pin = logic pin = logic µs µs µs µs Inpu capaciance () logic C IN - - pf Noes:. Guaraneed bu no esed pin phlx V pin plhx VDIFF pin - pin % rx phlx 9% % plhx 9% % fx rx fx V V V -V FIGURE - LINE DRIVER TIMING 4

5 HI-8585, HI-858 PACKAGE THERMAL CHARACTERISTICS 9, MAXIMUM ARINC LOAD ARINC 49 SUPPLY CURRENT (ma) JUNCTION TEMP, Tj ( C) PACKAGE STYLE DATA RATE Ta = 5 o C Ta =85 o C Ta=5 o C Ta =5 o C Ta =85 o C Ta=5 o C 8 Lead Plasic DIP 8 Lead Plasic ESOIC 5 8 Lead Plasic ESOIC PACKAGE STYLE 8 Lead Plasic DIP 8 Lead Plasic ESOIC 5 8 Lead Plasic ESOIC Low Speed High Speed Low Speed High Speed Low Speed High Speed , 8, 9, TXAOUT and TXBOUT Shored o Ground ARINC 49 SUPPLY CURRENT (ma) JUNCTION TEMP, Tj ( C) DATA RATE Ta = 5 o C Ta =85 o C Ta=5 o C Ta =5 o C Ta =85 o C Ta=5 o C Low Speed High Speed Low Speed High Speed Low Speed High Speed Noes:. All daa aken in sill air on devices soldered o single layer copper PCB (" X 4.5" X.").. A % duy cycle, power supplies. For V power supplies muliply all abulaed values by.8.. Low Speed: Daa Rae =.5 Kbps, Load: R = 4 Ohms, C=nF. 4. High Speed: Daa Rae = Kbps, Load: R = 4 Ohms, C=nF. Daa no presened for C=nF as his is considered unrealisic for high speed operaion Lead Plasic ESOIC (Thermally enhanced SOIC wih buil in hea sink). Hea sink no soldered o he PCB.. 8 Lead Plasic ESOIC (Thermally enhanced SOIC wih buil in hea sink). Hea sink soldered o he PCB.. Similar resuls would be obained wih TXAOUT shored o TXBOUT. 8. For applicaions requiring survival wih coninuous shor circui, operaion above Tj = 5 C is no recommended. 9. Daa will vary depending on air flow and he mehod of hea sinking employed.. Curren values are per supply. HEAT SINK - ESOIC PACKAGES An 8-pin hermally enhanced SOIC package is used for he HI-8585/HI-858 producs. The ESOIC package includes a meal hea sink locaed on he boom surface of he device. This hea sink should be soldered down o he prined circui board for opimum hermal dissipaion. The hea sink is elecrically isolaed from he chip and can be soldered o any ground or power plane. However, since he chip s subsrae is a V+, connecing he hea sink o his power plane is recommended o avoid coupling noise ino he circui. 5

6 HI-8585, HI-858 ORDERING INFORMATION HI - 85XX xx x x Blank F LEAD FINISH Tin / Lead (Sn / Pb) Solder % Mae Tin (Pb-free, RoHS complian) TEMPERATURE RANGE FLOW BURN IN I -4 C TO +85 C I No T -55 C TO +5 C T No M -55 C TO +5 C M Yes PACKAGE DESCRIPTION PD PS CR 8 PIN PLASTIC DIP (8P) 8 PIN PLASTIC NARROW BODY ESOIC (8HNE) 8 PIN CERDIP (8D) no available Pb-free OUTPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY.5 Ohms Ohms 5.5 Ohms Legend: ESOIC - Thermally Enhanced Small Ouline Package (SOIC) wih buil-in hea sink HI PS I - N N LEAD FINISH Tin / Lead (Sn / Pb) Solder - No hea-sink TEMPERATURE RANGE FLOW BURN IN I -4 C TO +85 C I No PACKAGE DESCRIPTION PS 8 PIN PLASTIC NARROW BODY SOIC (8HN) OUTPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY Ohms Legend: SOIC - Small Ouline Package (No Hea-Sink)

7 HI-8585, HI-858 REVISION HISTORY P/N Rev Dae Descripion of Change DS8585 M 5/8/8 Clarified emperaure ranges and added HI-8585PSI-N o Ordering Informaion N 9/9/ Replaced references of seing ARINC oupu levels wih zener diodes o using a band-gap reference circui. O /8/ Updae package drawings. Updae solder reflow emperaure.

8 HI-8585 / HI-858 PACKAGE DIMENSIONS 8-PIN PLASTIC SMALL OUTLINE (ESOIC) - NB (Narrow Body, Thermally Enhanced) millimeers (inches) Package Type: 8HNE Top View 4.9 (.9) BSC.5 ±.5 (. ±.) Boom View.48 ±.5 (. ±.). (.) BSC PIN.9 BSC (.54).5 ±.5 (.88 ±.).4 ±. (. ±.4) SEE DETAIL A.5 (.49) min Elecrically isolaed hea sink pad on boom of package Connec o any ground or power plane for opimum hermal dissipaion o 8 BSC = Basic Spacing beween Ceners is heoreical rue posiion dimension and has no olerance. (JEDEC Sandard 95). (.5) BSC.85 ±.45 (. ±.) DETAIL A.5 ±.5 (. ±.) 8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB (Narrow Body) millimeers (inches) Package Type: 8HN 4.9 BSC (.9).5 ±.5 (. ±.). BSC (.) PIN.9 BSC (.54) See Deail A.4 ±. (. ±.4).5 (.49) min. BSC = Basic Spacing beween Ceners is heoreical rue posiion dimension and has no olerance. (JEDEC Sandard 95). BSC (.5) o 8.85 ±.45 (. ±.) Deail A.5 ±.5 (. ±.) 8

9 HI-8585 / HI-858 PACKAGE DIMENSIONS 8-PIN PLASTIC DIP inches (millimeers) Package Type: 8P.85.5 (9.99.8).5 ±. (.5.54). BSC (.54).. (..54).5.5 (.49.8).5.5 (.49.8).5. (.5 ±.54).5.5 (.9.89).9. (.48.).55. (.9.54).5.5 ( ) BSC = Basic Spacing beween Ceners is heoreical rue posiion dimension and has no olerance. (JEDEC Sandard 95) 8-PIN CERDIP inches (millimeers) Package Type: 8D.8.4 (9.5.).5 min (. min).48. (.99.).9. (.99.54). max (5.8 max). BSC (.54).5 min (.8min) Base Plane Seaing Plane.4. (.9.).. (.54.5).. (4.4.94).5. (.4.5).8. (.45.5).5. (8.89.) BSC = Basic Spacing beween Ceners is heoreical rue posiion dimension and has no olerance. (JEDEC Sandard 95) 9

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