Design of Power Factor Correction Circuit Using AP1662

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1 Applicaion Noe 075 Design of Power Facor Correcion Circui Using AP66 Prepared by Wang Zhao Kun ysem Engineering Deparmen. nroducion. Produc Feaures The AP66 is an acive power facor conrol C which is designed mainly for use as a pre-converer in elecronic ballass, AC-DC adapers and off-line MP applicaions. The AP66 includes an inernal sar-up imer for sand-alone applicaions, a one-quadran muliplier o realize near uniy power facor and a zero curren deecor o ensure DCM boundary conducion operaion. The oem pole oupu sage is capable of driving Power MFET wih 600mA source curren and 800mA sink curren. Designed wih he advanced BiCM process, he AP66 feaures low sar-up curren, low operaion curren and low power dissipaion. The AP66 also has rich proecion feaures including over-volage proecion, inpu under-volage lockou wih hyseresis and muliplier oupu clamp o limi maximum peak curren. Zero Curren Deecion Conrol for DCM Boundary Conducion Mode Adjusable upu Volage wih Precise ver- Volage Proecion Low ar-up Curren wih 0µA Typical Value Low peraing upply Curren wih.5ma Typical Value % Precise nernal eference Volage nernal ar-up Timer Disable Funcion for educed Curren Consumpion Toem Pole upu wih 600mA ource Curren and 800mA ink Curren Under-Volage Lockou wih.5v of Hyseresis CMP MULT C NV 3 Muliplier 8 V Volage egulaion nernal upply 7.5V vervolage Deecion V Vref.V.6V Zero Curren Deecor arer 7 GD Enable Disable 5 6 ZCD Figure. Funcional Block Diagram of AP66 Jan. 0 ev.. 0

2 3. Pin Descripions NV (Pin ): This pin is he invering inpu of he error amplifier. is conneced o an exernal resisor divider which senses he oupu volage. CMP (Pin ): This pin is he error amplifier oupu, i is made available for volage loop compensaion by resisor and capacior combinaion beween pin and his pin. MULT (Pin 3): npu of he muliplier. This pin senses he AC sinusoidal volage and is muliplied wih he CMP pin volage. C (Pin ): npu of he curren conrol comparaor. This pin senses he power swich curren and meashures i agains he oupu of he muliplier. When he C pin volage is higher han he oupu of he muliplier, he gae driver signal will become low o urn off he exernal MFET. ZCD (Pin 5): Zero curren deecion inpu. When he ZCD pin volage decreases below.6v, he gae drive signal becomes oo high o urn on he exernal M- FET. f i is conneced o, he device is disabled. (Pin 6): Ground. Curren reurn for gae driver and conrol circuis of he C. GD (Pin 7): Gae driver oupu. A series resisor beween his pin and he power swich gae can reduce high frequency noise. (Pin 8): upply volage of gae driver and conrol circuis of he C.. Funcional Block Descripions upply Block As shown in Figure, pin 8 is he of AP66. There is a zener diode wih ypical V clamp volage (30 ma raed) o proec he device. A volage regulaor generaes a 7.5V volage o funcion as he C's inernal supply. also produces a precise inernal reference volage (.5V±% a 5 o C) Jan. 0 ev.. 0 Applicaion Noe 075 A hyseresis comparaor deecs he pin's volage. As long as he volage is high enough, he driver is enabled. To sar he AP66, he volage mus exceed he sar-up hreshold volage (3V max.). VN Volage egulaion Error Amplifier The error amplifier regulaes he PFC oupu volage. The inernal reference on he non-invering inpu of he error amplifier is.5v. The error amplifier's invering inpu (NV) is conneced o an exernal resisor divider which senses he oupu volage. The oupu of he error amplifier is one of he wo inpus of muliplier. A compensaion loop is conneced ouside beween he NV and he error amplifier oupu. Normally, he compensaion loop bandwidh is se very low o realize a high power facor for he PFC converer. To ensure fas over volage proecion, he inernal VP funcion is added. f he oupu over volage occurs, excess curren will flow ino he oupu pin of he error amplifier hrough he feedback compensaion capacior. (see Figure 3) The AP66 moniors he curren flowing ino he error amplifier oupu pin. When he deeced curren is higher han 0µA, he dynamic VP is riggered. The C will be disabled and he driver signal will be sopped. f he oupu over volage lass so long ha he oupu of he error amplifier goes below.5v, saic VP will ake place. Also he C will be disabled unil he error amplifier reurns o is linear region. and (see Figure 3) will be seleced as below: Vo.5V Pin (CMP) is he oupu of he error amplifier. A feedback low bandwidh compensaion nework is 8 V VEF Figure. upply Block VVP 0µ A UVL

3 Applicaion Noe 075 placed beween his pin and he NV (pin ) o avoid oupu volage ripple influence o he sysem. n he simples case, his compensaion is jus a capacior, which provides a low frequency pole as well as a high DC gain. A simple mehod o define he capaciance value is o provide abou 0dB aenuaion a wice line frequency (00Hz): C CMP 0 π 0µA.V.6V 5 0.V ZCD Zero Curren Deecor Disable Vin arer V L NV.5V Error Amplifier VP CMP MULT 3 Muliplier PWM Figure. Zero Curren Deecion, Triggering and Disable Block VP Curren Deecor.5V VP + V ds Vo V inpk 0µA AP66 V ZCD Figure 3. Error Amplifier and VP Block Zero Curren Deecion (Figure ) AP66 is a DCM boundary conducion curren mode PFC conroller. Usually, he zero curren deecion (ZCD) volage signal comes from he auxiliary winding of he boos inducor. When he ZCD pin volage decreases below.6v, he gae drive signal becomes oo high o urn on he exernal MFET. 500 mv of hyseresis is provided o avoid false riggering. The boos inducor winding urn raio, m, should be seleced o ensure ZCD pin volage is higher han.v during MFET urned-off. Then V V NM (MAX m. A resisor is placed beween he auxiliary winding and ZCD pin o limi he curren sink o he C. The limiing resisor's acual value can be fine-uned o make he urn-on of he MFET occur exacly on he Jan. 0 ev.. 0 ).V.6V 0.7V V GD i L Figure 5. pimum MFET Turn-on valley of he drain volage oscillaion (When he boos inducor curren reaches zero, he inducor will oscillae wih he MFET drain capaciance. (see Figure 5)). This will minimize he MFET power dissipaion when urned-on. An inernal sarer generaes a pulse o he gae of he MFET a firs sar-up. The frequency of he pulse is abou khz. f he ZCD pin is driven by an exernal signal, he 3

4 AP66 will be synchronized o (he negaive-going edges of) ha signal. f lef floaing, he AP66 will work a he frequency of is inernal sarer. The ZCD pin can be used for disabling he C. Making is volage below 0.5V or shor o he ground will disable he device hus reducing he C supply curren consumpion. Muliplier Block (Figure 6) The muliplier has wo inpus. ne (Pin 3) is he divided AC sinusoidal volage which makes he curren sense comparaor hreshold volage vary from zero o peak value. The oher inpu is he oupu of he error amplifier (Pin ). n his way, he inpu average curren wave will be sinusoidal as well as reflec he load saus. Accordingly, a high power facor and low THD are achieved. The muliplier ransfer characer is designed o be linear over a wide dynamic range, namely, 0 V o 3V for Pin 3 and.0 V o 5.8 V for Pin. The relaionship beween he muliplier oupu and inpus is described as he following equaion: V k ( V.5) V C CMP where V C (Muliplier oupu) is he reference for he curren sense, k is he muliplier gain, V CMP is he volage on pin (error amplifier oupu) and V MULT is he volage on pin 3. Figure 7 shows he ypical muliplier characerisics family. The linear operaion of he muliplier is guaraneed o be in he range of 0 o 3V of V MULT and 0 o.6v of V C. V MULTpk, he peak value for V MULT, will occur a maximum mains volage, should be 3V or below. The MULT pin resisor divider (see Figure 6) will be as follows: 3 + The AP66 is equipped wih a special circui ha reduces he AC inpu curren conducion dead-angle near he zero-crossings of he line volage (crossover disorion). n his way he THD (Toal Harmonic Disorion) of he curren is considerably reduced. Jan. 0 ev.. 0 V MULTpk V NM ( MAX ) MULT V C (V) Error Amplifier Applicaion Noe 075 CMP MULT C 3.7V Muliplier Curren Comparaor and PWM Lach (Figure 6) The PFC swich's urn-on curren is sensed hrough an exernal resisor in series wih he swich. When he sensed volage exceeds he hreshold volage (he muliplier oupu volage), he curren sense comparaor's oupu will become low and he exernal MFET will be urned off. This ensures a cycle-by-cycle curren mode conrol operaion. The sense resisor value is calculaed as follows: V Cpk Cpk where V Cpk is he maximum volage of V C, can be se.6v for linear operaion in he enire working range. The maximum curren sense reference is.8v. The maximum value usually occurs during he sarup process or abnormal condiions such as shor load. 3 Curren ense Comparaor Figure 6. Muliplier Block 0 3 V MULT (V) Figure 7. Muliplier Characerisics Family s V CMP.6V V CMP.8V V CMP 3V V CMP 3.V V CMP 3.5V V CMP V V CMP.5V V CMP 5V V CMP Max

5 When he power MFET is urned on, a narrow spike on he leading edge of he curren waveform can usually be observed. There is an inernal /C filer in AP66 o aenuae his noise and preven he false riggering caused by he urn-on spike. n low power applicaions, he exernal /C filer conneced o he C pin is no needed. The AP66 oem pole oupu sage is capable of driving a Power MFET or GBT wih 600mA source curren and 800mA sink curren. Pin 6 is he Ground of he C. This pin acs as he curren reurn boh for he inernal circuiry signal and for he gae drive curren. These wo pahs should be laid ou separaely in he prined circui board. 5. Boos Circui Basic Design The mos popular power facor correcion opology is he Boos circui. The boos converer consiss of a boos inducor (L), a conrolled power swich (), a diode (D), an oupu capacior (C ) and a conrol circui (see Figure 8). The goal of he PFC is o shape he inpu curren in a sinusoidal waveform, in-phase wih he inpu sinusoidal volage. To do his, he AP66 uses he so-called DCM boundary Conducion Mode echnique. Figure 9 shows he inducor curren waveform and MFET gae drive signal. During a line frequency period, he urn-on ime of MFET is kep consan, hus he inducor peak curren is in rack wih inpu sinusoidal volage waveform. When MFET urns off, he inducor curren will decrease. Jus afer he inducor curren reaches zero, MFET will urn on again. Applicaion Noe 075 Boos nducor Through he following calculaion, he insananeous swiching frequency along a line cycle equaion can be found: f sw ( V ( θ ) VNM sin( θ )) V L P V The swiching frequency will be a he minimum level a he op of he sinusoid and a he maximum level a he zero crossings of he line volage. Figure 0 shows an example of he swiching frequency changing during he half line cycle. The absolue minimum frequency f W(MN) can occur a eiher he maximum or he minimum mains volage. Thus he inducor value is defined by: ( V L V f NM WMN where V NM can be eiher V NM(MN) or V N- M(MAX). The lower value for L can be seleced. The suggesed minimum swiching frequency is greaer han he frequency of he inernal sarer (5kHz) o ensure a correc DCM boundary Conducion Mode operaion. The maxim inducor curren is: LMAX _ pk V η V By AP mehod, we can selec a ype of core. Then he inducor primary urns can be calculaed according ) V P V NM ( MN ) NM η NM η L D V N ~ C N C Load AP66 Jan. 0 ev.. 0 Figure 8. Boos Converer Circui 5

6 Applicaion Noe 075 o he following mehods: L N Bmax A LMAX_ PK E To selec Bmax according o characerisics of ferrie core and margin consideraion of sauraion flux densiy. oupu capacior. n addiion, a high frequency ripple will appear on he E of he oupu capacior due o Boos converer swiching. V + E (π f C ) AC Wih a low E capacior, C i Lpk i Lavg C π f AC P C V i L v gs f he load is resisive, he ripple curren of he oupu capacior is: 3 P V C( M ) ( ) 9π η VNM V Frequency(kHz) Figure 9. Boos nducor Curren in DCM Boundary Conducion Mode 6. Layou Consideraions There are some consideraions when laying ou he PCB of he PFC circui. The power swiching circui loop should be as small as possible. n Boos circui, when MFET urns on, here is a curren flow loop including a recifying bridge, Boos inducor and MFET. When he M- FET urns off, he curren flow loop includes he Boos inducor, diode and oupu capacior. The wo loops should be small o avoid high frequency radiaion noise Figure 0. wiching Frequency in Half Line Cycle upu Capacior The oupu bulk capacior (C ) selecion depends on he DC oupu volage, he allowed overvolage, he oupu volage ripple and ripple curren on he capacior. To achieve a high power facor, he oupu volage feedback conrol loop is slow. As a resul, here is wice he mains frequency volage ripple across he Jan. 0 ev.. 0 Degrees The connecion beween he power and signal should be a single poin connecion. Common connecion of will inroduce disurbances o small signals. Figure. shows he ideal ground connecion diagram. The power ground and signal ground should be separaed. The C ground () should connec direcly o he power ground of he PFC MFET curren sense resisor; he shorer he rack is, he beer he C works. The V CC capacior C and C3 should be placed close o pin 8 o ensure good noise suppression. The drain of he MFET has high dv/d when swiching. The conrol circui including AP66 should be kep away from i. f he MFET sicks o a hea sink, he hea sink should be conneced o he power. 6

7 Applicaion Noe 075 DC BU V N 3 C C3 8 3 MULT AP66 NV 6 GD C 7 5 D 6 s Co ignal Power Figure. Correc Connecion for AP66 in PCB Jan. 0 ev.. 0 7

Table of Contents. 3.0 SMPS Topologies. For Further Research. 3.1 Basic Components. 3.2 Buck (Step Down) 3.3 Boost (Step Up) 3.4 Inverter (Buck/Boost)

Table of Contents. 3.0 SMPS Topologies. For Further Research. 3.1 Basic Components. 3.2 Buck (Step Down) 3.3 Boost (Step Up) 3.4 Inverter (Buck/Boost) Table of Conens 3.0 SMPS Topologies 3.1 Basic Componens 3.2 Buck (Sep Down) 3.3 Boos (Sep Up) 3.4 nverer (Buck/Boos) 3.5 Flyback Converer 3.6 Curren Boosed Boos 3.7 Curren Boosed Buck 3.8 Forward Converer