ISSCC 2007 / SESSION 29 / ANALOG AND POWER MANAGEMENT TECHNIQUES / 29.8

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1 ISSCC 27 / SESSION 29 / ANALOG AND POWER MANAGEMENT TECHNIQUES / A 3GHz Swiching DC-DC Converer Using Clock- Tree Charge-Recycling in 9nm CMOS wih Inegraed Oupu Filer Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, Parick Palmer Universiy of Briish Columbia, Vancouver, Canada Complex designs ofen conain volage islands ha can operae a lower supply volages o reduce power. These circuis require muliple supply volages, however, i is challenging o bring in and disribue several volages on a chip. In his paper, a fully inegraed DC-DC buck converer for regional power regulaion is inroduced. A charge-recycling scheme is used o capure some of he energy sored in he clock-ree load and feed he charge ino he DC-DC converer. Furhermore, using he muli-ghz sysem clock for swiching significanly reduces he size of he oupu filer componens, making heir inegraion feasible. As a proof of concep, he proposed circui is implemened in a 1P7M2T 9nm CMOS process. I operaes a 3GHz o conver an inpu volage of 1.V o an oupu volage of.5 o.7v wih 4 o 1mA load curren. The major drawback of using a high swiching frequency is ha he dynamic swiching loss in he circui is increased. Direcly combining he clock-ree chain wih he converer swiching ransisors and gae driver chain merges he converer swiching losses wih he clock-ree swiching losses. Zero-volage swiching (ZVS) and clock-ree charge-recycling are used o furher reduce power loss and improve conversion efficiency. A delay circui implemened inside he clock-ree chain provides he dead-ime needed o implemen ZVS. To adjus and regulae oupu volage, he duy-cycle of he clock signal is changed by a conrol circui. Therefore, his clock signal is inended for circui blocks ha are insensiive o clock duy-cycle, such as edge-riggered flip-flops. The idea of using an inducor inside a clock disribuion nework was previously used in [1], in which a clock resonance scheme reduces power loss in he clock nework. In comparison, we use charge recycling and ZVS o decrease clock power loss. Figure shows he block diagram of wo implemened sysems: a ypical clock-ree nework and our converer. A chain of cascaded inverers is used as a clock buffer. C clk represens he clock nework capaciance. When he clock is high, C clk is charged hrough M p. In he oher half of he clock cycle, C clk would normally be discharged o ground hrough M n, wasing he sored charge. Insead, M p and M n can be considered as he power ransisors of a swiching buck converer and recycle he clock-ree charge o he oupu filer and consequenly o he load. The combined power and clock circui are shown in Fig and an idealized iming diagram of he inernal signals is shown in Fig In Fig , D, T sw, and T delay represen clock duycycle, swiching period (i.e., clock period), and ZVS dead-ime, respecively. As shown in Fig , here are hree modes of operaion: Mode 1 is inended o drive he load and charge C clk hrough M p. During his ime, inducor curren increases linearly since he volage across i is consan. Mode 2 is inended for charge recycling. Therefore, boh M n and M p. are off. The charge ha is sored in C clk is moved o he oupu circui hrough he inducor. This resuls in a rapid drop of V clk, which is inended. Mode 3 sars when he volage across M n is close o zero. A his ime M n is urned on o provide a low-resisance pah for he inducor curren. As a resul, inducor curren decreases linearly. The ZVS operaion occurs when M n is urned on while is sourcedrain volage is close o zero, hereby reducing power loss. Theoreically, if he falling inducor curren crosses zero, M n could be urned off o charge C clk wih he negaive inducor curren, hence providing ZVS operaion for M p. In pracice, his would increase boh oupu volage ripple and inducor RMS curren. The laer will cause addiional power loss in he inducor resisance. By design, he minimum inducor curren in his circui is se close o zero o reduce he inducor RMS curren, herefore, no ZVS operaion is implemened for M p. Since he inducor curren does no sop a zero, he converer operaes in coninuous conducion mode (CCM). The delay circui for he ZVS operaion of M n is also shown in Fig To conrol he exac on/off iming of M n and M p, he single inverer buffer o hose ransisors is replaced wih wo separae inverers. To implemen he delay ime, as shown in Fig , he gae of M 1 is conneced o V clk insead of he gae of M 2. Therefore, compared o V p, he rising edge of V n is delayed by T delay, a duraion which depends upon how quickly L f drains C clk and how fas M 1 urns on o raise V n. Because of he posiive-feedback configuraion of M 1 and M n, V clk complees he fall o V quie rapidly. To preven M 1 and M 2 from being on a he same ime a he rising edge of V m, he source of M 1 is conneced o V p insead of V dd. The conrol circui of he power converer is also shown in Fig An on-chip PI conroller is used o generae V crl for he PWM circui, which in urn changes he duy-cycle of he clock signal. Deails of he PWM circui are shown in Fig The inpu clock is delayed by wo similar parallel delay lines. One of he lines has a fixed delay, while he delay of he oher is conrolled by V crl. Combining hese wo delayed signals wih a NAND gae resuls in a clock signal wih conrolled duy-cycle [4]. The on-chip filer componens L f and C f are 32pH and 35pF, respecively. For he inducor, wo hick meal layers of he process (M6 and M7) are used in parallel. The capaciors C f and C clk are implemened using he gae capaciance of a ransisor array. In our implemenaion, C clk is esimaed o be 12pF. As he power converer (circui 1) is inegraed wihin he clock nework, an on-chip reference clock nework (circui 2) is also implemened. The effecive efficiency (η eff ) is calculaed using he difference in power needed o operae circuis 1 and 2 as follows: Pou1 η eff = 1 (1) P P in1 Here, P in1 and P in2 are he power dissipaion of circui 1 and 2, respecively, and P ou1 is he oupu power of circui 1. In our implemenaion, he circuis have independen supplies. A 3GHz, P in2 is measured o be 39.9mW. For an oupu volage of.72v a 35.9mA load curren (P ou1 = 25.7mW), P in1 is measured o be 56.2mW and η eff = 158%. The raw efficiency (η) of he inegraed converer and clock nework, wihou accouning for charge recycling, is Pou1 η = 1 = 46%. P in1 For an oupu volage of.52v a 11mA, η eff = 8% and η = 48%. The performance of he proposed converer is summarized in Fig ogeher wih resuls from recenly repored daa in [2] and [3] for comparison. Measured efficiency resuls are shown in Fig The oal area of he inegraed converer is.27mm 2. The chip micrograph is shown in Fig Acknowledgemens: The auhors would like o hank Canadian Microelecronics Corporaion (CMC Microsysems) for providing CAD ools and faciliaing he chip fabricaion. This work is suppored in par by funding from he Naural Sciences and Engineering Research Council of Canada (NSERC). References: [1] S. C. Chan, K. L. Shepard and P. J. Resle, Uniform-Phase Uniform- Ampliude Resonan-Load Global Clock Disribuions, IEEE J. Solid-Sae Circuis, pp , Jan., 25. [2] P. Hazucha e al., A 233MHz 8% 87% Efficien Four-Phase DC-DC Converer Uilizing Air-Core Inducors on Package, IEEE J. Solid-Sae Circuis, pp , Apr., 25. [3] S. Abedinpour, B. Bakkaloglu and S. Kiaei, A Muli-Sage Inerleaved Synchronous Buck Converer wih Inegraed Oupu Filer in a.18µm SiGe Process, ISSCC Dig. Tech. Papers, pp , 26. [4] P. H. Yang and J. S. Wang, Low-Volage Pulsewidh Conrol Loops for SOC Applicaions, IEEE J. Solid-Sae Circuis, pp , Oc., 22. in IEEE Inernaional Solid-Sae Circuis Conference /7/$ IEEE.

2 ISSCC 27 / February 14, 27 / 4:3 PM Wp/Lp=24/.1 Wn/Ln=8/.1 288/.1 M3 VclkPWM Vm Vp Mp 6144/.1 Wp/Lp=6/.1 Wn/Ln=2/.1 Wp/Lp=96/.1 Wn/Ln=32/.1 M4 248/.1 248/.1 96/.1 Vclk Cclk M1 ZVS Delay Circui 96/.1 Vn Mn 512/.1 GND Lf=32pH Cf=35pF Vou Rload M2 32/.1 18/1.5 Transisor dimensions are in µm. Figure : Block diagram of he chip. Figure : Circui diagram of he inegraed clock and power circui. Vp Vn ILf max Vclk Mode Time D T sw T sw D T sw+t delay Figure : Idealized iming diagram of he inernal signals. Figure : Deails of he PWM circui. Year This work 26 [2] 25 [3] Converer ype Technology Swiching frequency, F sw (MHz) Buck 9nm CMOS 3 4-Phase Buck 9nm CMOS Phase Buck.18 m SiGe RFBiCMOS Efficiency (effecive) Efficiency (raw) Inpu volage, V in (V) Oupu volage range, V ou (V) 1..5 o o o o 2 Nom Oupu volage ripple (%-pp) Oupu curren, I ou (ma) Effecive efficiency eff (%) Filer inducor, L f (nh) <5* V ou =.7V) 4 o 1* 158 V ou =.72V) 98 V ou =.62V) 8 V ou =.52V).32 3 o o ** Percen (%) Filer capacior, C f (pf) Off/on chip passive filer componens Converer area (mm 2 ) 35 On-chip.27 (including L f and C f ) * Design specificaion ** This design uses four inducors, 6.8nH each. Off-chip, in-package inducors.14 (excludes L) On-chip Figure : Summary of he measured performance of he converer and comparison wih [2] and [3] I ou (ma) Figure : Measured conversion efficiency, raw and effecive. Coninued on Page DIGEST OF TECHNICAL PAPERS 533

3 ISSCC 27 PAPER CONTINUATIONS Figure : Chip micrograph IEEE Inernaional Solid-Sae Circuis Conference /7/$ IEEE.

4 ISSCC 27 Figure : Block diagram of he chip IEEE Inernaional Solid-Sae Circuis Conference /7/$ IEEE.

5 ISSCC 27 Wp/Lp=24/.1 Wn/Ln=8/.1 288/.1 M3 VclkPWM Vm Vp Mp 6144/.1 Wp/Lp=6/.1 Wn/Ln=2/.1 Wp/Lp=96/.1 Wn/Ln=32/.1 M4 248/.1 248/.1 96/.1 Vclk Cclk M1 ZVS Delay Circui 96/.1 Vn 512/.1 Mn GND Lf=32pH Cf=35pF Vou Rload M2 32/.1 Transisor dimensions are in μm. 18/1.5 Figure : Circui diagram of he inegraed clock and power circui IEEE Inernaional Solid-Sae Circuis Conference /7/$ IEEE.

6 ISSCC 27 Vp Vn I Lf max Vclk Mode Time D T sw T sw D T sw +T delay Figure : Idealized iming diagram of he inernal signals IEEE Inernaional Solid-Sae Circuis Conference /7/$ IEEE.

7 ISSCC 27 Figure : Deails of he PWM circui IEEE Inernaional Solid-Sae Circuis Conference /7/$ IEEE.

8 ISSCC 27 This work [2] [3] Year Converer ype Buck 4-Phase Buck 2-Phase Buck Technology 9nm CMOS 9nm CMOS.18 m SiGe RFBiCMOS Swiching frequency, F sw (MHz) Inpu volage, V in (V) o Oupu volage range, V ou (V).5 o.7.9 o o 2 Nom. 1.8 Oupu volage ripple (%-pp) <5* V ou =.7V) Oupu curren, I ou (ma) 4 o 1* 3 o 4 2 Effecive efficiency eff (%) 158 V ou =.72V) 98 V ou =.62V) 8 V ou =.52V) 83.2 o Filer inducor, L f (nh) ** 11 Filer capacior, C f (pf) Off/on chip passive filer componens On-chip Off-chip, in-package inducors On-chip Converer area (mm 2 ).27 (including L f and C f ).14 (excludes L) 27 * Design specificaion ** This design uses four inducors, 6.8nH each. Figure : Summary of he measured performance of he converer and comparison wih [2] and [3] IEEE Inernaional Solid-Sae Circuis Conference /7/$ IEEE.

9 ISSCC Efficiency (effecive) Efficiency (raw) 12. Percen (%) I ou (ma) Figure : Measured conversion efficiency, raw and effecive IEEE Inernaional Solid-Sae Circuis Conference /7/$ IEEE.

10 ISSCC 27 Figure : Chip micrograph IEEE Inernaional Solid-Sae Circuis Conference /7/$ IEEE.

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