A New, Two-Switch, Isolated, Three-Phase AC-DC Converter

Transcription

1 A ew, Two-Swich, Isolaed, Three-Phase AC-DC Converer Yungaek Jang, Milan M. Jovanovi, Misha Kumar, and Kuris High Power Elecronics Laboraory Dela Producs Corporaion Research Triangle Park, C, USA Yihua Chang, Yiwei Lin, and Chun-Liang Liu Dela Elecronics, Inc. Chungli Indusrial Zone Taoyuan Couny, Taiwan, R.O.C. Absrac In his paper, a new, hree-phase, single-sage, isolaed ac-dc converer (recifier) ha employs only wo swiches and achieves less han 5% oal harmonic disorion (THD) of he hree-phase inpu currens and provides a ighly regulaed, isolaed, oupu volage is inroduced. The recifier feaures zerovolage-swiching (ZVS) of boh swiches over he enire inpu and load range wihou any addiional sof-swiching circuiry. The recifier is derived by combining he hree-phase, frequencyconrolled, power-facor-correcion (PFC), disconinuouscurren-mode (DCM) boos recifier wih he convenional LLC resonan half-bridge converer. The evaluaion was performed on a 1-kW prooype operaing wih a hree-phase line-volage range from 18 VL-L o 64 VL-L and delivering a ighly-regulaed, isolaed, oupu volage of 54 V. Keywords hree phase; power facor correcion; single sage; ac-dc recifier; zero volage swiching; LLC resonan converer I. ITRODUCTIO Generally, modern off-line power supplies consis of a fron-end power-facor-correcion (PFC) recifier followed by an isolaed dc-dc converer. In single-phase implemenaions, he PFC fron-end is ypically implemened eiher as a convenional boos converer, an inerleaved boos converer, or a bridgeless boos converer [1], []. In hree-phase applicaions, he six-swich boos converer and Vienna recifier are he mos commonly used fron-end opologies [3], [4]. In high-performance applicaions, he Vienna recifier is he preferred opology because i offers he highes efficiency wih oday s commercially available Si semiconducor devices. However, he lower-componen-coun six-swich boos converer implemened wih wide-band-gap SiC devices can also provide equally good efficiency and power densiy performance [4]. The choice of he isolaed dc-dc oupu-sage opology is primarily dependen on he power level. A higher power levels (>4-5 W), bridge-ype opologies are ypically used. In oday s ac-dc power supplies ha need o mee exremely challenging efficiency requiremens across he enire load range, he zero-volage-swiching (ZVS) full-bridge (FB) converer wih phase-shif conrol and LLC series-resonan converer are exclusively used as he dc-dc oupu sage. Alhough wo-sage off-line power conversion has demonsraed excellen performance, various hree-phase, single-sage implemenaions have been inroduced o reduce he cos and/or increase he power densiy, [5]-[11]. Generally, hey eiher inegrae a hree-phase boos recifier wih an isolaed dcdc sage [5]-[9], or combine hree single-phase, single-sage isolaed converers ino a hree-phase isolaed converer [1], [11]. A high PF and low inpu curren THD in he implemenaions in [5]-[11] were obained by operaing he inegraed boos sage in he disconinuous-conducion mode (DCM) where he phase currens naurally follow he respecive phase volages, i.e., wihou any acive curren conrol. In singlesage ac-dc opologies wih wide bandwidh oupu-volage regulaion, he major design challenge is he rade-off beween he inpu-curren THD and he maximum volage sress of he unregulaed bulk capacior volage. Generally, he maximum bulk capacior volage should be limied o a value ha allows for he minimum-volage-raed swiches o be used. The singlesage recifier inroduced in [9] is an inegraed opology of he hree-phase, frequency-conrolled, PFC, DCM boos recifier [1] and a full-bridge converer which regulaes he oupu volage as well as he bulk capacior volage using wo conrol loops. By acively regulaing he bulk capacior volage wih phase-shif pulse-widh modulaion (PWM) of he full-bridge converer and he oupu volage wih frequency conrol, he maximum volage sress of he recifier is well limied. In his paper, a new, hree-phase, single-sage, isolaed acdc converer ha is derived by combining he hree-phase, frequency-conrolled, PFC, DCM boos recifier [1] wih he V A Frequency Conrolled PFC DCM Boos D 1 D D 3 Recifier L 1 C 1 C C 3 V B L + L R i V TR B C L L 3 C S D O1 D R O D 4 D 5 D 6 Fig. 1. Proposed wo-swich isolaed hree-phase recifier. S 1 LLC Resonan Half-Bridge Converer C O C R1 + + R /18/$ IEEE 6

2 convenional LLC resonan half-bridge converer is inroduced. The converer employs only wo swiches and achieves less han 5% curren THD of he hree-phase inpu currens and provides a ighly regulaed, isolaed, oupu volage. The recifier feaures ZVS of boh swiches over he enire inpu and load range wihou any addiional sof-swiching circuiry. The inroduced recifier requires single feedback loop wih frequency conrol. Since he hree-phase, PFC, DCM boos recifier operaes wih frequency conrol, he inegraion wih a frequency conrolled LLC resonan converer is simpler han he inegraion wih a full-bridge phase-shif PWM converer which requires wo feedback loops for frequency conrol and PWM [9]. The evaluaion was performed on a 1-kW prooype operaing wih a hree-phase line-volage range from 18 V L-L o 64 V L-L and delivering a ighly regulaed isolaed oupu volage of 54 V. II. TWO-SWITCH ISOLATED THREE-PHASE RECTIFIER As shown in Fig. 1, he proposed recifier is derived by combining he hree-phase, frequency-conrolled, PFC, DCM boos recifier wih he convenional LLC resonan half-bridge converer. The frequency-conrolled, PFC, DCM, boos recifier achieves very low curren THD of hree-phase line inpu currens wih only wo swiches, as described in [1], while LLC resonan converers have been widely used because of heir superior efficiency [13]-[]. In his circui, swiches S 1 and S simulaneously serve as he swiches of he boos fron end and half-bridge swiches of he LLC resonan converer. A he inpu side, hree boos inducors L 1, L, and L 3 are conneced o he hree-phase power-source erminals along wih hree differenial-mode filer capaciors C 1, C, and C 3 conneced in Y ( sar ) configuraion. Since for a balanced hree-phase power source, he poenial of he common node of he filer capaciors, labelled in Fig. 1, has he same poenial as power source neural ha is no physically available or conneced in hree-wire power sysems, node represens a virual neural. Virual neural is conneced o he mid-poin beween wo swiches S 1 and S. As a resul of connecing virual neural direcly o he mid-poin beween swiches S 1 and S, decoupling of he hree inpu currens is achieved. In such a decoupled circui, he curren in each of he hree inducors is dependen only on he corresponding phase volage, which reduces he THD and increases he PF [1]. In addiion, he mid-poin of he swiches do no experience abrup changes wih high dv/d, which makes i possible for he recifier o operae wih a relaively low common-mode EMI noise. In Fig. 1, he primary side of he LLC resonan converer includes isolaion ransformer TR, resonan inducor L R, and resonan capaciors C R1 and C R. The secondary-side is implemened wih he cener-apped secondary winding, oupu diodes D O1 and D O, and oupu filer capacior C O. However, in some applicaions i may be more appropriae o implemen secondary side wih a full-bridge recifier or employ synchronous recifiers (SRs) insead of he diode oupu recifiers. Bulk capacior C B ha sores energy for hold-up ime is conneced on he dc-side of inpu bridge recifier D 1-D 6. V C Fig.. V B i L D1 D5 D6 L 1 L D 1 D 5 L 3 D 6 D1 D D6 i S1 S 1 i S S V B D D4 D6 (a) (b) Proposed hree-phase wo-swich ZVS PFC DCM boos recifier: (a) simplified circui diagram showing reference direcions of currens; (b) inpu-volage 6 -segmens during which none of phase volages changes sign. Conducing diodes in each segmen are also indicaed. Since swiches S 1 and S operae as he PFC boos swiches as well as he swiches of he LLC resonan circui, he energy required o achieve ZVS of swiches S 1 and S is sored boh in boos inducors L 1-L 3 and resonan inducor L R. Because he inducance of he boos inducors is relaively large, hey sore enough energy for complee ZVS of swiches S 1 and S even a very low power levels. III. AALYSIS OF OPERATIO To simplify he analysis of operaion, i is assumed ha ripple volages of he inpu and oupu filer capaciors as well as he bulk capacior shown in Fig. 1 are negligible so ha heir volages can be represened by consan-volage source, V B, V C,, and as shown in Fig.. Also, i is assumed ha in he on sae, semiconducors exhibi zero resisance, i.e., hey are shor circuis. However, he oupu capaciances of he swiches are no negleced in his analysis. By recognizing ha recifiers D 1, D, and D 3 conduc only when heir corresponding phase volage is posiive and recifiers D 4, D 5, and D 6 conduc only when heir corresponding phase volage is negaive, he simplified circui diagram of he recifier along wih he reference direcions of currens and volages is shown in Fig. (a). I should be noed ha he inpu model in Fig. (a) is only valid in he 6 segmen of he line cycle where V A >, V B<, and V C <, as shown in Fig. (b). However, he same model is applicable o any oher 6 segmen during which he phase volages do no change polariy. To furher faciliae he explanaion of he operaion, Fig. 3 shows opological sages of he circui in Fig. (a) during a swiching cycle, whereas Fig. 4 shows he power-sage key TR D O1 D D3 D4 1 D O C R1 L R V CB V C o 6 o 1 o 18 o 4 o 3 o 36 o D3 D4 D5 D1 D3 D5 C R ω 61

3 C OSS1 C OSS V C V B V C V B (a) [T - T 1] (b) [T 1 - T ] V C V B V C V B i L i L (c) [T - T 3] (d) [T 3 - T 4] C OSS1 C OSS V C V B V C V B i L i L (e) [T 4 - T 5] (f) [T 5 - T 6] V C V B V C V B i L i L (g) [T 6 - T 7] (h) [T 7 - T 8] V C V B V C V B i L (i) [T 8 - T 9] (j) [T 9 - T 1] Fig. 3. Topological sages of proposed recifier when V A >, V B < V C <, and LLC converer operaes above is resonan frequency f, i.e., f S > f. waveforms when LLC converer operaes above is resonan frequency f, i.e., f S > f. As can be seen from he gae-drive iming diagrams for swiches S 1 and S in Fig. 4, he swiches operae in a complemenary fashion wih approximaely 5% duy cycle and wih a shor dead ime beween he urn-off of swich S 1 and he urn-on of swich S, and vice versa. Because of his gaing sraegy, boh swiches can achieve ZVS. However, o simulaneously mainain ZVS and regulae he oupu volage wih respec o inpu volage and/or load curren variaions, he proposed recifier mus employ a variable swiching frequency conrol. The minimum frequency is se a full load and minimum inpu volage, whereas he maximum 6

4 S T S 1 S S 1 O S O S 1 O S O i L V S1 V S i S1 i S - L 1 L 1 -V C L 3 1 n = -V B -V B L i L L ZVS -V C L 3 i +i +i +i L1 L L3 LR n ZVS - i - i - i - i L1 L L3 LR oupu capaciance of swich S is fully discharged and he aniparallel body diode of swich S sars conducing a =T, as shown in Fig. 3(c) and Fig. 4. Because he body diode of swich S is forward biased, inducor currens i L and begin o increase linearly. During his period, primary volage is equal o n, where n= 1/ is he urns raio of he ransformer, and he sum of and reses resonan curren quickly o zero. A =T 3, swich S is urned on wih ZVS and inducor currens, i L, and are commuaed from he aniparallel diode of swich S o he channel of swich S. Moreover, resonan curren changes direcion and he secondary-side curren is commuaed from oupu diode D O1 o oupu diode D O, as shown in Fig. 3(d). This period ends when inducor curren decreases o zero a =T 4. To mainain DCM operaion, he ime period beween =T 3 and =T 4 mus be less han one-half of swiching period T S which means ha he rising slope of inducor curren should be smaller han is falling slope. As illusraed in Fig. 4, he rising and falling slopes of are /L 1 and (-)/L 1, respecively. As a resul, minimum volage -MI across bulk capacior C B o achieve DCM operaion is VCB MI = VA ( PK ) = VLL( RMS ), () 3 where -PK is he peak line-o-neural volage. -n T T 1 T T 3 T 4 T 5 T 6 T 7 T 8 T 9 Fig. 4. Key waveforms of proposed single-sage recifier when >, V B < V C <, and LLC converer operaes above is resonan frequency f, i.e., f S > f. frequency is se a ligh load and maximum inpu volage. The recifier operaes in conrolled burs mode a very ligh loads, including no load, o avoid excessive swiching losses a unreasonably high swiching frequencies. As shown in Figs. 3(a) and 4, before swich S 1 is urned off a =T 1, inducor curren flows hrough swich S 1. The slope of inducor curren is equal o /L 1 and he peak of he inducor curren a =T 1 is approximaely VA TS I L1( PK) =, (1) L1 where is line-o-neural volage. During he period beween T and T 1, oupu diode D O1 conducs oupu curren, as shown in Fig. 3(a). During his inerval, primary resonan curren resonaes wih resonan inducor L R and resonan capaciors C R1 and C R. Since swiching frequency f S is higher han resonan frequency f, resonan curren is posiive a =T 1, as shown in Fig. 4. A =T 1, when swich S 1 is urned off, inducor curren sars charging he oupu capaciance of swich S 1, as shown in Fig. 3(b). Because he sum of he volages across swich S 1 and swich S is clamped o volage, he oupu capaciance of swich S discharges a he same rae as he charging rae of he oupu capaciance of swich S 1. This period ends when he T1 I should also be noed ha because during he T -T 4 inerval inducor currens i L and and resonan curren flow in he opposie direcion from inducor curren, he average curren hrough swich S is reduced so ha he swich in he proposed recifier exhibis reduced power losses. During he period beween =T and =T 4, inducor currens i L and coninue o flow hrough swich S as shown in Fig. 4. The slopes of inducor currens i L and during his period are equal o V B/L and V C/L 3, respecively, and heir peaks a he momen when swich S urns off are approximaely VB TS IL (PK) = and (3) L VC TS IL 3(PK) =. (4) L3 As i can be seen in Eqs. (1), (3), and (4), he peak of each inducor curren is proporional o is corresponding phase volage, which resuls in a low THD of he phase currens [1]. Afer swich S is urned off a =T 5, resonan curren and inducor currens i L and sar o simulaneously charge he oupu capaciance of swich S and discharge he oupu capaciance of swich S 1, as shown in Fig. 3(f). This period ends a =T 6 when he oupu capaciance of swich S 1 is fully discharged and is ani-parallel diode sars conducing, as shown in Fig. 3(g) and Fig. 4. Afer =T 6, swich S 1 can be urned on wih ZVS. In Fig. 4, swich S 1 is urned on a =T 7. As shown in Fig. 3(h), once swich S 1 is on, increasing inducor curren and resonan curren flow in he opposie direcion from inducor currens i L and hrough swich S 1 so ha swich S 1 carries only he difference of sum of curren and resonan curren and sum of currens i L and. This period ends when inducor curren decreases o zero a =T 8. 63

5 During period T 8-T 9, decreasing inducor curren i L coninues o flow hrough swich S 1, as shown in Fig. 3(i). Afer inducor curren i L reaches zero a =T 9, as shown in Fig. 3(j), a new swiching cycle begins. Since swiches S 1 and S operae as he swiches of he frequency-conrolled, PFC, DCM, boos recifier as well as he swiches of he half-bridge LLC resonan converer, he inpu power of he boos recifier and oupu power of he half-bridge LLC resonan converer canno be independenly conrolled. Any difference beween he inpu power and he oupu power is handled by bulk capacior C B. Since he bulk capacior volage auomaically reaches seady sae a he volage level where he inpu power and oupu power are balanced, capacior volage varies wih he load (oupu power) and inpu volage. As a resul, he major design challenge of he proposed recifier is o find opimum values of boos inducors L 1-L 3, resonan inducor L R, magneizing inducance L M of ransformer TR, and resonan capacior C R so ha capacior volage says in he desirable range. This range is deermined by minimum volage -MI ha is required o achieve boos recifier operaion and maximum volage -MAX o safely employ swiches wih desirable (ypically, lowes) volage raing. The opimum componen values are found by using relaionships beween swiching frequency f S, bulk capacior volage, line-o-neural inpu volage V L-, and inpu power P I for boh opologies and following he design procedure oulined in Sec. IV. For he frequencyconrolled, PFC, DCM, boos recifier, his relaionship is given by, [1], 3 VCB.48 fs, (5) 8 L M PI M.9 where volage conversion raio VCB and boos M = VL, RMS inducor L = L 1 = L = L 3, whereas for he LLC resonan halfbridge converer, i is given by, [13]-[15], V CB nv O 1 1+ h h 1 + f S ( ) ( nvo ) f Z P I 8 π f f S f f S, (6) where h =L R/L M, f is resonan frequency, and Z = is he characerisic impedance of he resonan ank. Finally, i should be noed ha in he proposed recifier, he inpu curren is no sensed. The inpu curren shaping is obained naurally by mainaining volage relaively consan during seady sae, i.e., by mainaining swiching period T S virually consan during a line cycle. Wih a consan swiching period T S and 5% duy cycle, he peaks of he inducor currens are proporional o he corresponding phase volages. For such a riangular curren waveform, he linefrequency average-curren disorion is predominanly conained in he 3 rd harmonic. Since he 3 rd harmonic (riplen harmonic) currens canno flow in a hree-wire sysem, hey circulae hrough capaciors C 1, C, and C 3, whereas he remaining harmonics conribues less han 1% of inpu-curren THD, as described in [1]. IV. DESIG COSIDERATIOS Design guidelines for and performance evaluaion of he proposed recifier are presened for a elecom recifier wih he following key specificaions: Three-phase inpu volage VI: VL-L, RMS, 8 VL-L, RMS (nominal) Oupu volage VO: 54 V Maximum oupu power PO-MAX: 1 kw Peak efficiency η: >95% A. Design of Boos Inducor The value of boos inducor L should be seleced so ha he maximum volage of doesn exceed allowable volage sress and ha he minimum volage of is high enough o perform boos recifier operaion. From Eq. () and he given inpu volage specificaion, he minimum volage of C B is VCB MI = 18VL L( RMS) = 94V. (7) 3 The minimum volage of -MI is seleced o be 3 V for he boos inducance calculaion. To achieve desired efficiency and power densiy, he minimum frequency f S-MI a full load P O-MAX = 1 kw and minimum inpu volage V I-MI = 18 V L-L, RMS is se o 45 khz. As a resul, by using Eq. (5), he value of boos inducor L becomes 3 V L 8 f S MI CBMI η M P OMAX.48 M = 15μH. (8) To obain he desired inducance of boos inducors L 1, L, and L 3 of approximaely 15 μh, each inducor was buil using a pair of ferrie cores (PQ-3/3, 3C96) wih 46 urns of Liz wire (1 srands /AWG #38). The Liz wire was used o reduce he fringing-effec-induced winding loss near he gap of he inducor core. B. Selecion of Resonan Tank Componens To maximize he efficiency a nominal line, he LLC resonan converer is designed o operae a resonan frequency f = = 65 khz when i delivers full power from nominal inpu volage V I-OM = 8 V L-L, RMS. By using Eq. (5), he bulk-capacior volage in his operaing poin is calculaed o be -OM = 316 V. Since is he inpu of he LLC converer, urns raio n of he ransformer can be deermined from he dcvolage gain definiion M LLC = (n)/(/). Since a he resonan frequency M LLC = 1, urns raio is n = -OM/() = 316/18 3. Because zero-volage swiching of he proposed recifier is mosly achieved by he energy sored in he boos inducors, magneizing inducance L M of he ransformer could be large o 64

6 minimize circulaing magneizing curren. As a resul, differen from he convenional LLC design, he LLC converer in he proposed recifier can be designed wih h=l M/L R>>1. To deermine he resonan ank componens, i is necessary o deermine he characerisic impedance Z = of he resonan ank. Generally, Z should be seleced so ha bulkcapacior volage, which deermines he volage raing of primary swiches, is limied below he desired maximum volage in he enire inpu volage and load range. For swiching devices wih 6-V raing, o obain % margin, -MAX should no exceed 48 V. In his design, conservaive -MAX = 4 V is seleced. Maximum bulk-capacior volage -MAX occurs a he maximum inpu volage V I-MAX and minimum power P O-MI which is deermined by maximum swiching frequency f S-MAX. For a given f, -MAX, V I-MAX, and f S-MAX, characerisic impedance Z can be calculaed from Eq. (6), which for h >> 1 can be simplified o ( nv ) 8 O π V CBMAX Z 1. (9) P OMI f fs MAX nvo η fs MAX f By limiing maximum frequency f S-MAX o 36 khz o avoid high swiching losses, minimum power P O-MI ha can be regulaed a high line V I-MAX wihou enering burs mode is calculaed from Eq. (5) o be P O-MI 3 W. Therefore, he required characerisic impedance Z is calculaed from Eq. (9) as 8 ( 3 54) π ( ).95 4 Z 1 9. Ω Wih characerisic impedance Z and resonan frequency f known, he values of resonan inducor and resonan capacior are calculaed as L R = Z /(f ) μh and C R = 1/(f Z ) = 7 nf. Accouning for 1- μh leakage inducance of ransformer TR ha is par of he resonan ank, he desired inducance of [V] L B = 15 μh, L R = μh, C R = 38 nf 18 V L-L Oupu Power [W] Fig. 5. Calculaed bulk capacior volage of 1-kW proposed recifier a minimum, maximum, and nominal volages as funcions of oupu power. V I = 65 V L-L 8 V L-L resonan inducor L R of approximaely μh is obained by using a pair of ferrie cores (PQ-5/3, 3C96) wih 6 urns of Liz wire (1 srands of AWG #38). Two parallel conneced film capaciors (MKP, 8 nf, 16 VDC) from Vishay were used o achieve 164 nf for each of resonan capaciors C R1 and C R. Since resonan capaciors C R1 and C R of he half-bridge resonan ank circui are effecively in parallel, he oal resonan capaciance is 38 nf. Figure 5 shows calculaed bulk capacior volage of he proposed recifier a minimum, maximum, and nominal volage as funcions of oupu power wih seleced componen values. Because an explici soluion for bulk capacior volage canno be derived from Eqs. (5) and (6), numerical ieraion was employed o calculae he bulk capacior volages. The calculaed peak volage sress is approximaely 41 V, whereas he minimum volage is approximaely 315 V. C. Transformer Consrucion The ransformer was buil using ferrie cores and Liz-wire windings wih he following specificaions: Core: A pair of PQ3535-3C96 ferrie cores. Primary winding: 1 = 15 urns, Liz wire (1 srands of AWG #38). Secondary windings: = 5 urns, Liz wire ( srands of AWG #38), each. Air gap:. mm. The measured magneizing and leakage inducances are 96 μh and 1. μh, respecively. The maximum flux densiy in seady sae operaion is approximaely.5 T, which gives pleny of margin from he sauraion limi of he ferrie core. D. Semiconducor Device Selecion Because he volage sress of primary swiches S1 and S is approximaely equal o bulk capacior volage VCB, i.e., i is below 45 V, i is necessary o use swiches ha are raed a leas 6-V o mainain he desirable design margin of %. In he prooype circui, a IPW65R41CFD Si MOSFET (VDS = 65 V, RDS =.41 Ω, COSS=35 pf, Qrr=1.8 μc, VF=.9 44 A) from Infineon were employed. Since oupu diodes DO1 and DO mus block wice of he oupu volage wih pleny of margin, a VB3C Schoky diode (VRRM = V, IFAV = 3 A, VF =.6 V) from Vishay was used for each diode. E. Oher Passive Componens A film capacior (. μf, 45 VDC, 1 A a 4 khz) was used for each of inpu filer capaciors C 1, C, and C 3 which carry he ac componen of he boos-inducor currens as well as he riplen harmonic componen. Since he magniude of he riplen harmonic componen is much smaller han ha of he ac componen of he boos-inducor currens [1], he raing of he inpu capaciors is essenially deermined by he peak boos inducor curren ha occurs a full load and low line. Two serially conneced elecrolyic capaciors (56 μf, 3 VDC) were used for bulk capacior C B. Six parallel conneced elecrolyic capaciors (68 μf, 63 VDC) were used for oupu capacior C O. 65

7 F. Conrol Implemenaion The conrol of he prooype recifier was implemened wih TMS3F87 DSP from TI. Since he recifier naurally provides racking of he average inducor curren wih he corresponding phase volage, he conrol consiss only of a wide bandwidh feedback loop ha regulaes he oupu volage. Since a small-signal model for LLC converer is no available, he compensaor for he loop was designed wih he help of SIMPLIS TM simulaions. To obain desired loop bandwidh of 1.6 khz wih approximaely 5 phase margin a full load and nominal line, a PI compensaor wih K P=5.1 and K I=965 was used. Efficiency [%] V I=18 VL-L V I =8 VL-L V I =65 VL-L = 54 VDC V. EXPERIMETAL RESULTS The performance of he proposed recifier was evaluaed on he prooype circui design according o he design procedure and key specificaions given in Sec. IV. Figure 6 shows he schemaics and componen informaion of he prooype. As shown in Fig. 7, he measured efficiency of he prooype a nominal line volage V I=8 V L-L, RMS is above 95% from 9% of full load down o 5% of full load. I should be noed ha he efficiency can be furher increased by using synchronous recifiers insead of oupu Schoky diodes D O1 and D O. Figure 8 shows he measured inpu curren waveforms of he experimenal circui a nominal line V I-OM=8 V L-L, RMS and full power P O-MAX = 1 kw. The measured THDs of he inpu currens are below 5%. Figure 9 shows he measured gae volage waveform of swich S 1, he curren waveforms of boos inducor L 1, swich S 1, and resonan inducor L R for he same operaing condiions. The measured swiching waveforms in Fig. 9 are in good agreemen wih he ideal waveforms shown in Fig. 4. ZVS operaion of swich S 1 can be observed from Fig. 9 since i shows ha drain curren i S1 flows in reverse direcion a he momen when he gae signal of S 1 is urned on, which indicaes ha he body diode of swich S 1 is conducing and is drain-o-source volage is zero. The measured hold-up ime a L1, L, L3 PQ3/3-3C96 Liz.1mmx1 46T, 15uH V A L 1 V B V C C1, C, C3.uF /45 V L i L L 3 C 1 C C 3 D1-D6 STTH3R6 D 1 D D 3 D 4 D 5 D 6 TR (15T:5T:5T) PQ35/35-3C96 Pri.=Liz.1mmx1 Sec.=Liz.1mmx Lm=96uH S1 - S4 IPW65R41CFD LR PQ5/3-3C96 Liz.1mmx1 6T, uh CR1, CR 164nF/1.6kV 56uF /3V C B1 C B 56uF /3V Do1, Do VB3C, V + C O 6x R 68uF/63 V Fig. 6. Schemaics and componen informaion of experimenal prooype circui. S 1 S TR D O1 D O L R C R1 C R Oupu Power [W] Fig. 7. Measured efficiencies of experimenal prooype a minimum, maximum, and nominal volage as funcions of oupu power. full load P O-MAX=1 kw and nominal inpu volage V I-OM=8 V L-L, RMS is approximaely ms and, if necessary, can be exended by increasing capaciance of C B. Figure 1 shows he measured waveforms of bulk capacior volage, oupu volage, oupu curren, and inpu curren i A of phase A during load sep changes from 5 W o 1 kw and back o 5 W. Because of he fas oupuvolage feedback conrol, he over shoo and under shoo of oupu volage during he load sep changes are mv and 19 mv, respecively, which are less han specified 5-mV (.5%) limi. Fig. 8. Measured inpu curren waveforms when recifier operaes from hreephase line-o-line RMS inpu volage 8 V L-L and delivers 1 kw. Time scale is 4 ms/div. Fig. 9. Measured waveforms of gae driving volages V G-S1 and drain curren i S1 of swich S 1 as well as boos inducor curren and resonan inducor curren when recifier operaes from hree-phase line-oline RMS inpu volage 8 V L-L and delivers 1 kw. Time scale 4 μs/div. 66

8 (a) (b) Fig. 1. Measured waveforms of bulk capacior volage, oupu volage, oupu curren i O, and phase-a inpu curren i A during load sep change: (a) from 5 W o 1 kw; (b) from 1 kw o 5 W. The recifier delivers 54 V oupu from hree-phase line-o-line RMS inpu volage 8 V L-L. Time scale 1 ms/div. Also, from Figs. 1(a) and (b), i can be seen ha he seady-sae bulk-capacior volage (he volage before load ransiens) has a very low ripple and is pracically consan. Because inpu volage and regulaed oupu volage of he LLC converer are consan, he on-ime of he swiches is also consan during a line cycle. As a resul, he inpu currens in he proposed ac-dc converer exhibi very low THDs. Finally, he measured maximum bulk-capacior volage -MAX was approximaely 43 V, which is well wihin 1% of he 4-V design arge. VI. COCLUSIOS A new, hree-phase, single-sage, ZVS, ac-dc converer ha employs only wo swiches and achieves less han 5% curren THD of he hree-phase inpu has been inroduced. The evaluaion was performed on a 1-kW prooype operaing wih a hree-phase line-volage range from 18 V L-L o 64 V L-L and delivering a ighly regulaed, isolaed oupu volage of 54 V. The measured peak efficiency is greaer han 95.% and he measured maximum bulk-capacior volage is approximaely 43 V. REFERECES [1] M.M. Jovanovi and Y. Jang, Sae-of-he-ar, single-phase, acive power-facor-correcion echniques for high-power applicaions an overview, IEEE Transacions on Indusrial Elecronics, vol. 5, no. 3, pp , Jun. 5. [] L. Huber, Y. Jang, and M.M. Jovanovi, Performance evaluaion of bridgeless pfc boos recifiers, IEEE Transacions on Power Elecronics, vol. 3, no. 3, pp , May 8. [3] J. W. Kolar and T. Friedli, The essence of hree-phase pfc recifier sysems, IEEE Transacions on Power Elecronics, vol. 8, no. 1, pp , Jan. 13. [4] T. Friedli, M. Harmann, and J. W. Kolar, The essence of hree-phase pfc recifier sysems-par II, IEEE Transacions on Power Elecronics, vol. 9, no., pp , Feb. 14. [5] J.G. Conreras and I. Barbi, A hree-phase high power facor pwm zvs power supply wih a single power sage, IEEE Power Elecronics Specialiss Conf. (PESC) Proc., pp , [6] F.S. Hamdad and A.K.S. Bha, A novel sof-swiching high-frequency ransformer isolaed hree-phase ac-o-dc converer wih low harmonic disorion, IEEE Transacions on Power Elecronics, vol. 19, no. 1, pp , Jan. 4. [7]. Huang, D. Zhang, T. Song, M. Fan, and Y. Liu, A 1 kw single-sage converer for welding wih inheren power facor correcion, IEEE Applied Power Elecronics Conf. (APEC) Proc., pp , 5. [8] M. arimani and G. Moschopoulos, " A new hree-phase single-sage recifier wih improved inpu and oupu characerisics," in IEEE Applied Power Elecronics Conf. Rec. 11, pp [9] Y. Jang and M. M. Jovanovi, The single-sage Taipei recifier design consideraion and performance evaluaion, IEEE Transacions on Power Elecronics, vol. 9, no. 11, pp , ov. 14. [1] M.J. Kocher and R. L. Seigerwald, An ac-o-dc converer wih high qualiy inpu waveform, IEEE Transacions on Indusry Applicaions, vol. 19, no. 4, pp , Jul./Aug [11] R. Ayyanar,. Mohan, and J. Sun, Single-sage hree-phase powerfacor-correcion circui using hree isolaed single-phase sepic converers operaing in ccm, IEEE Power Elecronics Specialiss Conf. (PESC) Proc., pp ,. [1] Y. Jang and M. M. Jovanovi, The Taipei recifier a new hree-phase wo-swich zvs pfc dcm boos recifier, IEEE Transacions on Power Elecronics, vol. 8, no., pp , Feb. 13. [13] B. Yang, R. Chen, and F.C. Lee, "Inegraed magneics for LLC Resonan Converer," in IEEE Applied Power Elecronics Conf. Rec., pp [14] B. Lu, W. Liu, Y. Liang, F.C. Lee, and J.D. Van Wyk, "Opimal design mehodology for LLC resonan converer," in IEEE Applied Power Elecronics Conf. Rec. 6, pp [15] G. Ivensky, S. Bronshein, and A. Abramoviz, Approximae analysis of resonan LLC DC-DC converer, IEEE Transacions on Power Elecronics, vol. 6, no. 11, pp , ov. 11. [16] X. Fang, H. Hu, Z. J. Shen, and I. Baarseh, Operaion mode analysis and peak gain approximaion of he LLC resonan converer, IEEE Transacions on Power Elecronics, vol. 7, no. 4, pp , Apr. 1. [17] R. Beiranvand, B. Rashidian, M.R. Zolghadri, S.M.H. Alavi, A design procedure for opimizing he LLC resonan converer as a wide oupu range volage source, IEEE Transacions on Power Elecronics, vol. 7, no. 8, pp , Aug. 1. [18] F. Musavi, M. Cracium, D.S. Guaam, W. Eberle, and W.G. Dunford, An LLC resonan DC-DC converer for wide oupu volage range baery charging applicaions, IEEE Transacions on Power Elecronics, vol. 8, no. 1, pp , Dec. 13. [19] J. Deng, S. Li, S. Hu, C.C. Mi, and R. Ma, Design mehodology of LLC resonan converers for elecric vehicle baery chargers, IEEE Transacions on Vehicular Technology, vol. 63, no. 4, pp , May 14. [] Z. Fang, T. Cai, S Duan, and C. Chen, Opimal design mehodology for LLC resonan converer in baery charging applicaions based on imeweighed average efficiency, IEEE Transacions on Power Elecronics, vol. 3, no. 1, pp , Oc