VOLTAGE DOUBLER BOOST RECTIFIER BASED ON THREE-STATE SWITCHING CELL FOR UPS APPLICATIONS

Transcription

1 VOLTAGE DOUBLER BOOST RECTIFIER BASED ON THREE-STATE SWITCHING CELL FOR UPS APPLICATIONS Raphael A. da Câmara, Ranoyca N. A. L. Silva, Gusavo A. L. Henn, Paulo P. Praça, Cícero M. T. Cruz, René P. Torrico-Bascopé Energy Processing and Conrol Group, Elecrical Engineering Deparmen, Universidade Federal do Ceará P. O. Box: 6001 Campus do Pici Foraleza-CE Brazil Absrac This paper presens a volage doubler boos recifier based on hree-sae swiching cells for Uninerrupible Power Supply (UPS) applicaions. Is main feaures are: high power facor, reduced conducion losses, weigh and volume, simple conrol sraegy, and connecion beween inpu and oupu enabling he use of inverer and bypass. A heoreical analysis, simulaion resuls and experimenal resuls from a 3kW lab model are presened. I. INTRODUCTION An equipmen ha has been highlighing in he power elecronics on is abiliy o supply clean and reliable power o criical loads such as indusrial processes, compuers, nework servers, elecommunicaions sysems, medical sysems, even in siuaions of power ouages or anomalies of he mains is he Uninerrupible Power Supply (UPS). An UPS can be classified ino hree ypes: On-line, Lineineracive and Sand-by [1]. Among he differen ypes of UPS sysems, he on-line UPS sysem is widely recognized as he superior opology in performance, power condiioning and load proecion [2]. On-line UPS sysems consis of a recifier, a baery se, an inverer, and a bypass. A ypical single-phase on-line UPS sysem based on full-bridge converers is shown in Fig. 1 (a). In his configuraion i is normally required an isolaing ransformer for proper operaion of he bypass circui. This isolaion ransformer, when operaing a he grid frequency, boh size and cos are considerable. Ohers opologies were proposed in lieraure o overcome his problem, using he isolaion ransformer in a high frequency DC link [3-5]. Alhough his UPS opology incorporaing a high frequency ransformer reduces weigh of he sysem, i has increased he number of acive swiches and power sages, compromising he sysem s overall efficiency and reliabiliy. bypass Transformerless UPS incorporaing a common neural bus line using a half-bridge converer and inverer has araced special ineres for applicaions in compuer and elecommunicaion sysems. A ypical single-phase on-line UPS sysem is shown in Fig. 1 (b). This ype of sysem is highly cos-effecive and accepable due o is oal power conversion efficiency improvemen, volume and weigh reducion [6-9]. However, some disadvanages are found as: unbalance beween he upper and lower side DC link capaciors, AC-DC and DC-AC converers swiches are exposed o oal DC link volage [10]. The single phase hree-level recifier wih a half-bridge inverer can be advanageous for many applicaions [11-12]. In his converer only half of he DC link volage is applied across he recifier swiches and he curren flows hrough only wo or hree power semiconducors simulaneously. Therefore, his converer presens less conducion losses, and a common neural bus line is conneced beween he middle poin of DC capaciors link, inpu and load, making i possible o realize he bypass operaion wihou an isolaing ransformer. However, wih he inenion o work wih oupu power over few kilowas, his converer has high weigh, volume, curren sress on he semiconducors devices presening a high cos of componens and low efficiency. Wihin his conex, his paper presens a volage doubler boos recifier based on hree-sae swiching cells [13] for UPS applicaion ha presens power facor correcion (PFC), reduced curren sress on semiconducors devices, reduced volume and weigh of he magneic componens, simple conrol sraegy and connecion beween he middle poin of DC link, inpu and load, enabling he bypass operaion wihou an isolaing ransformer. The heoreical analysis, simulaion resuls and experimenal resuls of a lab model of 3kW oupu power are presened o validae he proposal. bypass S L Si1 Si2 Lf S L Si1 Lf Vs C Baery bank Cf Load Vs Baery bank Cf Load Si3 Si4 Isolaion Transformer Si2 (a) (b) Fig. 1. A ypical single-phase on-line UPS sysem: (a) based on full-bridge converers; (b) based on half-bridge converers.

2 II. PROPOSED CONVERTER CIRCUIT A. Circui Descripion The proposed converer is shown in Fig. 2 and is UPS applicaion is presened in Fig. 3 wih a double half-bridge inverer such as a DC/AC converer. I consiss of one inducor, one auoransformer wih windings and, four diodes, wo bi-direcional conrolled swiches formed by - and - and wo capaciors. Le us consider only one boos converer due o he inheren symmery of he circui. The converer operaes only in coninuous conducion mode (CCM). The converer operaion modes are defined by comparison beween inpu volage and oupu volage in funcion of conrolled swiches duy cycle presened in Fig. 4. While he inpu volage is less han he half of oupu volage, he converer operaes in overlapping mode (duy cycle > 0.5) and, while he inpu volage is greaer han he half of oupu volage, he converer operaes in non-overlapping mode (duy cycle < 0.5). B. Converer Operaion Analysis The operaing sages in non-overlapping mode are shown in Fig. 5 according o he main waveforms in Fig. 6. During he ime inervals (0 1) and (2 3) occurs he energy sorage in he inducor and he curren increases linearly. Half of he load curren flows hrough diode in ime inerval (0 1) or in ime inerval (2 3) and half flows hrough swich in ime inerval (0 1) or in ime inerval (2 3). This way, he curren sresses of swiches are reduced. The ransfer of he energy sored in he inducors o he load occurs in ime inervals (1 2) and (3 T). The operaion of he opology in he negaive semicycle of he inpu volage is analogous o he posiive one. The operaing sages in he overlapping mode are shown in Fig. 7 according o he main waveforms in Fig. 8. During he ime inervals (0 1) and (2 3) occurs he energy sorage in he inducor and here is no power ransfer from he mains o he load. The ransfer of he energy sored lage 2. Vp o he load occurs in ime inervals (1 2) and (3 T). The operaion of he opology in he negaive semi-cycle of he inpu volage is analogous o he posiive one. Noe ha, for boh operaing modes, he inducor curren frequency is he double of swiching frequency enabling he size and volume reducion. Non-overlapping Mode D<0,5 Inerval ( 0 1 ), similar o ( 2 3 ) Overlapping Mode D>0,5 Non-overlapping Mode D<0, Angle Fig. 4. Operaion modes during one-cycle of he mains. 1 Inerval ( 1 2 ) and ( 3 T) Fig. 5. Operaing sages in non-overlapping mode. Fig. 2. Proposed hree-level boos opology. VOLTAGE DOUBLER RECTIFIER Si3 2 DOUBLE HALF-BRIDGE INVERTER Si1 Si2 GND Si4 Lf1 Cf1 Cf2 Lf2 Fig. 3. Proposed recifier wihin a UPS applicaion. 2 V G V G I M I I m Im/2 I IM/2 V I IM/2 Im/2 V V L T Fig. 6. Main heoreical waveforms in overlapping mode.

3 A simple conrol sraegy implemened wih well-know PWM inegraed circui UC3854BN for PFC [14-15] is adoped as main conroller. However, he IC has only one gaing signal for swiches. Thus, an exernal modulaion wih saw-ooh signal is used o obain wo PWM gaing signals wih half phase shifed. III. EXPERIMENTAL RESULTS Inerval ( 0 1 ), similar o ( 2 3 ) A. Converer Specificaions The proposed doubler boos recifier based on hree-sae swiching cells design specificaions are shown in Table I and II. The converer swiching frequency was assumed f s = 20kHz. C. Conrol Sraegy The converer conrol sraegy is achieved wih an analog scheme using convenional average curren-mode-conrol. The operaing conrol scheme is shown in Fig. 9. Inerval ( 1 2 ) and ( 3 T) Fig. 7. Operaing sages in overlapping mode. Fig. 8. Main heoreical waveforms in overlapping mode. Low Pass Filer UC3854BN K x 2 I A C Curren Regulaor PWM1 PWM2 Fig. 9. Converer conrol block. A.B C Iref B Vc 2 DRIVER - DRIVER - lage Regulaor Vref TABLE I. Design specificaions Oupu power Po = 3kW Mains inpu volage = 110Vac Oupu volage = Vdc Mains frequency f r = 60Hz Oupu volage ripple Δ = 5%. Inpu curren ripple ΔI1 = 20%.I1 Theoreical efficiency = 0,97 1) Inducor - The inducance is calculaed by (1), considering =200V: = = 78, 59μH. (1) 16 ΔI1 fs To he projec is adoped = 80μH. The rms inducor curren and he inducor peak curren is deermined using (2) and (3), respecively: 2 2 α Irms = = 28, 12A. (2) 4 α I p = = 39, 76 A. (3) Where α is he relaionship beween oupu volage and inpu peak volage. 2) Auoransformer - The rms winding curren and he peak curren is calculaed by (4) and (5): 2 α IrmsT 1 = = 14, 06 A. (4) 2 α I pt 1 = = 19, 88A. (5) 3) Conrolled swiches - The swich average curren and rms curren is given by (6) and (7), respecively: ( 4 α π) Iavg = = 493A,, (6) π 2 α ( 3 π α 8) Irms = = 819A,, (7) 6 π 4) Diodes - The diode average curren is given by (8): I avg Io = = 773A,. (8)

4 5) Filer capaciors - The capaciance value of = is defined by (9): Po 1989μF 2 π fr V =. (9) Δ o The converer parameers are presened in Table II. TABLE II. Parameers of converer L = 80μH Inducor NEE 65/33/26 (Thornon Ipec) N L = 21 urns (19 x 20AWG) Auoransformer NEE 55/28/21 (Thornon Ipec) N p = N s = 12 urns (10 x 20AWG) Swiches IRGP50B60P Diodes - 30EPH06 Capaciors and C = 2040μF (3x680µF/ 350V) B. Simulaion Resuls Fig. 10 shows he inpu volage and inpu curren waveforms where power facor correcion is observed. Fig. 11 shows he volage and curren waveforms hroughou conrolled swich in swiching frequency, Fig. 11(a) for non-overlapping mode and Fig. 11(b) for overlapping mode. Fig. 12 shows he volage and curren waveforms hroughou diode in swiching frequency, Fig. 12(a) for non-overlapping mode and Fig. 12(b) for overlapping mode. Fig. 13 shows he volage and curren waveforms hroughou inducor in swiching frequency, Fig. 13(a) for nonoverlapping mode and Fig. 13(b) for overlapping mode. Fig. 14 shows he oupu volage. Fig. 12. lage and curren waveforms of diode : (a) non-overlapping mode; (b)overlapping mode. Fig. 13. lage and curren waveforms of inducor : (a) non-overlapping mode; (b)overlapping mode. 400V Toal Oupu lage 300V Co1 Oupu lage Co2 Oupu lage 200V 100V 0V 350ms 360ms 370ms 380ms 390ms 400ms Time Fig. 14. Oupu volage waveforms. Fig. 10. Inpu volage and curren waveforms. Fig. 11. lage and curren waveforms of swich : (a) non-overlapping mode; (b) overlapping mode. C. Experimenal resuls A lab model picure is shown in Fig. 15. Fig. 16 shows he inpu volage and inpu curren waveforms where power facor correcion is observed. Fig. 17 shows he volage and curren waveforms hroughou conrolled swich in swiching frequency, Fig. 17(a) for non-overlapping mode and Fig. 17(b) for overlapping mode. Fig. 18 shows he volage and curren waveforms hroughou diode in swiching frequency, Fig. 18(a) for non-overlapping mode and Fig. 18(b) for overlapping mode. Fig. 19 shows he oupu volage and oupu curren waveforms. The oupu volage regulaion wihin a specified volage ripple is observed. Fig. 20 shows he efficiency curve of he proposed converer. Noe ha he proposed converer efficiency is kep around 97%, reaching a nominal power wih a yield of 97.24%.

5 (a) Fig. 15. Lab model picure. Fig. 16. Inpu volage and curren waveforms. (100V/div, 50A/div, 2ms/div). (b) Fig. 18. lage and curren waveforms of diode : (a) nonoverlapping mode (100V/div, 5A/div); (b) overlapping mode (100V/div, 10A/div). Time (10μs/div). (a) Fig. 19. Oupu volage and curren waveforms (200V/div, 5A/div, 10ms/div). 100,00% Efficiency (%) 99,00% 98,00% 97,00% 96,00% (b) Fig. 17. lage and curren waveforms of swich : (a) non-overlapping mode (100V/div, 10A/div); (b) overlapping mode (100V/div, 5A/div). Time (10μs/div). 95,00% Oupu Power (W) Fig. 20. Efficiency versus oupu power curve.

6 IV. CONCLUSION A volage doubler boos opology wih PFC characerisics based on hree-sae swiching cell and is heoreical analysis and experimenal resuls are presened in his paper. The imporan feaures observed in he proposed converer by experimenal resuls validaing are: high inpu power facor, simple conrol scheme using convenional conrol echnique, reduced conducion losses resuling in an efficiency over 97%, reduced volume and weigh of he magneic componens and connecion beween inpu and oupu enabling by-pass wihou isolaing ransformer. Thus, his converer is an ineresing opion for applicaion in UPS wih few kilowas power oupu. [13] G. V. T. Bascopé, I. Barbi, A single phase PFC 3kW converer using a hree-sae swiching cell, in PESC 04 Proceedings, vol. 5, pp , [14] P. C. Todd, UC3854 Conrolled Power Facor Correcion Circui Design, Unirode Applicaion Noes, vol. U-134, pp , [15] L. Balogh, UC3854A/B and UC3855A/B provide power limiing wih sinusoidal inpu curren for PFC fron ends, Unirode Design Noes DN-66, ACKNOWLEDGEMENT The auhors would like o hank CAPES for he financial suppor. REFERENCES [1] S. B. Bekiarov, A. Emadi, Uninerrupible Power Supplies:Classificaion, Operaion, Dynamics, and Conrol, in Proc. of IEEE APEC 02 Conf., pp , [2] J. M. Guerrero, L. G. Vicuna, J. Uceda, Uninerrupible power supply sysems provide proecion, IEEE Ind. Elecron. Mag., vol. 1, no. 1, pp , [3] K. Hirachi, e al., Swiched-mode PFC recifier wih high-frequency ransformer link for high-power densiy single phase UPS, in Proc. of PESC'97, vol. 01, pp , [4] R. Krishnan, Design and developmen of a high frequency on-line uninerrupible power supply, in Proc. of IECON'95, vol. 01, pp , [5] R. P. Torrico-Bascopé, E. M. Sá Jr, C. G. C. Branco, F. L. M. Anunes, PFC pre-regulaor wih high frequency isolaion using full-bridge chopper for UPS applicaions, in Proc. of INDUSCON 04, vol. 01, [6] K. Hirachi, M. Sakane, S. Niwa, T. Masui, Developmen of UPS using new ype of circuis, in Proc. of INTELEC 94, pp , [7] N. Hirao, T. Saonaga, T. Uemasu, T. Kohama, T. Ninomiya, M. Shoyama, Analyical consideraions on power loss in a hree-arm-ype Uninerupible Power Supply, in Proc. of PESC 98, vol. 2, pp , [8] K. Hirachi, A. Kajiyama, T. Mii, M. Nakaoka, Coseffecive bidirecional chopper-based baery link UPS wih common inpu-oupu bus line and is conrol scheme, in Proc. of IECON 96, vol. 3, pp , [9] S. B. Bekiarov, A. Nasiri, A. Emadi, A new reduced pars on-line single phase UPS sysem, in Proc. of IECON 03, vol. 1, pp , [10] C. G. C. Branco, C. M. T. Cruz, R. P. Torrico-Bascope, F. L. M. Anunes, L. H. S. C. Barreo, A ransformerless single phase on-line UPS wih 110V/220V inpu oupu volage, in Proc. of APEC 06, pp , [11] J. C. Calmon, Circui opologies for single-phase volage doubler boos recifiers, IEEE Trans. Power Elecron., vol. 8, no. 4, pp , Oc [12] G. J. Su, T. Ohno, A new opology for single phase UPS sysems, in Proc. of PCC 97, vol. 2, pp , 1997.