4D-Interleaving of Isolated ISOP Multi-Cell Converter Systems for Single Phase AC/DC Conversion

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1 2016 IEEE Proceedings of he Conference for Power Elecronics, Inelligen Moion, Power Qualiy (PCIM Europe 2016), Nuremberg, Germany, May 10-12, D-Inerleaving of Isolaed ISOP Muli-Cell Converer Sysems for Single Phase AC/DC Conversion M. Kasper M. Anivachis D. Boris J. W. Kolar G. Deboy This maerial is published in order o provide access o research resuls of he Power Elecronic Sysems Laboraory / D-ITET / ETH Zurich. Inernal or personal use of his maerial is permied. However, permission o reprin/republish his maerial for adverising or promoional purposes or for creaing new collecive works for resale or redisribuion mus be obained from he copyrigh holder. By choosing o view his documen, you agree o all provisions of he copyrigh laws proecing i.

2 4D-Inerleaving of Isolaed ISOP Muli-Cell Converer Sysems for Single Phase AC/DC Conversion Mahias Kasper, Power Elecronic Sysems Lab., ETH Zurich, CH, Michael Anivachis, Power Elecronic Sysems Lab., ETH Zurich, CH Dominik Boris, Power Elecronic Sysems Lab., ETH Zurich, CH Johann W. Kolar, Power Elecronic Sysems Lab., ETH Zurich, CH Gerald Deboy, Infineon Technologies Ausria AG, Villach, Ausria Absrac The muli-cell converer approach allows o break he performance barriers of convenional sysems by leveraging he advanages of using muliple inerleaved low volage and/or low curren converer cells. In his diges, a fourh dimension of inerleaving is proposed which considers he ime dependen degrees of freedom in he conrol of he enire muli-cell converer sysem. This new conrol concep is based on he possibiliy o decouple he operaion of he series conneced inpu sages from he parallel conneced oupu sages by using he energy sorage capabiliy of he DC-link capaciors. This diges shows how he 4D-inerleaving concep improves he sysem performance such as he efficiency which will be demonsraed wih measuremen resuls on a hardware prooype sysem in he final paper. 1. Inroducion Driven by he rising demand for highly efficien elecom and server power supplies resuling from he global rend of cloud compuing, he indusry research effors for new converer opologies wih improved performance concerning efficiency and power densiy have been considerably increased. A very promising approach described in (1) (cf. Fig. 1(b) and Fig. 2) owards a hyperefficien and super-compac elecom recifier (η = 98%, ρ =2.2kW/dm 3, V in,rms = 230 V,V ou = 48 V,P ra,o =3.3kW) is based on a muli-cell converer concep wih ISOP arrangemen of he converer cells. Each converer cell conains an AC/DC recifier inpu sage which is a full-bridge operaed wih Toem-Pole modulaion and an isolaed DC/DC converer oupu sage consising of a phase-shifed full bridge converer. This muli-cell ISOP configuraion allows o share he inpu volage among he converer cells and hus enables he use of low-volage semiconducors wih superior Figure-of-Meris hroughou he converer cells. In addiion, he cells can be operaed in an inerleaved fashion in order o increase he effecive swiching frequency of he enire sysem up o a muliple of a single converer cell s swiching frequency. These advanages of he ISOP converer approach provide significan benefis in erms of reduced conducion and swiching losses and smaller volumes of inducive componens and hea sinks (2). V DC,o V DC,i 0 -V DC,o N v,min v g Degree of Freedom v g L b i Converer Cell b i ou,1 i ou,o Degree of P sys,max AC DC Freedom v FB,1 V ou DC DC i ou,2 AC DC v FB,2 P cell,max p ou DC DC N v p,min FB,o V DC,i i ou,i 0 AC DC v FB,i DC DC (c) Min. nr. of acive DC/DC sages Min. nr. of acive AC/DC sages (b) Fig. 1: 4D inerleaving conceps ( and (c)) for an ISOP muli-cell elecom power supply module (b). The available degrees of freedom in he operaion of he sysem arise from he fac, ha for each operaing poin of inpu volage and oupu power only a cerain minimum number of acive AC/DC and DC/DC converer sages - N v,min and N p,min - is required. Any number of sages beween he minimum and he maximum available number of cells can be operaed a he AC/DC and (c) DC/DC sages. Furhermore, he number of acive cells can be differen for boh sages, as he DC-link capaciors employed in he cells decouple he power flow beween he inpu and he oupu sages.

3 DC Link Capaciors 400V v FB,o( ) 30A Single Cell 200V 0V 15A 0A EMI Filer -200V i b( ) -15A Boos Inducor Power & Conrol Boards -400V (b) Time /ms Fig. 2: Hardware demonsraor of a muli-cell elecom power supply module (3) wih N cells =6cells and (b) measured waveform of he converer inpu volage v FB,o and he curren i b in he inpu side boos inducor for he operaion wih N PWM =6PWM cells a a power level of P ou =1.5kW. The ISOP configuraion iself can be considered as a spaial, i.e. 3-dimensional inerleaving of muliple converer cells, where he cells are operaed wih a fixed operaion mode and/or consan ime-invarian inerleaving. In his paper, a 4 h dimension (4D) of inerleaving he converer cells is inroduced, where he operaion mode (PWM vs. fundamenal frequency modulaion) and/or he number of acive cells is varied over ime depending on he inpu volage and he load power level. In Sec. 2 he basic degrees of freedom in he operaion of he muli-cell converer of Fig. 1(b) which provide he possibiliy for 4D-inerleaving are inroduced. Furhermore, differen 4D-inerleaving conceps are proposed for he series conneced AC/DC inpu sages and he parallel conneced DC/DC oupu sages of he muli-cell sysem. In Sec. 3 he bes suied 4D-inerleaving conceps are idenified for boh sages by means of a comprehensive Pareo-opimizaion and analyical derivaions, respecively. Furhermore, he performance improvemens are quanified in comparison o a convenional sysem conrol and a balancing scheme for he DC-link volages is inroduced. 2. 4D-Inerleaving of ISOP Converers For convenional 3D-inerleaving muli-cell converer sysems wih ISOP configuraion are usually operaed wih a common duy cycle for all AC/DC recifier sages and all DC/DC converer sages, since his ensures an equal volage sharing a he series conneced inpus and an equal curren sharing a he parallel conneced oupus of he converer cells (4; 5). However, his modulaion scheme, does no ake ino accoun ha he ime-varying inpu volage and load power in addiion o he presence of large DC-link capaciors provide addiional degrees of freedom for he operaion of he sysem. Depending on he inpu volage and oupu power, he number of acive recifier sages and oupu sages can vary over ime as long as he following hree condiions are fulfilled: Inpu volage: A any given ime he AC/DC recifier sages have o provide a volage v FB,o () which is defined by he grid volage, i.e. v g () v FB,o () over a swiching period, where v FB,o () = N cells i=1 v FB,i() = N cells i=1 V DC,i m i () wih m i denoing he modulaion index of a cell. This allows o derive a minimum number of acive recifier sages N v,min ha are required vg() for he operaion of he sysem: N v,min = V DC,i (cf. Fig. 1). Oupu curren: The oal oupu curren i ou,o () which is provided by he parallel conneced DC/DC converers has o be equal o he load curren, i.e. i load () =i ou,o () = N cells i=1 i ou,i(). Since each converer cell has a maximum power and hus also a maximum curren raing I DC/DC,max, a minimum number N p,min of converer cells required for he power ransfer can be derived as N p,min = i load() I DC/DC,max (cf. Fig. 1(c)). DC link capaciors: The DC-link capaciance is ypically sized for a hold-up ime requiremen. -30A

4 N v,op N PWM N FFM,on 1 N v,op N PWM N FFM,on V DC,6 v FB,6 V DC,5 v FB,5 v g 0.5 v g V DC,o m ac V DC,4 V DC,3 v FB,4 v FB,3 V DC,2 v FB,2 0 0 π π 3 π π 0 π π 3 π π Grid volage angle (b) Grid volage angle Fig. 3: Examples of he 4D-inerleaving conceps for he series conneced AC/DC recifier sages: operaion wih a variable number of PWM modules where all acive recifier sages (N v,op ) are operaed wih PWM wih he same modulaion index m ac. The minimum number of acive PWM sages is se o N PWM,min =1; (b) operaion wih a fixed number of PWM sages (i.e. N PWM =1) where he remaining cells are operaed wih fundamenal frequency and are eiher urned on or off (N FFM,on = N v,op N PWM ). Therefore, especially a low-power levels, his capaciance allows o have a power flow of he AC/DC recifier sages ha is differen from he power flow of he DC/DC converers. The difference in he power flow is hen sored in or supplied by he DC-link capaciors. This means, ha he number of acive AC/DC recifier sages N v,op a a given ime can be differen from he number of acive DC/DC converer sages N p,op as long as he ne power flow of he DC-link capaciors of each cell is zero over a cerain ime inerval, e.g. some milliseconds. Based on he above menioned degrees of freedom, a selecion of modulaion schemes making use of he 4h dimension of inerleaving is presened in he following paragraphs. V DC,1 v FB, AC/DC Recifier Inpu Sages The oal sinusoidal cell inpu volage v FB,o can be disribued among he AC/DC recifier sages in differen ways. Apar from he number of acive modules (N v,op [N v,min,n cells ]) he mode of operaion of each acive module can also be chosen. Namely, an acive module can be eiher operaed wih PWM modulaion or wih fundamenal frequency modulaion (ON-OFF). Based on hese degrees of freedom, wo essenially differen modulaions schemes can be idenified: Variable number of PWM cells: In his modulaion scheme only he minimum number N v,op = N v,min of required cells is operaed wih PWM while he remaining cells are urned off, as shown in Fig. 3. This means, ha he number of acive cells, N v,op, changes wih he ime-varying value of he grid volage. All acive cells are operaed wih a fixed frequency PWM, i.e. N PWM = N v,op, wih he same modulaion index and a phase shif beween he cells which depends on he number of acive cells, φ = 360 /N PWM. This leads o a varying effecive swiching frequency due o he varying number of acive cells. In order o limi he difference beween he maximum and minimum effecive swiching frequency, a lower limi for he number of acive PWM cells, N PWM,min, can be defined. Fixed number of PWM cells: Insead of changing he number of PWM cells during a grid cycle, his modulaion scheme operaes wih a defined number of PWM cells a all imes (N PWM = cons), as depiced in Fig. 3(b) for he case of a single PWM cell (N PWM =1). The remaining cells are operaed wih fundamenal frequency which means hey are eiher urned on or off (N FFM,on = N v,op N PWM ). As a resul, in his operaion mode only a fixed number of cells (N PWM ) exhibis swiching losses, whereas he oher cells only have conducion losses. A disadvanage, however, is he reduced effecive swiching frequency which requires an increase of he boos inducance value in order o limi he peak-o-peak curren ripple of he

5 N PWM,min = 6 N PWM = 6 N PWM,min = 1 N PWM = Time [ms] (b) Time [ms] Fig. 4: Comparison of simulaed boos inducor curren ripple waveforms (i.e. curren i b wihou he 50 Hz low frequency componen) for differen 4D-inerleaving schemes: variable number of PWM modules (N PWM,min denoes he minimum number of acive PWM modules); (b) fixed numbers N PWM of PWM modules where he remaining cells are operaed as fundamenal frequency modules. (Sysem wih 6 cells and a swiching frequency of he PWM cells of f sw,pwm =20kHz, a boos inducance of L b =25μH, and a DC-link volage of each cell of V DC,cell =66V.) inpu curren. For all of he above cases, he insananeous cell power values are unequal and he individual DClink capacior volages inherenly flucuae. Thus, i is required o properly permue he operaion of he cells, e.g. by cyclically changing he selecion of PWM cells. Especially, in order o achieve an accurae cancellaion of harmonics by inerleaving muliple PWM cells, he DC-link volages of hese PWM cells should be kep as close as possible o he same value DC/DC Converer Oupu Sages Similarly o he volage disribuion among he inpu side series conneced AC/DC converer sages he oupu curren can be disribued in differen ways among he parallel conneced DC/DC converer oupu sages: Equal curren sharing: The number of acive DC/DC sages varies depending on he oupu curren. All cells are operaed wih he same curren reference value and herefore equally share he oupu curren. The curren reference of a single cell can be calculaed by dividing he oal oupu curren by he number of acive cells. As a drawback, however, he curren reference of each cell will exhibi a sep change every ime he number of acive cells changes, which requires a highly dynamic curren conroller in each cell. Unequal curren sharing: In his modulaion scheme he oupu curren is unequally divided among he acive cells. This migh be achieved e.g. if an addiional cell is only acivaed when he previously acived cell has reached is maximum curren value. This has he advanage ha he curren reference values of all cells are coninuously changed over ime wihou any sep changes (under he assumpion ha here are no load seps). As a drawback, he sress on he DC-link capaciors is heavily unbalanced as some cells operae a heir maximum power levels while ohers are in sand-by mode. A minimum number of DC/DC converer sages can be defined o reduce he oal curren ripple a he oupu by inerleaving he acive DC/DC converer sages. This can be applied o boh conceps, since he curren ripple a he oupu of an individual cell is independen from he curren level of he cell (i.e. he average value of he oupu curren). Thus, even he inerleaving of wo cells wih unequal curren sharing reduces he oupu curren ripple. 3. Simulaion and Opimizaion Resuls In his chaper he differen 4D-inerleaving modulaion schemes are comparaively evaluaed in order o idenify he bes possible modulaion schemes for he AC/DC and he DC/DC converer sages. In he following, he 4D-inerleaving modulaion schemes are applied o an ISOP muli-cell elecom power supply module wih N cells =6converer cells where each cell has a raed power

6 10 N PWM,min = 6 N PWM = 6 Volage [V] 1 10 N PWM,min = 1 N PWM = Frequency [khz] (b) Frequency [khz] Fig. 5: Comparison of he harmonic specrum of he inpu volage v FB,o of he series connecion of AC/DC converer cells (wihou he 50 Hz low frequency componen) for differen 4D-inerleaving schemes: variable number of PWM modules (N PWM,min denoes he minimum number of acive PWM modules); (b) fixed numbers of PWM modules N PWM where he remaining cells are operaed as fundamenal frequency modules. (Sysem wih 6 cells and a swiching frequency of he PWM cells of f sw,pwm =20kHzand a DC-link volage of each cell of V DC,cell =66V.) level of P ra = 550 W and a DC-link capaciance of C DC =8.8mFwih a nominal DC-link volage of V DC,cell =66V AC/DC Converer Sages The modulaion scheme of he AC/DC sages akes direc influence on he harmonic specrum of he inpu curren waveform, he RMS value of he inpu curren, and also on he oal swiching losses. The effec of he seleced modulaion scheme on he inpu curren waveform is shown for boh modulaion schemes (variable and fixed numbers of PWM cells) in Fig. 4 for wo seleced scenarios. The modulaion wih a variable number of PWM modules and a value of N PWM,min =6is equal o he operaion wih a fixed number of N PWM =6cells which is he sandard 3D inerleaving operaion as measured in Fig. 2(b). The harmonic specrum of he generaed converer inpu volage is shown for boh of he aforemenioned modulaion schemes in Fig. 5. I can be seen ha he modulaion wih he variable number of PWM modules (Fig. 5) leads o a more even disribuion of he swiching frequency harmonics over he frequency range, due o is varying effecive swiching frequency. As a remark, for he generaion of he plos in Fig. 4 and Fig. 5 he DC/DC sages were operaed wih convenional (3D) modulaion where all sages are acivaed and equally share he oal oupu power. Since he choice of he modulaion scheme affecs several sysem parameers, a comprehensive opimizaion of he enire inpu sage comprising he EMI filer, he boos inducor and he MOSFET chip area of he AC/DC full bridges has o be performed o ake ino accoun he dependencies beween he differen elemens and he modulaion schemes. This opimizaion allows o idenify he Pareo-limi of he rade-off beween efficiency and power-densiy of he enire recificaion sage by considering all available degrees of freedom given for he design: EMI filer: Regardless of he seleced modulaion scheme, he sysem has o comply wih he CISPR Class B direcive which specifies limis for he noise emissions in he frequency range of f CISPR = 150 khz 30 MHz. This requires he calculaion of he harmonic specrum for each modulaion scheme and he idenificaion of he Pareo-opimal filer designs which can be found by considering differen degrees of freedom like he number of filer sages and he choice of differen values for he filer elemens. Boos Inducor: The value of he boos inducance is anoher opimizaion parameer since a small value leads o a large inpu curren ripple which increases he RMS value and also he losses of he inducor and conducion losses of he MOSFETs. However, a large curren ripple also resuls in lower swiching losses of he MOSFETs as he hard-swiching insans occur a lower curren levels. In addiion, he design of he boos inducor represens a Pareoopimizaion problem by iself as for a given se of elecrical parameers differen inducor designs can be found due o he possibiliy of employing e.g. differen ypes of core maerial, core shapes, winding ypes (e.g. liz or foil windings), number of urns and air gap lenghs.

7 η / % N PWM,min = N PWM = D Bes D Proo Volume: -10% Losses: -17% (b) ρ / kw dm 3 Fig. 6: η-ρ efficiency vs. power-densiy Pareo-opimizaion resuls of he enire recificaion sage (incl. EMI filer, boos inducor, AC/DC full bridges, and DC-link capaciors): Performance rade-off wih a variable number of PWM cells for differen minimum numbers N PWM,min of PWM cells, and (b) performance space for a fixed number N PWM of PWM cells where he remaining cells are operaed wih fundamenal frequency modulaion. Compared o a convenional approach employed in he prooype sysem (D Proo, N PWM =6)a seleced design on he Pareo-fron (D Bes, N PWM =1) shows 10% lower oal volume and 17% lower losses. Swiching Frequency: The swiching frequency direcly impacs he swiching losses bu also he shape of he inpu curren for a given boos inducance. This also has an effec on he inducor design and he EMI filer design. Regarding he MOSFETs, a high swiching frequency leads o larger swiching losses bu o a lower curren ripple and hus o a lower curren RMS value which decreases he conducion losses. MOSFET Chip Areas: The chip area selecion of he MOSFETs allows o rade-off conducion losses which decrease wih a larger chip area and (urn-on) swiching losses which increase wih a larger chip area. The resuls of he Pareo-opimizaion of he enire recificaion sage, including he EMI filer, boos inducor, full-bridge MOSFETs of he AC/DC sages, DC-link capaciors (seleced for a hold-up ime of holdup =10ms), resisive PCB losses, and consan conrol losses, for operaion a raed power (P ra =3.3kW) are ploed in Fig. 6 and 6(b) for he modulaion scheme wih a variable number of PWM modules and he modulaion scheme wih a fixed number N PWM of PWM modules, respecively. I can be concluded ha he highes performance can be achieved by operaing only one cell wih PWM and he remaining cells wih fundamenal frequency modulaion. Compared o he design of he hardware demonsraor (D Proo )(3) wih a coninuous operaion of N PWM =6cells, he 4D-inerleaving concep allows o simulaneously improve he efficiency and he power densiy of he recificaion sage; he losses are reduced by 17% and he volume by 10%, as shown for design D Bes in Fig. 6(b). More deails abou boh designs can be found in Tab DC/DC Converer Sages For he parallel conneced DC/DC converer sages he mos efficien 4D inerleaving modulaion scheme can be analyically derived by assuming a generic loss funcion of each DC/DC converer Tab. 1: Comparison of he parameers of he AC/DC converer sages of he prooype design D Proo and he Pareo-opimal 4D-inerleaving design D Bes (cf. Fig. 6). Variable D Proo D Bes N PWM 6 1 f sw,pwm 20 khz 24 khz L b 25 μh 90μH EMI Filer Sages 3 3 Parallel MOSFETs 2 5

8 Sysem Efficiency [%] N p,min=1 N p,op =1 N p,min=2 N p,op=2 N p,min=3 N p,min=4 N p,min=5 N p,min=6 P sys 97 N p,op=3 P 3 N p,op=4 P 2 96 N p,op=5 Opimal Operaion P 1 N p,op=6 Efficiency gain Sysem Oupu Power [kw] (b) P 6 P 5 P 4 Example Load Profile P sys Nr.of acive cells (c) Nr.of acive cells P 6 P 5 P 4 P 3 P 2 P 1 Example Load Profile Fig. 7: 4D-inerleaving of he parallel conneced DC/DC converer sages of an ISOP sysem wih N cells =6 converer cells which leads o a higher par-load efficiency (cf. ) by always operaing only a subse of converer cells. (b) Operaion mode wih equal power reference values for all acive cells which resuls in disconinuous changes of he power levels of he individual acive cells. (c) Alernaive operaion wih unequal power levels of he converer cells bu smooh changes of he power levels of he individual cells. depending on he oupu power as p loss,i = k 0 + k 1 p ou,i + k 2 p 2 ou,i (1) where k 0 models he consan losses (e.g. auxiliary power), k 1 p ou,i he linearly dependen losses (e.g. a diode volage drop) and k 2 p 2 ou,i he quadraically dependen losses (e.g. resisive losses). The oal losses of he DC-DC converer sage comprising N DC/DC converers can hus be wrien as N N p losses,o = N k 0 + k 1 p ou,i + k 2 p 2 ou,i. (2) By applying he Lagrangian mehod o he minimizaion problem of (2) under he consrain of p ou,o () = N cells i=1 p ou,i() following soluion can be found for he general case i=1 p ou,1,op = p ou,2,op =... = p ou,n,op = p ou,o (3) N under which he oal losses are minimized. By insering he soluion of (3) in (2) he oal losses can be calculaed as p losses,o = N k 0 + k 1 p ou,o + k 2 p2 ou,o N. (4) The remaining opimizaion parameer is he opimum number of acive DC-DC converers N = N op [N p,min,n cells ] used for he power ransfer for maximum efficiency. By differeniaing (4) wih respec o N and seing he derivaive equal o zero, he opimal number of acive cells can be found as k 2 N op = p ou,o. (5) k 0 Since he number N op is ypically a raional number, he wo neares ineger values have o be considered and he ineger value which sill saisfies N op,in [N p,min,n cells ] and leads o lower losses according o (4) has o be considered. If none of he neares ineger values saisfies he condiion of N op,in [N p,min,n cells ] (ypically for sysems wih larger consan losses han quadraic losses, i.e. k 0 k 2 ), he value of N op,in = N p,min has o be chosen. As a conclusion, his means, ha he mos efficien 4D-inerleaving modulaion scheme for he parallel conneced DC/DC sages is obained by equally sharing he oal power and/or he oal oupu curren among he acive DC/DC cells. This allows o exend he level of highes efficiency also o very low power levels as shown in Fig. 7 for he muli-cell elecom recifier of Fig. 2. i=1

9 V DC,o (400V) v g 20A V DC,i 0 i g T p 2T p AC/DC sages DC/DC sages -V DC,o (-400V) Sage 1 Sage 2... Sage 6 Sage 1... Sage 6-20A PWM FFM... FFM T perm 68V 66V 64V Tp V DC,1... V DC,6 Fig. 8: Simulaion resuls of he 4D-inerleaving modulaion of he ISOP muli-cell elecom recifier sysem wih N cells =6a he operaing poin of P ou =1.5kW. A he inpu side only one AC/DC sage (Sage 1) is modulaed wih PWM while he remaining five sages are operaed wih fundamenal frequency modulaion (FFM). A he seleced power level of P ou =1.5kW he mos efficien operaion of he DC/DC sages is achieved wih N p,op = 4 acive DC/DC sages. The balancing algorihm selecs he acive AC/DC and DC/DC sages based on he DC-link volages of he cells. The permuaion ime inerval for he DC/DC sages is chosen as T perm =2ms. Compared o he sandard modulaion where all six DC/DC sages are operaed a all power levels, significan efficiency gains can be achieved a power levels below 30% of he raed power P ra,o. In order o avoid sep changes of he power reference values of he cells every ime he number of cells changes (cf. Fig. 7(b)) i is preferable o allow unequal reference values during ransien load changes (cf. Fig. 7(c)). 2Tp 3.3. DC-Link Volage Balancing The 4D-inerleaving modulaion schemes lead o an unequal sress of he DC-link capaciors since, on he one hand, a low inpu volages and oupu power only a fracion of he AC/DC sages and DC/DC sages is acive a a given ime and, on he oher hand, he number N v,op of acive AC/DC inpu sages can be differen from he number N p,op of acive DC/DC oupu sages. Thus, in order o balance he DC-link volages during he operaion wih 4D-inerleaving a proper permuaion algorihm has o be employed which acivaes/deacivaes he AC/DC and DC/DC sages of he cells in such way ha a minimal volage ripple on he DC-link capaciors is obained. One possible permuaion algorihm for he AC/DC sages is described below for a sysem wih N cells =6converer cells and a fixed number of N PWM =1PWM AC/DC sages and N FFM =5 AC/DC sages wih fundamenal frequency modulaion (FFM). In conras o he balancing scheme proposed in (6), he AC/DC sage which is seleced for PWM operaion is always he uppermos cell in he sack of converer cells, i.e he cell which is conneced o he inpu side boos inducor L b, since his minimizes he common-mode currens in he sysem caused by he swiching operaion of he PWM cell. The proposed permuaion algorihm works in such way, ha an addiional FFM AC/DC sage is acivaed every ime he modulaion index of he PWM cell reaches is upper limi and is deacivaed when he lower limi of he modulaion index of he PWM sage is

10 reached, similar o he concep shown in Fig. 3(b). The decision abou which FFM AC/DC sage o acivae/deacivae is based on he deviaion of he DC-link volages of he cells from he se-poin volage (V DC,se = 400 V/N cells ) in such a way ha he AC/DC sage of he cell wih he lowes DClink volage is always he nex one o be acivaed and he AC/DC sage of he cell wih he highes volage is he nex one o be deacivaed. Apar from he AC/DC sages of he cells he DC/DC sages can also be uilized for DC-link volage balancing by means of permuaion. For a sysem which operaes a a consan power level, however, here is no naural even when DC/DC sages have o be acivaed/deacivaed like here is for he AC/DC sages, due o he ime-varying inpu volage. Thus, a consan ime inerval of e.g. T perm =2msis chosen afer which he selecion of acive sages is re-evaluaed based on he DC-link volage values of he cells. This means, ha he DC/DC sages of he N p,op cells wih he highes DC-link volages are acivaed. Consequenly, he balancing of he DC-link volage is achieved by permuaion of he acive AC/DC and DC/DC sages which is shown in Fig. 8 for he operaion a a consan oupu power level of P ou,o =1.5kWwhere he mos efficien operaion is achieved wih N p,op =4acive DC/DC sages. As can be seen, he ISOP sysem can be operaed in a sable condiion wih 4D-inerleaving a he AC/DC and DC/DC sages while he DC-link volages are effecively balanced wih only small deviaions of around a maximum of ΔV DC 3V. 4. Conclusions A new dimension of inerleaving he operaion of he converer cells of an ISOP muli-cell elecom power supply module is presened. The proposed concep is based on a ime-varying acivaion/deacivaion of individual AC/DC inpu and DC/DC oupu sages of differen cells and uilizes he decoupling of he inpu and oupu sides of he cells provided by he energy sorage capabiliy of he DC-link capaciors. Differen 4D-inerleaving operaion schemes are discussed for he series conneced AC/DC sages and he parallel conneced DC/DC sages and evaluaed by means of a comprehensive η-ρ Pareo opimizaion and analyical calculaions. Compared o he sandard 3D-inerleaving he losses of he enire recifier sage can be reduced by 17% and he volume can be decreased by 10% and a very fla efficiency vs. oupu power characerisic of he parallel conneced DC/DC converer sages can be achieved. Considering he increasing imporance of higher par-load efficiency of elecom power supplies, he muli-cell converer approach in combinaion wih he proposed 4D-inerleaving concep herefore provides an ineresing soluion for fuure implemenaions. 5. References [1] M. Kasper, D. Boris, J. W. Kolar, and G. Deboy, Hyper-Efficien (98%) and Super-Compac (3.3kW/dm 3 ) Isolaed AC/DC Telecom Power Supply Module based on Muli-Cell Converer Approach, in Proc. of he IEEE Energy Conversion Congress and Exposiion (ECCE USA), pp , [2] M. Kasper, D. Boris, and J. Kolar, Scaling and Balancing of Muli-Cell Converers, in Proc. of he Inernaional Power Elecronics Conference (IPEC ECCE Asia), [3] M. Kasper, C.-W. Chen, D. Boris, J. Kolar, and G. Deboy, Hardware Verificaion of a Hyper-Efficien (98%) and Super-Compac (2.2kW/dm 3 ) Isolaed AC/DC Telecom Power Supply Module Based on Muli-Cell Converer Approach, in Proc. of he IEEE Applied Power Elecronics Conference and Exposiion (APEC), pp , [4] R. Giri, V. Choudhary, R. Ayyanar, and N. Mohan, Common-Duy-Raio Conrol of Inpu-Series Conneced Modular DC-DC Converers wih Acive Inpu Volage and Load-Curren Sharing, IEEE Trans. Ind. Appl., vol. 42, no. 4, pp , [5] W. van der Merwe and T. Mouon, Naural Balancing of he Two-Cell Back-o-Back Mulilevel Converer wih Specific Applicaion o he Solid-Sae Transformer Concep, in Proc. of he 4h IEEE Conf. on Indusrial Elecronics and Applicaions (ICIEA), pp , [6] H. Iman-Eini, J.-L. Schanen, S. Farhangi, and J. Roude, A Modular Sraegy for Conrol and Volage Balancing of Cascaded H-Bridge Recifiers, IEEE Trans. Power Elecron., vol. 23, no. 5, pp , 2008.

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