Chapter 2 Introduction: From PhaseLocked Loop to Costas Loop


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1 Chaper 2 Inroducion: From PhaseLocked Loop o Cosas Loop The Cosas loop can be considered an exended version of he phaselocked loop (PLL). The PLL has been invened in 932 by French engineer Henri de Belleszice []. In his firs applicaion, de Belleszice used he PLL as a synchronous demodulaor for double sideband ampliude modulaed signals wih carrier. The block diagram of a PLL is shown in Fig. 2.. I is buil from hree blocks, a phase deecor (PD), a loop filer (LF), and a volageconrolled oscillaor (VCO). In he firs PLL applicaions, an analog muliplier was used for he phase deecor [2]. Assuming for he firs momen ha boh signals U and U 2 are sinusoidal, we can wrie u ðþ ¼U sinðx þ h Þ u 2 ðþ ¼U 2 cosðx þ h 2 Þ where U,U 2 are he ampliudes of U and U 2, respecively, x is he radian frequency of he inpu signal U, and h and h 2 are he zero phases of U and U 2, respecively. Assume furher ha he sysem is already locked, i.e., boh signals have he same frequency, bu can have differen phases. In his case, he signals u and U 2 differ by 9 in he locked sae; hence, i is reasonable o define U as a sine wave and U 2 as a cosine wave. I can be shown ha he oupu signal of he phase deecor is proporional o sin(h h 2 ) = sin(h e ), where h e is called phase error. Bu he oupu signal of ha ype of phase deecor also conains a highfrequency erm, i.e., a sine erm having radian frequency 2 x. This erm is removed by he loop filer, which is mosly realized eiher as a laglead filer or as a PI filer (proporional Elecronic supplemenary maerial The online version of his chaper (doi:.7/ _2) conains supplemenary maerial, which is available o auhorized users. Springer Inernaional Publishing AG 28 R. Bes, Cosas Loops, hps://doi.org/.7/ _2 5
2 6 2 Inroducion: From PhaseLocked Loop o Cosas Loop Fig. 2. Block diagram of a phaselocked loop and inegral filer). More abou loop filers laer in his ex. The oupu signal u f of he loop filer is applied o he inpu of he VCO. When here exiss a phase error, he frequency of he VCO is adjused such ha finally he phase error becomes eiher or is a leas very small. Nex we consider a PLL circui used for synchronous demodulaion of AM signals. Figure 2.2 shows he relevan signals. The upper race is he modulaing signal. I is scaled such ha i is wihin he range from o. The middle race is he carrier signal c(). The modulaed signal U is given by u ¼ cðþð þ mu m ðþþ wih m = modulaion index. m mus be chosen m <, a commonly used value is m =.3. In his case, he modulaed signal u (lower race) is always inphase wih he carrier c(). If m were chosen larger han, U could be in aniphase wih he carrier when he modulaing signal has large negaive values. When he modulaed signal u is now applied o he inpu of a PLL, he oupu signal U 2 of he VCO would correcly lock ono ha signal, i.e., here would always be a phase difference of 9 beween u and u 2. Figure 2.3 shows he block diagram of a PLL designed for synchronous demodulaion of he ampliude modulaed signal. Four blocks have been added o he basic circui of Fig. 2., a 9 phase shifer, a muliplier (MUL), a lowpass filer (LPF), and a highpass filer (HPF). As we have seen, here is a phase difference of 9 beween U and U 2 when he PLL has locked. When U 2 is shifed by 9, he shifed signal U 2,shif is exacly inphase wih he modulaed carrier U. Wih he definiions u ¼ U sinðx þ h Þð þ mu m Þ u 2;shif ¼ U 2 sinðx þ h Þ
3 2 Inroducion: From PhaseLocked Loop o Cosas Loop 7 Modulaing signal um c u Carrier AM signal Fig. 2.2 Double sideband AM wih carrier. Upper race: modulaing signal U m, middle race: carrier c, lower race: modulaed signal U Fig. 2.3 PLL used for synchronous demodulaion of AM signal
4 8 2 Inroducion: From PhaseLocked Loop o Cosas Loop he oupu signal of he muliplier U Mul becomes u Mul ¼ U U 2 ð þ mu m Þ sin 2 ðx þ h Þ ¼ U U 2 ð þ mu m Þ 2 2 cosð2x þ 2h Þ We recognize ha U Mul conains a highfrequency erm cenered a wice he cener radian frequency x. This erm is removed from he lowpass filer; hence, is oupu signal is given by u LPF ¼ U U 2 ð þ mu m Þ 2 This signal conains a dc erm U U 2 /2. This can be removed if required by a highpass filer. The oupu of he highpass filer is hen u HPF ¼ U U 2 m u m 2 which is idenical wih he modulaing signal scaled by a facor U U 2 m/2. Whereas he PLL can be successfully used for he synchronous demodulaion of double sideband AM signals wih carrier, i fails when i cames o demodulaed AM signals wih suppressed carriers. The waveforms of such an AM signal are shown in Fig Firs race: modulaing signal U m. Second race: carrier c(). Third race: modulaed signal U. Fourh race: reconsruced carrier U 2,shif. The modulaed signal U is given here by u ¼ u m sinðx Þ When U m is posiive (cf. ime inerval from 4 ms), U is inphase wih he carrier. When U m becomes negaive, however, he U is in aniphase wih he carrier (cf. ime inerval from 4 8 ms). When U is applied now o he inpu of a PLL, his circui would rack he phase of he VCO oupu signal U 2 o he phase of U. The shifed signal U 2,shifed would be inphase wih U when U m is posiive, bu afer a ransien in he inerval 4 5 ms, i would lock in aniphase wih he carrier c (). If he circui in Fig. 2.3 were used o demolae he AM signal, he oupu signal U Mul would have wrong polariy during he inervals where U m is negaive. There is anoher applicaion where he PLL fails for he same reason: Binary Phase Shif Keying (BPSK). The signals are similar o hose in he previous example, as shown in Fig The same happens as in he previous example. Because he polariy of he BPSK signal is reversed when he binary signal becomes negaive, he reconsruced carrier U 2,shif is in aniphase wih he carrier c(), when he modulaing signal U m is negaive.
5 2 Inroducion: From PhaseLocked Loop o Cosas Loop 9 um c u u2,shif Modulaing signal Carrier AM signal Reconsruced carrier Fig. 2.4 Waveforms of a double sideband AM signal wih suppressed carrier Here he Cosas loop comes ino play [3]. Figure 2.6 shows he block diagram of he convenional Cosas loop for BPSK. Compared wih he PLL, his novel circui consiss of wo branches, he I branch and he Q branch, whereas he PLL has only one. The inpu signal is given by U = m() sin(x +h ), where m is he daa signal and can wo values, +c or c, where c is a consan. In many cases, c = is chosen. When he currenly ransmied bi is a logical one, m = + c, and when he currenly ransmied bi is a logical zero, m = c. The volageconrolled oscillaor in his circui has wo oupus ha differ by 9 inphase, i.e., a sine oupu and a cosine oupu. The inpu signal is muliplied by he sine wave in he I branch, and i is muliplied by he cosine wave in he Q branch. Consequenly, he oupu of he muliplier in he I branch becomes m() sin(x +h ) 2 sin(x +h 2 ). This signal conains a highfrequency erm whose frequency is cenered around 2 x. This erm is removed by lowpass filer LPF, and he oupu signal of his filer becomes m() cos(h h 2 ) = m() cos h e, where h e is he phase error. In analogy, he oupu signal of lowpass filer LPF2 becomes m() sin h e. Now he oupu signals of boh lowpass filers are muliplied; hence, he oupu signal of muliplier MUL is u d ¼ m2 2 sinð2 h eþ
6 2 Inroducion: From PhaseLocked Loop o Cosas Loop binary signal u2,shifed u c um Carrier BPSK signal Reconsruced carrier Fig. 2.5 Waveforms for BPSK. Firs race: binary signal u m. Second race: carrier c(). Third race: BPSK signal u. Fourh race: reconsruced carrier U 2,shif, shifed by 9 Fig. 2.6 Block diagram of Cosas loop for BPSK
7 2 Inroducion: From PhaseLocked Loop o Cosas Loop When he phase error is small, his can be wrien u d ¼ m 2 h e i.e., he muliplier represens a phase deecor having deecor gain K d ¼ m 2 We recognize ha he oupu signal u d of he phase deecor does no depend on he polariy of signal m, due o he facor m 2. Thus, he phase deecor oupu signal does no change polariy when m changes from posiive o negaive values and vice versa. The oupu signal u d of he muliplier (phase deecor) is applied o he inpu of he loop filer LF. This filer is always realized as a lowpass filer. Two kinds of loop filers are in use, he laglead filer and he PI filer (proporional and inegral filer) [2, 4]. When here is a phase error h e, he oupu signal of he loop filer conrols he frequency of he VCO such ha he phase error is reduced o zero or o a very small value. When he phase error has been reduced o zero or near zero, he oupu signal of lowpass filer LPF is idenical wih he daa signal m(). We have seen ha he Cosas loop can adjus he frequency and phase of he VCO such loop locks wih a phase difference h h 2 near zero. I should be noed ha he Cosas loop can also lock wih a phase difference h h 2 of p. Assume for he momen ha h h 2 has no ye aained he value p, bu is near p. We hen can se h h 2 ¼ p þ h e Under his condiion, he oupu signal of LPF becomes m() cos(h h 2 )= m () cos h e, and he oupu signal of LPF2 becomes m() sin h e. The oupu signal of he muliplier hen becomes again u d ¼ m 2 h e Here again, when here exiss a phase error, he frequency of he VCO will be adjused such ha he loop sably locks wih a phase difference h h 2 = p. We can conclude herefore ha he Cosas loop can lock a wo differen poins of equilibrium, i.e., wih h h 2 = or wih h h 2 = p. When he loop locks wih a phase difference of p, he oupu signal of lowpass filer LPF becomes m, i.e., is polariy ges invered. This is no necessarily a problem, because in many cases differenial encoding is used wih BPSK [5]. Wih sandard i.e., no differenial encoding he value of he currenly ransmied bi depends only on he polariy of signal m(). The Cosas loop can decide ha a ransmied bi is a logical when m is posiive or a logical when m is negaive. When differenial encoding is applied, he value of he currenly ransmied bi depends from wo values, i.e., from he polariy of he curren bi and he polariy of he previously ransmied bi. We define, for example, ha
8 2 2 Inroducion: From PhaseLocked Loop o Cosas Loop he currenly ransmied bi is a logical when curren and previous bi have opposie polariy, and ha he value of ha bi is a logical when hese wo samples have he same polariy. Under his condiion, he Cosas loop can lock ono any of he wo equilibrium saes. Nondifferenial encoding can be used when he Cosas loop can be brough o lock a priori wih he correc phase difference of. Assume ha a ransmier sars o send a series of binary daa, e.g., a series of 256 bis. To obain correc locking, a preamble is preceding he daa block, e.g., a series of 6 logical s. The Cosas loop mus now be equipped wih an iniializaion circui ha becomes acive a sar of daa ransmission. Because he Cosas loop knows he correc value of he firs received bis, he iniializaion circui can conrol he VCO such ha false locking (i.e., locking wih a phase difference of p is prevened). In Sec. 5.6, an example of a Cosas loop using such a preamble is presened. References. De Belleszice H., La Recepion Synchrone, L onde elecrique,, (932) 2. E. Roland, Bes, phaselocked loops, design, simulaion, and applicaions, 6h edn. (McGrawHill, New York, 27) 3. J.P. Cosas, Synchronous communicaions. Proc. IRE (956) 4. U. Rohde, J. Whiacker, Communicaions receivers (Sofware Radios, and Design, McGrawHill, DSP, 2) 5. B. Sklar, Digial communicaions, fundamenals and applicaions (Prenice Hall, USA, 988)
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