A ZVS Integrated Single-Input-Dual-Output DC/DC Converter for High Step-up Applications

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1 A ZS Inegraed Single-Inpu-Dual-Oupu / Converer for High Sep-up Applicaions Ming Shang, Suden Member, IEEE, Haoyu Wang, Member, IEEE School of Informaion Science and Technology ShanghaiTech Universiy Shanghai, China wanghy@shanghaiech.edu.cn Absrac This paper presens a novel inegraed dc/dc opology wih a sep-up oupu and a sep-down oupu. A new conrol scheme is developed o regulae boh oupus simulaneously. Compared wih discree configuraions, he proposed inegraed converer uilizes a lower number of swiches due o he reuse of componens. The converer characerisics are sudied comprehensively. I is demonsraed ha all MOSFETs are urned on a zero volage wih reduced swiching losses. For he sep-up sage, he converer provides a high boos raio and is able o clamp he swich volage spikes. For he sep-down sage, he seady-sae characerisics and he dynamic performances are similar o ha of he convenional buck converer. Moreover, he sep-down oupu por can be exended o muliple pors, where he single-inpu-muliple-oupu SIMO) version of converer can be derived. A 25 W, 42 o 39 and 15 converer prooype is designed, analyzed and esed. The experimenal resuls are presened o verify he feasibiliy of he opology. Keywords dc/dc converer; inegraed converer; single-inpudual-oupu SIDO); single-inpu-muliple-oupu; zero volage swiching. Single Inpu Single Inpu High Sep-up Converer Sep-down Converer a) Inegraed Dual Oupus Converer v o1 v o2 v o1 v o2 I. INTODUCTION Muliple oupus dc/dc converers are used in a wide variey of applicaions, such as LED drivers [1], [2], dc nanogrids [3] [5], porable devices [6], plug-in elecric vehicles [7], mulilevel inverers [8] and communicaion power supplies [9]. Among hem, SIMO dc/dc converers have heir advanage of reduced circui complexiy. Fig.1 a) shows a ypical sysem diagram wih wo discree power sages. While Fig. 1 b) shows an inegraed dual oupu sysem implemened wih a hree por converer. In comparison wih he discree version, he inegraed converer uilizes a lower number of swiches due o he reuse of componens. This leads o reduced swiching losses and he removal of he redundan componens. Meanwhile, many applicaions such as high inensiy discharge lamp ballas used in auomoive headlamps, call for high sep-up raio converers [1]. The main challenges lie in a) how o exend he sep-up raio; and b) how o alleviae he volage spikes across he swiching devices inroduced from he ransformer leakage inducor [11]. A flyback-boos derived converer is proposed in [11]. The proposed opology provides a high volage gain wihou incurring exreme duy raios. However, he opology is only explored in single-inpu-single-oupu scenarios. In [12], he b) Fig. 1. Schemaic of power converer archiecures wih dual dc oupus: a) discree version; b) inegraed version. concep of SIMO was repored. A class of SIMO converers have been inroduced in [13] [16]. In [13], [14], some highly efficien SIMO dc/dc converers were proposed. However, only one acive swich is employed. This makes i infeasible o regulae boh oupus simulaneously. A SIMO dc/dc converer wih reused swiches [15] was proposed. However, i can only provide sep-down oupus. This means ha i is no an opion for applicaions where sep-up oupu is required. A family of SIMO dc/dc opologies wih one sep-up and muliple sep-down oupus are proposed in [16]. However, he converer suffers from considerable swiching losses due o he hard swiching. This paper proposes a novel inegraed dual-oupu converer as showed in he Fig. 2), which can provide one high sep-up oupu and one sep-down oupu. The proposed opology enjoys he benefis of a) reduced swich coun compared wih is discree counerpars; b) zero volage swiching ZS) among This work is sponsored in par by Shanghai Sailing Program 16YF1476) /16/$ IEEE

2 i L C b Operaion modes I II IIII I II III IX v L m i v i D 1 C O1 co1 G D 1 T s D 3 T s i Q 1 i Q 3 i C O2 co2 o G T s Q 2 i L 1 C 1 1 o1 G Fig. 2. Schemaic of he proposed inegraed SIDO converer. all he MOSFETs and reduced swiching losses; c) precise and independen conrol of he dual oupus; and d) he exension capabiliy o muliple sep-down oupu pors. II. POPOSED SIDO CONETE i i A. Topology Descripion The proposed converer origins from he convenional flyback converer. As shown in Fig. 2, a volage-doubler recifier nework is added on he secondary side of he flyback converer. Furhermore, a bidirecional boos converer is insered o form a parallel-inpu-series-oupu configuraion. Moreover, by adding swich Q 2 ) series wih Q 1 plus a LC ler nework, a sep-down oupu por is implemened. By acively conrolling he duy raios of Q 1-3, he converer provides a high sep-up oupu and a sep-down oupu simulaneously. The inermediae bidirecional boos srucure ensures he sof swiching of all he swiches. Furher advanages such as a) high swich working frequency, b) high device uilizaion rae, and c) swich volage sress clamping can also be achieved using he proposed opology. B. Operaion Principle The key seady sae waveforms of he proposed inegraed SIDO converer are ploed in Fig. 3. As shown, in each swiching cycle, here are nine differen operaing modes. The nex swiching cycle is symmerical o he firs swiching cycle. One specific swiching period, [, 9 ) is exraced for deail analysis. Those nine operaing modes correspond o nine equivalen circuis as ploed in Fig. 4. The operaing modes analysis is based on he assumpion ha C b, C 1, C o1 and C o2 are sufficienly large, such ha heir volage ripples can be ignored. Thus, hose capacior volages are considered as dc volages,,, Co1 and Co2, respecively. Mode I: [, 1 ). A -, he body diodes of Q 1 and Q 2 are conducing, which creaes a zero volage condiion for he urning on of he MOSFETs. A, he MOSFETs channels are urned on wih ZS. The volage across L m is cb co1 )/n. While he volage across C b is negaive, as shown in Fig. 4a). Mode I ends when he curren hrough he capacior C b i ) reaches zero. In mode I, he curren hrough he inducor L i ) increases linearly as follows, i Q i i cb i D i i i i Fig. 3. Seady sae operaion waveforms. ) + / n i i i co1 ) + ) he curren hrough he inducor L 1 i ) decreases linearly as, o1 1) i ) = ) + i ) 2) Mode II: [ 1, 2 ). A 1, he posiive erminal of C b is conneced o he coupling poin of he ransformer via D 1. I reverses is polariy o negaive. is urned off and D 1 is urned on. Mode II ends when Q 2 is urned off. In mode II, i coninues o decrease, i increases linearly as follows, / n ) = 1) + 1) L Mode III: [ 2, 3 ). A 2, Q 2 is urned off. Since i is posiive, he body diode of Q 3 begins o conduc. The applied volage across L 1 is posiive. Thus, i and i cb increase linearly 3)

3 v v v i i i i i i i i 1 1 i 1 1 i 1 1 a) b) c) v v v i i i i i i i i i 1 1 d) e) f) v v v i i i i i i i 1 1 i 1 1 i 1 1 g) Fig. 4. Converer equivalen circuis in differen operaion modes. respecively. Mode III ends when Q 3 is urned on. In mode III, i decreases linearly, / n i i i co2 2) + 2) i increases linearly as, co2 o ) i ) = ) + i ) 5) Mode I: [ 3, 4 ). A 3, Q 3 is urned on wih ZS. i coninues o increase and he i coninues o decrease, respecively. Mode : [ 4, 5 ). Before 4, i coninues o increase linearly. A 4, i reverses is polariy o posiive, and i coninues o decrease linearly. Mode I: [ 5, 6 ). Before 5, i cb coninues o increase linearly. A 4, i cb reverses is polariy o posiive. Meanwhile, is urned on and D 1 is urned off. Mode I ends when Q 1 is urned off. In his mode, i decreases linearly as, + )/ n i i i co2 co1 5) + 5) Mode II: [ 6, 7 ). A 6, Q 1 is urned off; i drops o zero; and i reaches is peak value. In mode II, i is posiive. Thus, he body diode of Q 2 sars o conduc. Mode II ends when i 6) h) reaches zero. In mode II, i coninues o decrease linearly and i decreases linearly as, i ) = ) + i ) 7) o1 6 6 Mode III: [ 7, 8 ). A 7, i and i change heir polariies o negaive and posiive, respecively. Mode III ends when Q 1 is urned off. In his mode, i and i coninue o decrease linearly. Mode IX: [ 8, 9 ). A 8, Q 3 is urned off, i cb reaches is peak value. In his mode, i and i boh change heir polariies o negaive and flow hrough he body diodes of Q 1 and Q 2. Mode IX ends when Q 1 and Q 2 are urned on, which denoes he sar of he nex swiching period. i coninues o decrease linearly and i decreases linearly as, )/ n i i i co1 8) + 8) III. CICUIT ANALYSIS AND DESIGN CONSIDEATIONS A. lage Gain Derivaion of he volage conversion raio is based on hose approximaions: i) 8)

4 1-D 1 )T s G Q D 1 T s G G T s D 3 T s G i i i i 2n/ )I O [1+n)/ ]I O I o 2/ )I O i Fig. 5. Gae signals and simplified curren waveforms. i L v L m i Q 1 i Q 2 Q n i v cb D 1 C O1 Q n+1 i i Q,n+1 L 1 i Ln i Qn C b C n-1 n o,n-1 C O2 co2 C 1 1 o1 Fig. 6. Proposed inegraed muliple-oupus dc/dc converer srucure. M v carrier ) co1 o a) The filering oupu capaciances are sufficienly large. b) The converer is ideal wihou inermediae energy losses. c) The curren ripple of he magneizing inducor is much smaller han ha of he leakage inducor and can be assumed as zero. d) The relaively narrow ime inervals, - 1, 8-9 and 2-5, can be assumed o be zero. Fig. 5 shows he corresponding curren waveforms under hose assumpions. According o he law of energy conservaion, by applying he principles of capacior charge balance on C b, and vol-second balance on L and L m, he sep-up raio of he converer, M 1, can be derived as, 1 n) 2 2) 1 2) o M1 = = 1+ i nl f s D D 9) where, f s is he swiching frequency, is he load resisance on he high volage oupu, and is he duy cycle of Q 2. When n equals o zero, M 1 coincides wih he sep-up raio of he classical boos converer. The sep-down raio of he converer is, 1 1 Co2 = = 1 D 1) i Co2 i 2 where, D 1 is he duy cycle of Q 1. From Eq. 1, i can be seen ha he sep-down oupu can be regulaed by D 1 and. B. Topology Exenion The proposed dual oupu converer can be exended o is n oupus version by adding n1 series-conneced swiches and LC ler neworks. The single inpu n oupus dc/dc archiecure can provide a high sep-up oupu and n-1 sep-down oupus. Fig. 6 demonsraes he schemaic of he exended circui. According o he analysis of he dual-oupu converer, he n-sage sep-down raio of he converer as shown in he shadowed area) can be derived as, c1 c2 G G Q G Q G τ d G, G G, Fig. 7. PWM signals generaion schemaic D D D = = on, 1 on, 1 on, 2 Co2 1 2 n, n 2 C, n 3 1 Dn 11) C. PWM Conrol Sraegy As aforemenioned, D 1 and can regulae each of he individual oupu precisely. In his secion, a simple PWM based conrol scheme is inroduced. The main scheme for PWM signals generaion is demonsraed in Fig. 7. The modulaing signals c1 & c2 ) are compared wih he same carrier signal v carrier )). Thus, he gae signals of Q 2 and Q 3 G and G ) are generaed. In order o ensure he ZS of Q 2, synchronous gae signals of Q 2 and Q 3 G and G ) are adoped. This means ha Q 2 is urned on ogeher wih he Q 1. I should be noed ha a shor ime delay τ d ) mus be enforced beween wo differen carrier signals. τ d can be found as, c 1 c2) τ d = 12) 2 f M

5 v o v o1 v o,n-1 Hs) Hs) Hs) H v v e v c d 1 G G c1s) PWM - v o_ref H v v e v c d 2 G G c2s) PWM - v o1_ref H v v v c e G cns) - PWM where, f is he frequency of he carrier signal. The PWM signal generaion scheme for muli oupus converer is shown in Fig. 8. The oupu volage o is sampled by a volage sensor wih is s-domain gain equal o Hs). Then H v is compared wih a reference signal v o,ref ) o generae he error signal v e ). The modulaing signal of Q 1 equals o v e imes he compensaor gain, G c1 s). Then i is fed ino he pulse-widh modulaor o generae he PWM signal d 1. For he oher PWM signals generaions, due o he inegraed srucure, he error amplifier EA) oupu of he higher sage is he sum of he EA oupu of he previous sage and he presen EA value. The gae signal of Q n+1 is complemenary wih ha of Q n. Since G and G can be regulaed independenly, he sep-up and sep-down oupus can be conrolled independenly. I. ESULTS A 25 W, 42 inpu, 39, 15 oupus converer is designed. The specificaions and design parameers of he prooype are summarized in Table I. Fig. 9 a) shows ha how he sepped up volage varies wih he variaion of. As shown, he high oupu volage increases wih he increase of. A wide oupu volage range from 25 o 5 is mapped o he range of from.5 o.8. Fig. 9 b) demonsraes he variaion of he sep-down volage wih D 1 is consan); while Fig. 9 c) shows how he sep-down volage varies wih D 1 is consan). The simulaion resuls agree well wih he heoreical predicions. Fig. 1 demonsraes he gae-source volage and he drain-source volage waveforms of Q 2 and Q 3. As shown, v DS2 v o,n-1_ref -1 Fig. 8 PWM conrol schemaic for muli oupus converer. TABLE I CICUIT SPECIFICATIONS AND DESIGN PAAMETES Quaniy Symbol Parameer Inpu volage i 42 Oupus volage o 4 o1 15 aed power P 26 W Primary side inducor L 1 μh Secondary side inducor L 1 5 μh Magneizing inducor L m 3 μh Secondary side capacior C b 1 μf Oupu capacior 1 C o1 1 μf Oupu capacior 2 C o2 1 μf Swiching frequency f s 1 khz d n G Qn d n+1 G Q,n+1 High sep-up volage [] Sep-down volage [] Sep-down volage [] D 1 =.7-4 D 1 =.6-5 D 1 =.5-6 Simulaion esuls and v DS3 drop o zero before he conducion of MOSFET channels. i conribues o discharge he MOSFET parasiic capaciors. Therefore, ZS is achieved during he MOSFET urn-on process. Similar ZS phenomenon also applies o Q 1, as shown in Fig. 11. Fig. 11 shows he volage waveforms of MOSFET Q 1 and he curren waveforms of he oupu recifiers D 1 & ). As can be seen from he figure, he ZS of he swich Q 1 and he zero curren urn-off of each recifier is achieved. Fig. 12 shows he waveforms of he, o, o1, as well as i a he raed power. The oupu volage waveforms are very clean wihou high frequency ringing. The waveform of i agrees well wih he aforemenioned seady sae analysis. a) b) D 1 c) Simulaion esuls =.3 =.4 =.5 Simulaion esuls Fig. 9. Converer performances: heoreical predicions compared wih simulaion resuls: a) high sep-up volage versus ; b) sep-down volage versus ; c) sep-down volage versus D 1.

6 v DS2 v GS2 v GS3 ZS derived. Moreover, by adding anoher series-conneced swiches and LC ler neworks, his dual-oupu opology can be easily exended o muliple oupus. Compared wih he radiional SIMO converers, his novel opology has he advanages in reduced swiching losses for all power MOSFETs are urned on wih ZS. Experimenal resuls are provided o highligh he meris of his converer. The proposed converer can be applied o high frequency applicaions. v DS3 Fig. 1. lage waveforms of he MOSFETs a full load. v DS1 v GS1 i ZS. CONCLUSIONS ZS Fig. 11. lage waveforms of he MOSFET Q 1 and he curren waveforms of he oupu recifiers. i o1 o i To improve he performance of he convenional high sepup converers in SIMO applicaions, a novel inegraed singleinpu-dual-oupus dc/dc opology wih one high sep-up oupu and one sep-down oupu is proposed in his paper. Seady sae analyses are conduced, and he volage conversion raios are i Fig. 12. The inpu and oupu volages and he primary leakage curren waveforms. EFEENCES [1] A.. Sankovic, L. Nerone, and P. Kulkarni, Modified synchronousbuck converer for a dimmable HID elecronic ballas, IEEE Trans. Ind. Elecron., vol. 59, no. 4, pp , 212. [2] H. Chen, Y. Zhang, and D. Ma, A SIMO parallel-sring driver IC for dimmable LED backlighing wih local bus volage opimizaion and single ime-shared regulaion loop, IEEE Trans. Power Elecron., vol. 27, no. 1, pp , 212. [3] C. N. Onwuchekwa and A. Kwasinski, A Modified-Time-Sharing Swiching Technique for Muliple-Inpu Converers, IEEE Trans. Power Elecron., vol. 27, no. 11, pp , 212. [4] P. Shamsi and B. Fahimi, Dynamic Behavior of Mulipor Power Elecronic Inerface Under Source/Load Disurbances, IEEE Trans. Ind. Elecron., vol. 6, no. 1, pp , 213. [5]. Adda, O. ay, S. Mishra, and A. Joshi, DSP based PWM conrol of Swiched Boos Inverer for nanogrid applicaions, in 38h Annual Conference on IEEE Indusrial Elecronics Sociey, 212, vol. 28, no. 3, pp [6] M. H. Huang and K. H. Chen, Single-inducor muli-oupu SIMO) - converers wih high ligh-load efficiency and minimized crossregulaion for porable devices, IEEE J. Solid-Sae Circuis, vol. 44, no. 4, pp , 29. [7] H. Wang, A Phase Shif Full Bridge Based econfigurable PE Onboard Charger Wih Exended ZS ange and Zero Duy Cycle Loss, in Proc. IEEE Applied Power Elecronics Conference and Exposiion, Long Beach, CA, Mar [8] S. Inverer, J. Wu, and C. Chou, A Solar Power Generaion Sysem Wih a Seven-Level Inverer, IEEE Trans. Power Elecron., vol. 29, no. 7, pp , 214. [9] E. Lam,. Bell, and D. Ashley, evoluionary Advances in Disribued Power Sysems, in Applied Power Elecronics Conference and Exposiion, 23, vol. 1, no. C, pp vo1.1. [1] Q. Zhao and F. C. Lee, High-efficiency, high sep-up dc-dc converers, IEEE Trans. Power Elecron., vol. 18, no. 1 I, pp , 23. [11] H. W. Seong, H. S. Kim, K. B. Park, G. W. Moon, and M. J. Youn, Zerovolage swiching flyback-boos converer wih volage-doubler recifier for high sep-up applicaions, in 21 IEEE Energy Conversion Congress and Exposiion, ECCE 21 - Proceedings, 21, pp [12] H. Masuo, Cpmparison of Muliple-Oupu - Converers Using Cross egulaion, IEEE Trans. Ind. Elecron., vol. I, no. 3, pp , 198. [13] Y. Ye and K. W. Eric Cheng, Single-swich single-inducor mulioupu pulse widh modulaion converers based on opimised swichedcapacior, IET Power Elecron., vol. 8, no. 11, pp , 215. [14]. Wai and K. Jheng, High-Efficiency Single-Inpu Muliple-Oupu, IEEE Trans. Power Elecron., vol. 28, no. 2, pp , 213. [15] G. Chen, J. Dong, Y. Deng, X. He, and Y. Wang, Inegraed Dual- Oupu Synchronous - Buck Converer, in 215 IEEE Energy Conversion Congress and Exposiion ECCE), 215, no. Dcm, pp [16] O. ay, S. Member, A. P. Josyula, S. Member, S. Mishra, S. Member, and A. Joshi, Inegraed Dual-Oupu Converer, IEEE Trans. Power Elecron., vol. 62, no. 1, pp , 215.

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