FROM ANALOG TO DIGITAL

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1 FROM ANALOG TO DIGITAL OBJECTIVES The objecives of his lecure are o: Inroduce sampling, he Nyquis Limi (Shannon s Sampling Theorem) and represenaion of signals in he frequency domain Inroduce basic conceps of analog-o-digial conversion (ADC) and quanizaion noise Consider pracical ADC and DAC devices This lecure covers he sampling and analog-o-digial conversion processes.

2 Signals in Time and Frequency Domains Time Domain Frequency Domain AMPLITUDE T 1 =1/f 1 AMPLITUDE TIME f 1 FREQUENCY T 2 =1/f 2 AMPLITUDE AMPLITUDE TIME f 2 FREQUENCY T = period f = frequency All elecronic signals can be visualized (signal represenaion) using wo basic mehods - he ime domain and he frequency domain.

3 Real Signals AMPLITUDE TIME Real life signals are a combinaion of many frequencies AMPLITUDE -f m f m 2f m FREQUENCY The bandwidh of a signal is he difference beween he maximum and minimum frequencies above a cerain ampliude

4 SHARE PRICES Sampling TIME (IN WEEKS) 14 Take snapshos of coninuously changing daa The Sampling Period is fixed This makes informaion undersandable My share price hi is lowes poin in week 4 My share price reached is peak in week 9 Sampling Period The period beween samples Sampling Time (The Snapsho) The ime aken o ake a sample (Monday am)

5 Missing Informaion PRICES PRICES T1 T2 T3 T4T5 T6 T1 T2 T3 T4 Acual variaion Inferred plo P BUY TIME P BUY TIME Non-periodic Snapshos May miss informaion The dip in prices beween T3 and T4 goes unnoiced Informaion canno be inerpreed easily Periodic Snapshos May miss informaion The dip in prices beween T2 and T3 goes unnoiced Easier o inerpre The key is he sampling frequency.

6 Geing he Sampling Righ TIME FREQUENCY f s - f a f s + f a CASE 1 f s >>f a f f s = Sampling Frequency f a = Signal Frequency f a f s 2f s CASE 2 f s =2f a f f a f s 2f s CASE 3 f s <2f a f f s Inferred Signal Alias Original Signal f a

7 Limiing he Specrum Signals in he real world conain many frequencies f s f m Aliasing f s f Frequency componens greaer han 1/2f s cause aliasing (f>f m ) Ge rid of (filer ou) frequencies above f m (no aliasing) f s >2f m Then ensure ha he sampling rae is greaer han 2f m f f m

8 sample & Digiizing he Signal hold Aim is o obain 1, 0 represenaion s 4 s 8 s Sample signal periodically Hold sampled value unil nex sample s 4 s 8 s quanize??? Classify new signal ino levels (quanize he signal) More levels means more accuracy Signal = s 4 s 8 s

9 Quanizaion Error Quanizaion Error Quanizaion inroduces errors Increasing he number of quanizaion levels is no always he answer Non-uniform Quanizaion Use more levels where here are more variaions Use fewer levels where here are fewer variaions

10 Analog-o o-digial Converers (ADCs) Successive Approximaion ADC Volage V in - + Comparaor CONTROL LOGIC SUCCESSIVE APPROXIMATION 10 V 3 V 2 V 1 V V in ime Se DAC oupu o V 2 = 1 0 DAC generaes analog volage V 2 (V in >V 2 ) DAC Se MSB o 1 DAC now generaes V 3 Se LSB o 0 since V 3 >V in Digiize in wo cycles n Bis = n Cycles

11 Oher Types of ADCs Digiizing Pipeline ANALOG BAND LIMIT SAMPLE AND HOLD ADC DIGITIZE Dual Slope ADC- use a capacior conneced o a reference volage. Very precise Slow, Expensive Flash ADC- compare he volage in parallel wih a series of comparaors ha are aached o a resisive nework. Very fas Requires precision componens Sigma Dela ADC Uses mosly digial echnology Sable

12 From Digial o Analog Volage Source Muliplying DAC DIGITAL CONTROL V cc 10 For 10 Digial Conrol: Swich in R o supply (V cc ) 2R o ground (GND) Analog Oupu = (R1/R) * V cc Gain = R1/Inpu Resisance THE OUTPUT V O = - [ V in * ( R 1 /R) + V in * (R 1 /2R) ] R 2R - R 1 V O MSB MSB = Mos Significan Bi LSB = Leas Significan Bi LSB + ANALOG OUTPUT Possible Inpu and Oupus for R1 = R GND INPUTS OUTPUTS 1.5 V cc V cc 0.5 V cc 0

13 Smoohing he Oupu DAC LOW- PASS FILTER DIGITAL IN SAMPLE AND HOLD SMOOTHED OUTPUT Conver digial inpu o analog value Hold unil he nex digial inpu is convered Finally, smooh he oupu signal

14 Commercial Converers TLC32040 Analog Inerface Circui (AIC) ANALOG IN ANALOG OUT ANTI- ALIASING FILTER RECON- STRUCTION FILTER ADC DAC SERIAL PORT SERIAL DIGITAL OUT ADC and DAC on same chip Digiized daa serialized Inerfaces o serial por of DSP Programmable Anialiasing filer Programmable Reconsrucion filer (Smoohing Filer)

15 C54x DSK Design TMS320C54 PC PARALLEL PORT CTRL D0 D15 A0 A23 SERIAL PORT TLC32040 AIC ANALOG OUT ANALOG IN C54x, 16-Bi Fixed Poin DSP 2K x 16 Bis On-Chip RAM 64 x 32 Bis On-Chip Cache 40 ns Single-Cycle Insrucion Execuion Time Analog Inerface Uni (AIC) Conains ADC (14-bi) DAC (14-bi) Filers Parallel Por JTAG and Expansion Connecor

16 Summary Sampling Frequency 2 * Maximum Signal Frequency (no aliasing) Limi signal specrum o preven aliasing Quanizing analog signals Successive approximaion ADC Volage-muliplying DACs Serial analog inerface circui (TLC32040) DSK funcional blocks

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