Potato IC. Contact Potato Semiconductor for IP or detail. PotatoSemi High frequency noise cancellation technology.

Size: px

Start display at page:

Download "Potato IC. Contact Potato Semiconductor for IP or detail. PotatoSemi High frequency noise cancellation technology."

Cornelius Logan
5 years ago
Views:

1 How oes PoaoSemi Kill inside Of I? Volage mode differenial Logic. New Paen IP. d MOS logic by using high frequency noise cancellaion echnology Poao I Normal I Inpu1 Inpu2 Inpu3 ie Oupu1 Oupu2 Oupu High Frequency ancellaion bonding diagram ie ie Normal I bonding diagram Poao hip ie Normal hip ie Single o ifferenial ancellaion Translaor Single o ifferenial ancellaion Translaor High Frequency Volage Mode ancellaion ifferenial Logic ore High Frequency ifferenial o Single ancellaion Translaor Inpu Pad Inpu Pad Normal High Logic ore Oupu Pad S S S S R R R R SET SET RESET RESET PoaoSemi High frequency noise cancellaion echnology Normal High onac Poao Semiconducor for IP or deail.

2 ancellaion Logic Volage Mode ifferenial Logic d MOS logic by using high frequency noise cancellaion echnology Volage Mode ifferenial MOS Logic NN gae dvanage: 1. Very high oupu frequency. (The max. frequency can reach process max. frequency.) 2. Swiching noise can be eliminaing by noe o noe noise cancellaion. ( from noe & noise from noe bar will cancel each oher. from noe & noise from noe bar will cancel each oher. from noe & noise from noe bar will cancel each oher. from noe ou & noise from noe ou bar will cancel each oher.) 3. Rail o rail oupu signals. 4. Wihou swiching noise, logic oupu signal can be much sronger hen oher logic oupu signal. 5. Low jier. 6. Oupu signals can drive long disance. 7. No error bi. 8. No saic curren. 9. esign is very similar o normal MOS logic. I can be used for high frequency & high performance VLSI design. isadvanage: More complicae design hen normal MOS logic ier die size hen normal low speed MOS logic. Poao Semiconducor Is are using his echnology such as Normal saic MOS Logic NN gae ynamic Logic ynamic NN gae urren mode differenial Logic urren Mode ifferenial NN gae LK LK R 1 R 2 V 1 V 2 V V EE (-4.5 o -5.2V) dvanage: 1. Simple. 2. Small ie size. 3. No saic curren isadvanage: 1. High swiching noise. 2. Low operaing frequency. 3. Higher error bi rae. 4. Higher jier. 5. higher propagaion delay. 6. weak oupu signal. Mos low frequency logic Is are using his echnology such as regular 74 series MOS logic. dvanage: 1. Higher oupu frequency hen normal logic 2. Less inpu capaciance & less swiching noise from inpu & hen normal saic logic. isadvanage: 1. High Power consumpion. 2. an no run lower clock frequency 3. Oupu signal is swiching all he ime. Mos high clock frequency SI Is are using his echnology such as graphic chips. They usually work wih a big fan. dvanage: 1. High oupu frequency. 2. Low noise. 3. Low jier. isadvanage: 1. urren source design wih high saic curren. 2. omplicae design. 3. ifficul o design a perfec curren source. 4. Need many exra componens such as 50 ohm loading resisors. Mos high frequency oupus are using his echnology such as EL logic, PEL, LVS, ML ec.

3 ring Power ino Is How does decoupling capacior work? ll elecronics engineers know decoupling capacior. However, do you know how o make hem working properly? There are four examples show below. Only las circui can clean noise. Only opposie noise plus decoupling capacior working ogeher can release elecronics from capacior & clean up I & sysem noise. Example 1 Normal MOS logic wihou decoupling capacior Power volage beween & will change because of he swiching noise. Inpu ie Oupu NN Example 2 Normal MOS logic wih decoupling capacior ecoupling capacior will mainain power volage beween &, bu i can no clean noise. Inpu Oupu NN Example 3 Volage mode differenial logic wihou decoupling capacior Power volage beween & will change because of he posiive noise & is opposie noise. Inpu ie Oupu Example 4 (Poao echnology ) Volage mode differenial logic wih decoupling capacior Posiive noise & is opposie noise will cancel each oher. NN Inpu Oupu NN release elecronics release elecronics

4 How does he New Technology work? y using our special IO inerface, logic cells & design rule, we can conver mos of exising Logic chips ino much higher frequency han i was before. fer we conver he sandard chips, all chips become much more reliable, much less noise and much higher running frequency. ompare o 74 Series Logic Y PoaoSemi TI Fairchild Renesa NXP evice PO74G32 SN74LV32 74LVX32 H74LV32 74LV32 Vcc 1.65V ~ 3.6V 1.65V ~ 3.6V 2V - 3.6V 2V ~ 5.5V 1.65V ~ 3.6V Max. Frequency 2 GHz 200 MHz 200 MHz 200 MHz 200 MHz Propagaion delay (Max) 1.5 ns 2.8 ns 7.5 ns 6.5 ns 2.8 ns Low inpu capaciance 4.0 pf 4.0 pf 4.0 pf 4.0 pf 3.5 pf ompare o lock uffers IN PoaoSemi Pericom IT IS ypress NXP evice PO49FT FT FT3807E- MK Y2810 P3807 Vcc 1.65V ~ 3.6V 3.3V 3.3V 3.3V 2.5V or 3.3V 2.5V or 3.3V Max. Frequency 800M Hz 156 MHz 166 MHz 100MHz 250MHz 150 MHz pin o pin skew 80 ps 250 ps 100 ps 350 ps 380 ps 120 ps Pulse skew 250 ps 250 ps 250 ps 350 ps 200 ps 300 ps Propagaion delay (Max) 2.0 ns 2.5 ns 2.0 ns 3.8 ns 3.5 ns 2.5 ns Low inpu capaciance 3 pf 3.0 pf 3 pf 5 pf 3 pf 3 pf

5 How does he New Technology work? ompare o GHz us Swich EN1 EN2 PoaoSemi Pericom TI Fairchild evice PO31000 PI3H1000 SN FST3384 Vcc 1.65V ~ 3.6V 2.5V / 3.3V 2.3V ~ 3.6V 4.0V~5.5V Wide andwidh ( -3db ) 1.2GHz 500 MHz 500 MHz N/ Near-Zero elay Yes Yes Yes Yes Special design for differenial signals Yes No No No Ron (Max.) on (Typ.) 7.9 pf 6.4 pf 10 pf 5 pf Ulra-Low uiescen Power (Typ.) 0.1µ N/ 1000 µ 0.1µ uiescen Power (Max.) 3 µ 800 µ 2000 µ 3 µ 0 ompare o GHz Translaor PoaoSemi OnSemi Micrel TI IS evice PO100HSTL23 M100EPT23- SY89323L SN65LVS9637 IS83023I Vcc 2.4V ~ 3.6V 3V-3.6V 3V-3.6V 3V-3.6V 3V-3.6V Max. Frequency 1 GHz 275 MHz 275 MHz 200 MHz 350 MHz pin o pin skew 150 ps 125 ps 300 ps 400 ps 60 ps oupu skew (differen package) 300 ps 500 ps 500 ps 1000 ps 500 ps propagaion delay (Max) 1.8 ns 2.4 ns 2.5 ns 3 ns 2.4 ns

6 Nex Generaion Logic ells The bes way o improve an I is from he core circui srucure! High os High os High os Low os & Easy implemen es Performance High Frequency ancellaion MOS Logic urren Performance IP, SM, G, Flip hip Package Process GHz MOS Oupu 45nm, 55nm, 65nm, 90nm, 0.13um, 0.18um, 0.25um, 0.35um, 0.5um X86, ual ore, 64 rchiecure, ec. rchiecure 50 years old High MOS Logic ircui Srucure MOS echnology has been widely used for more hen 50 years. I delivers he low cos wih high yield. However, because of he unbalanced MOS srucure, i will generae high noise ino Power & ground. From he pas 50 years of I hisory, our GHz MOS oupu driver is he only echnology ha you can kill your chip inernal ground and power noise wihou scarifies your oupu performance. ecause of his noise cancellaion echnology, our oupu frequency can be 7 o 10 imes faser hen anyone else in his world. In addiion, because of his low noise -ech nology, any Is wih our oupu drivers can deliver he accuracy wihou any error. The example shows he oupu signal from our sandard logic PO74G32. The V is 3V. The oupu frequency from he measure- - men is 2GHz wih probe loading. The max frequency will be more han 2GHz. Vp-p is 2.075V. Vhigh is 2.175V. Vlow is 100mV.

PI90LV9637. LVDS High-Speed Differential Line Receivers. Features. Description. Applications PI90LV9637

PI90LV9637. LVDS High-Speed Differential Line Receivers. Features. Description. Applications PI90LV9637 LVDS High-Speed Differenial Line Receivers Feaures Signaling Raes >400Mbps (200 MHz) Single 3.3V Power Supply Design Acceps ±350mV (ypical) Differenial Swing Maximum Differenial Skew of 0.35ns Maximum