LECTURE 1 CMOS PHASE LOCKED LOOPS

Transcription

1 Lecure 01 (8/9/18) Page 1-1 Objecive LECTURE 1 CMOS PHASE LOCKED LOOPS OVERVIEW Undersand he principles and applicaions of phase locked loops using inegraed circui echnology wih emphasis on CMOS echnology. Topics Background Fundamenals Organizaion Sysems Perspecive Types of PLLs and PLL Measuremens PLL Applicaions and Examples Circuis Perspecive PLL Componens Technology Perspecive CMOS Technology

2 Lecure 01 (8/9/18) Page 1-2 Suggesed References Phase Locked Loops: 1. F.M Gardner, Phaselock Techniques, 2 nd ed., John-Wiley & Sons, Inc., NY, B. Razavi (ed.), Monolihic Phase-Locked Loops and Clock Recovery Circuis, IEEE Press, R.E. Bes, Phase-Locked Loops: Design, Simulaion, and Applicaions, 4 h ediion, McGraw-Hill, A. Hajimiri and T.H. Lee, The Design of Low Noise Oscillaors, Kluwer Academic Publishers, B. Razavi, Design of ICs for Opical Communicaions, McGraw-Hill, T.H. Lee, The Design of CMOS Radio-Frequency Inegraed Circuis, 2 nd ediion, Cambridge Universiy Press, NY, C. Quemada, e al, Design Mehodology for RF CMOS Phase Locked Loops, Arech House, Norwood, MA, 2009.

3 Lecure 01 (8/9/18) Page 1-3 Wha is a PLL? OPERATING PRINCIPLES OF PLLs A PLL conains hree basic componens as shown below: Inpu Oscillaor Oupu Phase Frequency Deecor Error Volage Conrolled Oscillaor Loop Filer Conolling Volage Phase/frequency deecor deermines he difference beween he phase and/or frequency of wo signals The loop filer removes he high-frequencies from he volage-conrolled oscillaor (VCO) conrolling volage The VCO produces and oupu frequency conrolled by a volage

4 Lecure 01 (8/9/18) Page 1-4 More Deailed PLL Block Diagram v in () The inpu or reference signal in The radian frequency of he inpu signal v osc () The oupu of he VCO osc The radian frequency of he VCO v d () The deecor oupu volage = K d e e Phase error beween v in () and v ou () = in - osc v c () The oupu volage of he loop filer and he conrol volage for he VCO

5 Lecure 01 (8/9/18) Page 1-5 The Phase Deecor and VCO in more Deail Phase Deecor: where v d () = K d e = K d ( in - osc ) K d is he gain of he phase deecor in = phase shif of he inpu volage osc = phase shif of he VCO oupu volage The unis of K d are vols/radians or simply vols assuming all phase shifs are in radians and no degrees. Volage Conrolled Oscillaor: osc = o + K o v c () where K o is he VCO gain and o is he free-running radian frequency. The unis of K o are rads/sec V or simply (sec V) -1 assuming all phase shifs are in radians and no degrees.

6 Lecure 01 (8/9/18) Page 1-6 PLL Operaion Locked Operaion: The loop is locked when he frequency of he VCO is exacly equal o he average frequency of he inpu signal. The PLL has he inheren abiliy o suppress noise superimposed on is inpu signal. To mainain he conrol volage needed for locked condiions, i is generally necessary for he oupu of he phase/frequency deecor o be nonzero. Unlocked Operaion: The VCO runs a a frequency called he free running frequency, o, which corresponds o zero conrol volage. The capure process is he means by which he loop goes from unlocked, free-running sae o ha of he locked sae.

7 Lecure 01 (8/9/18) Page 1-7 Transien Response of he PLL Assume he inpu frequency is increased by an amoun. v in () 1.) in increases by a o. 2.) The inpu signal leads he VCO and v d begins o increase. 3.) Afer a delay due o he loop filer, he VCO increases osc. v osc () 4.) As osc increases, he phase error reduces. v d () Insananeous values of v d 5.) Depending on he loop filer, he final phase error will be reduced o zero or o a finie value. w in w o w osc Dw w o Dw o

8 Lecure 01 (8/9/18) Page 1-8 Types of PLLs CLASSIFICATION OF PLL TYPES PLL Type Phase Deecor Loop Filer Conrolled Oscillaor Linear PLL (LPLL) Analog muliplier RC passive or acive Volage Digial PLL (DPLL) Digial deecor All digial PLL (ADPLL) Sofware PLL (SPLL) RC passive or acive Volage Digial deecor Digial filer Digially conrolled Sofware muliplier Sofware filer Sofware oscillaor The digial PLL (DPLL) has been he mainsay of mos PLLs and is called he classical digial PLL.

9 Lecure 01 (8/9/18) Page 1-9 The Linear PLL (LPLL) Inpu Analog Muliplier Error Analog Loop Filer Oscillaor Oupu Volage Conrolled Oscillaor Conrolling Volage Uses a analog muliplier for he PDF Loop filer is acive or passive analog VCO is analog

10 Lecure 01 (8/9/18) Page 1-10 The Digial PLL (DPLL) Inpu Digial Deecor Error Analog Loop Filer Conrolling Volage N Couner (opional) Oscillaor Oupu Volage Conrolled Oscillaor Phase deecor is digial Loop filer is passive of acive analog VCO is analog Called he Classical Digial PLL

11 Lecure 01 (8/9/18) Page 1-11 The All-Digial PLL (ADPLL) Inpu Digial Deecor Digial Error Digial Loop Filer Oscillaor Oupu Digially Conrolled Oscillaor Conrolling Digial Fixed Oscillaor (Clock) Phase deecor is digial Loop filer is digial VCO is digial Compaible wih modern CMOS echnology

12 Lecure 01 (8/9/18) Page 1-12 The Sofware PLL (SPLL) Inpu Analog- Digial Converer Sofware PLL Digial- Analog Converer Oupu Clock Phase deecor is implemened in sofware Loop filer is implemened in sofware Oscillaor is implemened in sofware driven by an exernal clock Requires analog o digial conversion a he inpu and digial o analog conversion a he oupu Sofware permis reconfiguring of he PLL

13 Lecure 01 (8/9/18) Page 1-13 SYSTEMS PERSPECTIVE OF LINEAR PHASE LOCK LOOPS (LPLLs) Inroducion Objecive: Undersand he operaing principles and classificaion of LPLLs. Organizaion: Sysems Perspecive Types of PLLs and PLL Measuremens PLL Applicaions and Examples Circuis Perspecive PLL Componens Technology Perspecive CMOS Technology

14 Lecure 01 (8/9/18) Page 1-14 Ouline LPLL Blocks Locked Sae Order of he LPLL Sysem The Acquisiion Process - Unlocked Sae Noise in he LPLL LPLL Sysem Design Simulaion of LPLLs

15 Lecure 01 (8/9/18) Page 1-15 Building Blocks of he LPLL LPLL BLOCKS v 1 () w 1 w 2 Phase Deecor (Muliplier) v d () Low Pass Filer v 2 () Volage Conrolled Oscillaor v f () v 1 () = Inpu signal, generally sinusoidal v 2 () = VCO oupu signal, may be sinusoidal or square wave v d () = Phase deecor oupu signal v f () = Loop filer oupu signal and conrolling signal o he VCO 1 = Frequency of he inpu signal 2 = Frequency of he VCO

16 Lecure 01 (8/9/18) Page 1-16 Loop Filers In he PLL, here are many high frequencies including noise ha mus be removed by he use of a low pass filer in order o achieve opimum performance. Types of Loop Filers: 1.) Passive lag filer (lag-lead) 1 + s 2 F(s) = where 1 + s( ) + R 1 R = R 1 C and 2 = R 2 C F(jw) db 0dB -20 db/decade V d - C Pole is a 1/( ) and he zero a 1/ 2. V f db Since he pole is smaller han he zero, he filer is lag-lead Passive filers should have no ampliude nonlineariy log 10 (w)

17 Lecure 01 (8/9/18) Page 1-17 Loop Filers - Coninued 2.) Acive Lag filer F(s) = K a 1 + s s 1 where 1 = R 1 C 1, 2 = R 2 C 2 and K a = - C 1 C 2 Easier o make lead-lag Can have gain (no necessarily desirable) Limied by he lineariy and noise of he op amp

18 Lecure 01 (8/9/18) Page 1-18 Loop Filers - Coninued 3.) Acive Proporional-Inegral (PI) Filer F(s) = 1 + s 2 s 1 where 1 = R 1 C and 2 = R 2 C Has large open loop gain a low frequencies Large hold range Limied by he lineariy and noise of he op amp Gain limis a he op amp open loop gain Sabiliy: To keep he loop sable, i is imporan o pick he loop filer so ha i does no inroduce more han a 90 phase shif in he loop.

19 Lecure 01 (8/9/18) Page 1-19 Phase s I is imporan o remember ha frequency and phase are relaed as d d = = d Transfer funcions: H(s) = V 2(s) V 1 (s) where V 2 (s) and V 1 (s) are he Laplace ransforms of v 2 () and v 1 (). To examine phase signals, le us assume ha, v 1 () = V 10 sin[ ()] and v 2 () = V 20 sin[ ()] For phase signals, he informaion is carried only in (). Nex, we consider some simple phase signals ha are used o excie a PLL.

20 Lecure 01 (8/9/18) Page 1-20 Phase s Coninued 1.) A sep phase shif which is an example of phase modulaion. 1 () = u() DF v 1 () q 1 () ) A sep frequency change assuming ha 1 () = o for < 0. We may express v 1 () as, v 1 () = V 10 sin[ o + ] 1 () = = V 10 sin[ o + 1 ()] (he phase becomes a ramp signal) v 1 () w 1 () Dw q 1 () Dw

21 Lecure 01 (8/9/18) Page 1-21 Phase s Coninued 3.) Frequency ramp 1 () = o + v 1 () where is he rae of change of he angular frequency. v 1 () = V 10 sin ( o + )d 0 = V 10 sin o w o w 1 () q 1 () Slope = Dẇ 1 () =

22 Lecure 01 (8/9/18) Page 1-22 LPLL blocks are: SUMMARY 1.) Muliplying phase deecor 2.) Low pass filer 3.) Volage conrolled oscillaor Locked sae: Inpu frequency = VCO frequency The phase response is low pass The phase error response is high pass