The Delay-Locked Loop

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A Circui for All Seasons Behzad Razavi The Delay-Locked Loop Delay-locked loops (DLLs) can be considered as feedback circuis ha phase lock an oupu o an inpu wihou he use of an oscillaor.

This aricle deals wih fundamenal DLL design conceps. The origins of DLLs can be raced o a paper published in 1961 [1].

1 A Circui for All Seasons Behzad Razavi The Delay-Locked Loop Delay-locked loops (DLLs) can be considered as feedback circuis ha phase lock an oupu o an inpu wihou he use of an oscillaor. In some applicaions, DLLs are necessary or preferable over phase-locked loops (PLLs), wih heir advanages including lower sensiiviy o supply noise and lower phase noise. This aricle deals wih fundamenal DLL design conceps. The origins of DLLs can be raced o a paper published in 1961 [1]. The auhors presen he opology shown in Figure 1 as a delay-lock discriminaor operaing on random signals. The feedback loop consiss of a conrolled delay line, a muliplier acing as a phase deecor (PD), and a lowpass filer. The use of DLLs in modern CMOS design evidenly began wih he work by Bazes in 1985 [2] and Johnson and Hudson in 1988 [3]. Basic Idea Suppose, as shown in Figure 2, an inpu clock ravels on a long inerconnec, experiencing a significan skew, D T. How do we align CKou wih CKin? Since he clock is periodic, we surmise ha an addiional delay can be inroduced o make he oal delay equal o one clock cycle [Figure 2]. To se he delay properly, we can view D T as an error ha mus be suppressed by means of negaive feedback. Tha is, if he phase of CKou is compared o ha of CKin, he resuling error can be used Digial Objec Idenifier /MSSC Dae of publicaion: 13 Augus 2018 o adjus he delay and force D T oward zero. This conjecure leads us o he arrangemen depiced in Figure 2(c). Here, a phase deecor measures he skew and adjuss he delay of B2 o reduce D T. A s wih PLLs, he low-pass filer aenuaes he high-frequency componens generaed by he PD. This circui exemplifies a simple delay-locked loop. The residual phase error in Figure 2(c) depends on he loop gain, i.e., he gain of he PD, KPD, and he gain of he variable-delay sage. The laer is defined as KDL = 2z/ 2con, where z is he sage s delay in ra di ans. Raher han aemp o maximize KPDKDL, we can add an inegraor o he loop. Drawing upon our knowledge of PLLs, we hus consruc he archiecure shown in Figure 2(d), where he cascade consising Received Waveform As [ T()] n() Reference ks () ks [ T()] Differeniae Figure 1: An early DLL repored in [1]. The origins of DLLs can be raced o a paper published in of he phase/frequency deecor (), charge pump (), and capacior provides an infinie gain, hus driving he skew oward zero. The variable-delay sage is realized as a volageconrolled delay line (CDL). Figure 2(e) shows an example of CDL design employing varacors for delay conrol. While he DLL does no require frequency deecion, he provides a convenien inerface wih he. As explained nex, no resisor is necessary in series wih C1. This DLL archiecure is commonly used in highspeed sysems. The DLL of Figure 2(d) is of firs order, facing no sabiliy issues. Moreover, i benefis from he lower phase noise and supply sensiiviy of delay lines compared o oscillaors. In conras o PLLs, delay-locked loops do no generae a frequency; Muliplier x() Low-Pass Filer F (p) Delay Conrol Conrolled Delay Line Gain g d = 1/α sec/ol ks () Delay Esimae at() " IEEE SOLID-STATE CIRCUITS MAGAZINE summer

2 T CK Long Inerconnec B 1 B 2 T ariable Delay Sage B 1 B 2 T CK CDL B 1 B 2 B 1 B 2 PD (c) (d) (e) Figure 2: An inerconnec wih skew, he correcion of skew by a delay sage, (c) a simple feedback sysem for conrolling he delay line, (d) a basic DLL, and (e) a CDL implemenaion example. raher, hey simply delay he inpu. As such, DLLs are less versaile han PLLs. For example, in pracice, a DLL would no be able o generae a 5-GHz clock from a 20-MHz reference. Anoher drawback of DLLs is ha hey allow he inpu duy cycle error o propagae o he oupu. In fac, he delay line may furher increase his error. Thus, he CDL is ypically preceded or followed by a duy cycle correcion sage. A hird drawback of DLLs is ha hey operae he and he a high speeds. The dynamic behavior of DLLs deermines how hey respond o such effecs as inpu phase noise, and supply noise. We herefore sudy his behavior in he nex secion. Loop Dynamics We wish o analyze he dynamic be - havior of he DLL shown in Figure 3. In he locked sae, he phase difference beween CKin and CKou is consan and, in principle, equal o zero. Thus, he CDL provides a delay of one clock period, TCK. Before delving ino he overall loop dynamics, le us undersand hose of he CDL iself. The circui has a clock inpu and a conrol inpu. Wha happens if CKin in Figure 2(e) incurs a phase sep? This sep propagaes hrough he chain and emerges a he oupu TCK seconds laer [Figure 3]. Tha is, he ransfer funcion associaed wih his pah can be expressed as exp( - TCKs). In pracice, TCK is much less han he overall DLL ime consan, allowing he approximaion exp( -TCK s). 1. How abou he pah from con o CKou? If we apply a sep a con in Figure 2(e), how long does i ake o affec he oupu phase? From he waveforms shown in Figure 3(c), we recognize ha his pah oo has a delay of a mos one TCK. Based on hese observaions, we can consruc an approximae, saic model for he CDL; as shown in Figure 3(d), i simply adds a phase equal o KDL con o he inpu phase. (The one-cycle delay is negleced here.) I is insrucive o firs examine he overall DLL s response qualiaively. If he phase of CKin in Figure 3 flucuaes slowly, he DLL mainains a high loop gain, keeping 10 summer 2018 IEEE SOLID-STATE CIRCUITS MAGAZINE

3 T CK CDL Inpu Phase Sep CDL = K DL (c) (d) Figure 3: A DLL wih a CDL, he propagaion of inpu phase sep o oupu, (c) he propagaion of sep on con o oupu, and (d) a linear model of a CDL. CKou aligned wih CKin. Tha is, he closed-loop ransfer funcion has a uniy magniude for slow phase variaions. Now suppose CKin experiences very fas phase changes. Then, he DLL has lile loop gain, con does no change, and CKin simply propagaes o CKou. In his case, oo, he closed-loop response is around uniy because he inpu phase changes appear a he oupu wih only a delay of TCK seconds. We hus conclude ha DLLs exhibi an all-pass response, a poin of conras o he low-pass behavior of PLLs. The all-pass naure of DLLs can also be confirmed mahemaically. For he DLL of Figure 3, we draw he phase model as shown in Figure 4, noing ha con is given by ( zin - zou)[ Ip/( )], where Ipdenoes he charge pump curren, and hence Ip zin ( zin - zou) KDL = zou. (1) Tha is, KDLIp -( zin - zou) = ( zin- zou), (2) which implies zin = zou. In pracice, he response exhibis a small amoun of peaking [Figure 4] [4]. We should remark ha some DLLs apply an independen reference clock o he and do no follow hese dynamics [4]. The aforemenioned sudy reveals wo poins: 1) DLLs do no generally face sabiliy issues and can operae wih a wide range of values for Ip and C1, and 2) he lack of filering abiliy precludes he use of he foregoing DLLs in applicaions where he inpu jier mus be removed. The laer issue is resolved by a differen DLL archiecure [4]. I p c 1 s K DL Figure 4: A linear model of DLL and he DLL phase response. ω Effec of Supply Noise The principal effec of supply noise, DD (), in DLLs is o modulae he delay of he CDL. How does he DLL of Figure 3 respond o DD ()? If he noise varies slowly, he loop has enough srengh o keep z ou close o z in, i.e., con opposes DD () and z ou = 0 DD K DD I p K DL c 1 I p c 1 s K DD K DL DD ω Figure 5: The supply noise in a DLL and he DLL phase response. IEEE SOLID-STATE CIRCUITS MAGAZINE summer

4 is no affeced. For high-frequency noise, on he oher hand, he loop gain drops, and z ou is direcly modulaed by DD. Le us define for he CDL a gain from DD o z ou as KDD= 2zou/ 2DD. Shown in Figure 5 is he DLL model wih supply noise and z in = 0. Beginning from he oupu, we can wrie con as - zou[ Ip/( )] and hence Ip - zou KDL DDKDD = zou. (3) I follows ha Sφ,ring Sφ,DL Phase Locked Oscillaor f 0 f 0 f f Figure 6: The comparison of ring oscillaor phase noise and delay line phase noise. z ou KDD () s =. I K DD p DL (4) Ploed in Figure 5, he response begins o flaen ou beyond he pole frequency, ~ p = IpKDL/ C1. We mus herefore choose a high value for ~ p so as o maximize he supply rejecion. Effec of Phase Noise DLLs are generally considered o generae much less phase noise han PLLs, bu he comparison mus be done carefully. We begin wih he inpu phase noise. As exemplified by he ransfer funcion ploed in Figure 4, his noise experiences no aenuaion and simply propagaes o he oupu. The case of he CDL phase noise is more ineresing. We make wo observaions. Firs, as shown in [5], he phase noise of a delay line, S z,dl, and ha of a ring oscillaor using such a line, S z,ring, are relaed as follows: 2 f0 Sz, ring( f) = Sz, DL c m, (5) rdf where f0 is he oscillaion frequency (Figure 6). We conclude ha he ring produces much higher phase noise. One inerpreaion of his resul is ha, in a ring, an edge coninues o accumulae phase noise as i circulaes, whereas, in a delay line, an edge experiences he phase noise of he delay sages only once before i reaches he oupu [6]. Second, we model he CDL phase noise as shown in Figure 7 and wrie Ip - zou K DL zn, DL = zou, (6) obaining z z ou n, DL () s C1 = s. IpKDL (7) Similar o he effec of supply noise, his resul indicaes a firsorder high-pass behavior [Figure 7]. As expeced, he loop rejecs slow phase flucuaions caused by he CDL. In general, he dominan source of phase noise in CDLs is he sup p- ly noise. = 0 I p c 1 s K DL φ n,dl φ n,dl 1.0 I p K DL c 1 Figure 7: A DLL model including delay line phase noise and he DLL response. 0 T D 2 Figure 8: A DLL generaing muliple phases. N N 1 ω 0 = N Generaion of Muliple Phases In addiion o he deskewing funcion illusraed in Figure 2(d), DLLs also find applicaion in sysems re - quiring muliple clock phases. For example, some clock and daa recovery circuis demand 32 or 64 equally spaced clock phases, a difficul siuaion for ring oscillaors as heir operaion frequency is inversely pro - porional o he number of sages ha hey employ. Figure 8 depics a DLL ha delivers muliple clock phases. Incorporaing N nominally idenical delay sages, he CDL provides N phases wih a minimum spacing equal o he delay of one sage, TD. The key poin here is ha TD = TCK/ N because he loop locks such ha CKou and CKin have a phase difference of TCK. In oher words, by virue of he feedback around he loop, TD remains well defined and relaively precise even wih process, volage, and emperaure (PT) variaions. By comparison, a free-running delay line can 12 summer 2018 IEEE SOLID-STATE CIRCUITS MAGAZINE

5 CDL Inv N1 Inv N N2 N1 N Inv a a Inv b b Figure 9: The DLL of Figure 8 wih oupu inverers added and uniform fanous a all CDL aps. experience a nearly wofold change in is delay as a funcion of PT. The muliphase DLL shown in Figure 8 faces several issues. Firs, due o unequal loading, he phase spacings a he boundaries of he CDL can be differen from hose in he middle. To undersand his poin, consider he siuaion illusraed in Figure 9, where inverers InvN - 1 and InvN see differen fanous; he former drives wo inverers bu he laer, an inverer and a. As a resul, he phase difference beween N - 2 and N 1 - is no he same as ha N This issue beween N - 1 and. is overcome as shown in Figure 9, wih wo inverers insered a he inpus. Assuming all of he inverers are idenical, we observe ha 1) he fanou a 4 is equal o ha a 1, 2, and 3, and 2) he loop drives he phase difference beween a and b o zero, hus aligning 0 and 4 as well. One assumpion here is ha he waveform arriving a 0 has approximaely he same rise and fall imes as ha a 4 ; oherwise, he delays hrough Inva and Invb are slighly differen. Anoher issue in he DLL of Figure 8 is he problem of false lock. Assume he circui is designed o provide a oal delay of TCK a he ypical-ypical (TT), 27 c C corner. Now, suppose he DLL operaes in he slow-slow (SS), high-emperaure corner, and, upon sarup, he oal CDL delay is slighly greaer han 2TCK (Figure 10). Then, he DLL simply aemps o align 0 and N, and i can do so if he phase difference beween hese wo signals reaches 2TCK raher han TCK. As a resul, he phase spacings will be equal o 2TCK / N. Avoiding false lock generally re quires subsanial added complexiy, especially if he DLL mus operae across a wide frequency range. Depiced in Figure 11 is a soluion employing a PLL. A replica of he CDL is configured as a ring oscillaor and phase locked o he main inpu, hus guaraneeing ha he delay from A o B is equal o TCK and hence con1 reaches he desired value. Now, his volage serves as he coarse conrol for he main CDL, allowing he DLL o provide only a fine adjusmen hrough fine. For example, if he wo CDLs have a delay mismach of 10%, hen fine mus vary he delay by only CDL fine his amoun, hereby avoiding false lock. The filer preceding co arse suppresses he ripple and noise presen in con1. This archiecure approximaely doubles he area and power consumpion. Anoher mehod is described nex. Sar Up Condiion 2T CK ε N Afer Lock 0 N 2T CK 2T CK Figure 10: The problem of false lock. coarse Figure 11: The addiion of a PLL o a DLL o avoid false lock. A 1 Replica CDL PLL B IEEE SOLID-STATE CIRCUITS MAGAZINE summer

6 X Y 2 a b c d a 3 4 b X Figure 12: An edge-combining circui for frequency muliplicaion and is waveforms. 2 (= 6 ) The hird issue in he muliphase DLL of Figure 8 relaes o he mismaches beween he delay unis, which ranslae o deparures in he phase spacings from TCK / N. Presen in boh he driving srengh of he sages and heir load capaciances, he mismaches mus be managed by proper sizing, careful layou, and Mone Carlo simulaions Figure 13: The use of AND and OR operaions for frequency muliplicaion and he logical implemenaion. Edge Combiner 9 4 f in f in f mul N Figure 14: A false lock deecor using a frequency muliplier. ou False Lock Flag Frequency-Muliplying DLLs An imporan shorcoming of DLLs is heir inabiliy o perform fre - quen cy synhesis, i.e., generae ar - birary oupu frequencies. In some applicaions, a DLL can muliply he inpu frequency by an ineger, hereby acing as a poor man s frequency synhesizer. Recall ha he DLL of Figure 8 produces N equally spaced clock edges wih a resoluion of TCK / N seconds. If we combine hese edges, we can generae an oupu having a higher frequency. Shown in Figure 12 is an eigh-phase delay line, wih is oupus applied o XOR gaes. Noing ha he DLL aligns 8 and 0, we observe a phase difference of 45c beween adjacen aps. As illusraed in Figure 12, he XOR resul of 1 and 2 exhibis pulses every TCK / 2 seconds and so does he XOR resul of 3 and 4. Since a and b have a phase difference of 90c, heir XOR resul, X, has a period of TCK / 4 seconds. From anoher perspecive, he firs rank of XOR gaes doubles he frequency, and he second rank doubles again. The eigh-sage DLL hus muliplies he inpu frequency by a facor of four. Noe ha he XORs inroduce uniform loading along he delay line (if he XOR gaes are symmeric wih respec o heir wo inpus). The XOR sages form an edge combiner here. I is possible o design an edge combiner using AND and OR gaes. The delay line shown in Figure 12 provides delayed signals and heir complemens. For ex ample, 5 = 1, 6 = 2, ec. If we AND 1 and 2, we obain one pulse of widh TCK / 8 every TCK seconds [Figure 13]. Similarly, 3 4 exhibis he same shape bu shifed by TCK / 4. I follows ha yields wo such pulses every TCK seconds. Noing ha has he same behavior 14 summer 2018 IEEE SOLID-STATE CIRCUITS MAGAZINE

7 R 2 R F R 2 in R 3 A B R 4 ou in C 2 R 3 x R 3 ou I C 2 R eq C 2 C 2 R 2 R F Figure 15: A noninvering inegraor. Figure 16: The TowThomas biquad. bu shif ed by TCK / 2, we conclude ha is a signal wih four imes he inpu frequency. The implemenaion is shown in Figure 13. In realiy, he AND and OR gaes are replaced by NANDs. The muliplicaion facor in Figures 12 and 13 is difficul o change, a poin of conras o PLLs. Moreover, delay mismaches among he sages give rise o jier and spurs. The frequency muliplicaion abiliy of DLLs can be exploied o deec false locking. Consider he archiecure shown in Figure 14, where an edge combiner muliplies he frequency by a facor of N. This resul, fmul, is hen divided by N and compared o fin. Wih correc locking, fmul = Nfin, leading o a low average value for he oupu. In he presence of false lock, on he oher hand, he oal delay from CKin o CKou is equal o or greaer han 2TCK, and fmul < Nfin. As a resul, he oupu exhibis a higher average. The false lock flag can hen be used o adjus he uning range of he delay line so ha he oal delay remains less han 2TCK. Quesions for he Reader 1) Suppose he up and down currens in he charge pump of Figure 2(d) have a mismach of DI. How does he DLL reac o his mismach? 2) The imperfecions in Figure 2(d) creae a periodic ripple in con. Wha is he effec of his ripple on he oupu waveform? Answers o Las Issue s Quesions 1) Figure 15 shows a noninvering inegraor. Derive he condiion for he elemens so ha he circui acs as an ideal inegraor. Wha is he principal difficuly wih his opology? We have B. A = our1/ ( R1 R2). Also, ( in- B)/ R3 ( ou - B)/ R4 = BC2s. Thus, R in R1C2 = s ou R R R1 ou c R1 R2 R R $ R3R m. R (8) 4 For ideal inegraion, he second erm on he righ-hand side mus vanish, yielding R2/ R1 = R4/ R3. Anoher perspecive provides addiional insigh. If ou is proporional o he inegral of in, hen so are A and B. T hus, IC2 = C2dB/ d is also proporional o in, a condiion ha is me only if he Noron equivalen of he circui in he dashed box reduces o an ideal curren source. Since he Noron resisance is given by R3 Req, we se Req o - R3 and hence obain R2/ R1 = R4/ R3. The principal issue here is ha he circui relies on equal posiive and negaive feedback facors and is prone o lach up in he presence of componen mismaches. 2) Suppose he TowThomas biquad of Figure 16 senses a large, narrowband undesired channel a ~ = ~ - 3dB. Which of he wo inegraors produces greaer volage swings and hence experiences more nonlineariy? We have ou / X =- 1/( R3C2s). The relaive swings in he wo inegraor oupus depend on he componen values. For ex ample, if C1 = C2, R2 = R3 = RF, and Q = 1, hen ~ n = 1/( R3C2) and ~ - 3dB = 127. ~ n = 1. 27/( R3C2). Tha is, ou / X = 1/ In his case, he firs inegraor compresses firs. If he undesired channel occurs a 2~- 3dB, we have ou / X = 1/ 2. 54, observing even a greaer swing dispariy. References [1] J. J. Spilker and D. T. Magill, The delaylock discriminaor: An opimum racking device, Proc. IEEE, vol. 49, pp , Sep [2] M. Bazes, A novel precision MOS synchronous delay line, IEEE J. Solid-Sae Circuis, vol. 20, pp , Dec [3] M. G. Johnson and E. I. Hudson, A variable delay line PLL for U-coprocessor synchronizaion, IEEE J. Solid-Sae Circuis, vol. 23, pp , Oc [4] M. J. E. Lee, W. J. Dally, T. Greer, H. T. Ng, R. Farjad-Rad, J. Poulon, and R. Senhinahan, Jier ransfer characerisics of delay-locked loops: Theories and design echniques, IEEE J. Solid-Sae Circuis, vol. 38, pp , Apr [5] A. Homayoun and B. Razavi, Relaion beween delay line phase noise and ring oscillaor phase noise, IEEE J. Solid-Sae Circuis, vol. 49, pp , Feb [6] J. Sonnag and R. Leonowich, A monolihic CMOS 10 MHz DPLL for burs-mode daa reiming, in Proc. In. Solid-Sae Circuis Conf. Dig. Tech. Papers, Feb. 1990, pp IEEE SOLID-STATE CIRCUITS MAGAZINE summer

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P. Bruschi: Project guidelines PSM Project guidelines. Projec guidelines. 1. Rules for he execuion of he projecs Projecs are opional. Their aim is o improve he sudens knowledge of he basic full-cusom design flow. The final score of he exam is no affeced by