Synchronization of the bit-clock in the receiver
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1 Synchronizaion of he bi-clock in he receiver Necessiy - he recovery and synchronizaion of he local bi-clock in he receiver is required for wo reasons: he sampling of he coded received signal should be performed wih a clock synchronized o i; he decoding of he received encoded sequence also requires a clock signal synchronized wih he encoded signal - he decoding of he biphasic, Miller and CMI codes, which have he minimum duraion of he level of he coded signal of a half bi-period, requires a local clock wih f local = 2 f bi. - in hese cases, he bi clock is obained by a frequency division of he local clock(f local ). Bu his division migh inser an 180º uncerainy beween he local clock and he coded signal, due o he iniial condiion of he divider; his uncerainy should be removed. - he decoding of he AMI code and is varians require a clock wih f local = f bi ; - he phase shif beween he received encoded signal, and he local xck has he following causes: he differen saring momens of he wo oscillaors; his generaes he iniial phase shif φ 0 which akes a random value beween 0º and 180º; he difference beween he frequencies of he wo pilo oscillaors ha deliver he wo clock signals; i generaes a dynamic phase shif which varies according o: φ d ()=Δω ; (1) he disorions insered by he channel he 180º uncerainy induced by he iniial sae of digial frequency dividers - he phase difference beween he wo oscillaors varies in ime acc. o: () d () 0 channel (2) - by synchronizaion beween he locally generaed clock and he received coded signal, we mean he synchronism beween he ransiions of he coded signal, considered as a phase reference, and he negaive ransiions of he locally generaed clock f local, whose frequency equals f bi or 2 f bi depending on he code. - he synchronizaion is accomplished in 3 seps: he removal of he iniial phase shif φ 0, named fas or coarse synchronizaion; his operaion is performed only once a he beginning of he ransmission; he removal of he 180º uncerainy, called resynchronizaion; his is required only by he decoding of he Miller code. The decoding of he oher codes presened does no require his operaion; he removal of he dynamic phase shif φ d + φ channel (caused by he frequency diff. and by channel phase his) beween he received coded signal and he locally generaed clock, called dynamic synchronizaion. I operaes during he whole ransmission, afer he oher wo seps have been performed. If he fas synchro is missing, he removal of he iniial phase shif is also performed by he dynamic synchro. he dynamic and fas (when used) synchros are accomplished by means of Phase-Lock Loops (PLL). PLL. General Aspecs i is an ensemble of circuis ha provides a local signal whose phase is aligned o he phase of an incomming reference signal. Is block diagram is shown in figure 1. s i () s o () Phase Deecor s φ () Volage Conrolled Oscillaor (VCO) Loop Filer v φ () Figure 1. Block diagram of a PLL - he phase deecor (comparaor) (PhD(C)) oupus a error-volage signal whose ampliude is (ideally) proporional o he phase difference beween he incoming (reference) signal s i () and he locally generaed s o (). - he loop filer (LF) is a low-pass filer which reains only he low-frequency componens of he error-volage, e.g. aenuaes he high-frequency componens of he noise, and generaes a conrol volage which modifies dynamically he momenary frequency of he locally generaed signal o decrease he phase offse beween he s i () and s o (). - ideally, his process coninues unil he phase offse reaches zero, which corresponds o a consan value of he error-volage (usually his consan value equals zero) - in many of he pracical implemenaions, he momenary frequency of he VCO is adjused in order o decrease and bring owards zero (or below an imposed value), he error-volage and, equivalenly, he phase offse beween he reference (inpu) signal and he locally-generaed (oupu) signal. - if he error-volage equals zero, he frequency of he signal provided by rhe VCO is denoed as freerunning frequency f OL. 1
2 Types of PLLs analogue or linear loops (APLL or LPLL) o he phase deecor is implemened wih analogue circuis (e.g. analogue muliplier), he loop filer migh be an acive or passive analogue filer. This ype of PLL uses a VCO. digial loops (DPLL) o is acually an analogue PLL ha has he PhC implemened wih digial circuis (gaes, JK flop-flops, ec.). I migh include a digial frequency divider and can be used as a frequency muliplier. all digial loops (ADPLL) o all blocks in he loop are implemened wih digial circuis, and he VCO migh be replaced by a conrolled divider. sofware PLL (SPLL) o i is implemened using programable circuis Descripions and Funcionaliies of he componen blocks Phase Deecor- PhD - i oupus an error signal s φ () which varies wih he offse i o beween he momenary phases of he inpu (reference) signal s i () ( i - he phase of he reference signal) and of he oupu (locally generaed) signal s o () ( o - he phase of he local signal). - he PhD can be implemened wih analogue or digial circuis. - according o he dependency-law beween he error-volage and he phase-offse i o, he PhC could be divided in one of he following ypes, see figure 2: PhD wih linear dependency (or sawooh) o usually hese comparaors are implemened wih digial circuis, while he impu signals are recangular ones. These circuis are also named Phase-Frequency Deecors (PFD). PhD wih sinusoidal dependency o hese PhD are implemened wih analogue circuis, e.g. analogue mulipliers, and he inpu signals are harmonic, e.g. sine or cosine signals. o i provides an oupu sinchonized signal which has a phase offse of π/2, wih respec o he inpu reference signal. The error volage provided by his PhD is expressed by: A sin( i) cos( o) A sin( i) cos( i ()) U sin( ()) sin(2i ()) (3) sφ PhD wih riangular dependency Sawooh o implemened wih digial circuis and he Sinusoidal inpu signals are recangular sgn PhD wih signum (sgn) dependency o provides only he phase offse s sign; i is implemened wih digial circuis, while he Triangular Φ e - Φ o inpu signals migh be eiher analogue or digial. Figure 2 Types of dependencies of he Phase Deecor Volage Conrolled Oscillaor -VCO - i is an oscilaor generaing a (co)sinusoidal (or recangular) waveform whose frequency deviaion from he he free-running frequency (f OL ) is proporional o he error-volage V φ (). - If he error-volage equals zero, he frequency of he generaed waveform equals f OL. - So he oupu volage is expressed as, see he FM lecures: o 0 OL VCO s() Vcos2f K v()d (4) Loop Filer - LP i usually is a LP filer, which affecs he dynamics and sabiliy of he loop, because is ransfer funcion affecs he behaviour of he loop a he frequency variaions of he inpu signal. In he same ime, he characyerisic of his filer affecs he widhs of he lock-in and hold-in ranges (see below) and he lock-in (synchronizaion) ime. 2
3 f o f OL Lock-In ange i is he frequency range (band) of he inpu reference signal wihin which he PLL is able o modify he frequency of he local signal so ha is phase would be equal o he phase of he incoming reference signal, see figure 3. - his rule applies for he case when he local signal is no iniially synchronized o he incoming one. Figure 3. Frequency variaion of he local signal vs. he frequency of he reference signal f OL f i Hold-in ange i is he frequency range of he inpu signal wihin which he frequency of he locally generaed signal, afer i has been synchronized o he reference signal, can be modified so ha is phase would follow he phase of he reference signal, i.e. he phase offse beween he wo signals would end o zero, see fig. 3. Lock-in (Synchronizaion) Time i is he ime inerval required by he PLL o capure hen phase of he incoming signal, i.e. o make he phase of he local signal equal o he phase of he reference (incoming) signal. Dynamic Synchronizaion - i is an ADPLL - due o he (1) perfec phase synchronizaion beween he local clock and he ransiions of he received code signal is pracically impossible. - he aim of he dynamic synchro is o keep Delay x x x Syncro x x sep 2x dynam ic Equilibrium zone Figure 4. Dynamic equilibrium zone Coded received signal N f si ncro Phase Compa raor Lock-in range Hold-in range Circ. Adv. cd Circ. Delay cd J Ck K Q eceived coded signal eference Advance Local Syncro Clock F ro m he b lo ck in g oupu of he fas syncro Divider by N/2 Figure 5. Block diagram of he dynamic synchro circui f sin cr o - lo cal he modulus of he phase shif (offse) beween he wo signals below an a priori esablished value, called synchronizaion sep. - he considered ransiions of he wo signal are aligned only a random momens; he ransiions of he local clock are eiher ahead or behind he ransiions of he coded signal, which is he reference signal, bu he modulus of he phase offse would always be smaller han he prese value x. - he phase-widh of he dynamic equilibrium is 2x, see figure 4. - he block diagram of he dynamic synchro circui is shown in figure 5 - he phase comparaor senses he relaive posiion beween he ransiions of he CS (received coded signal) and he negaive ransiions of local clock; i generaes a command so ha a conrolled phase shif, in advance or delay, is accomplished. - if he local clock is delayed, compared o he reference CS, he CP will acivae he Advance-clock circui which will ac upon he firs cell in dividing chain, by insering addiional ransiions which will shif he local clock in advance. - if he local clock is in advance, compared o he ref. CS, he CP acivaes he Delay-clock circui which acs upon he firs cell in dividing chain, by deleing ransiions, hus shifing he local clock behind. - he CP conrols only he sign (sense) in which he local clock is phase-shifed; i does no conrol he phase shif s modulus insered a every correcion. - he phase of he local clock signal is modified by emporarily modifying he dividing facor of he highfrequency f aack clock; his is named phase-shif by conrolled frequency division mehod. - he CP would always indicae he phase-shif from he closes ransiion of he reference signal; herefore he modulus of he maximum possible phase-shif will be 180º. - for decoding AMI, BnZs, HDB3, 4B3T, MLT-3 and b4b5 codes, = f bi, - for decoding biphasic, Miller, CMI, = 2f bi. - as an example of he phase shif by conrolled division, we describe a dynamic synchro ha synchronizes a local clock, employing a divider clock wih a frequency f aack = 2 n = 32 f synchro. 3
4 s.c.r. The momen when he delay-circui acs Def. în avans Advance phase-shif; Def. în înârziere delay phase shif U în -JK Tac în avans - s.c.r. Clock advanced - CS Figure 6. The delay phase-shif of he local clock by conrolled division Tac înârzia - s.c.r. Clock delayed - CS s.c.r. The momen when he advance- circui acs Delay phase-shif Def. in inirziere; Def. în avans- Advance phase shif U avans - Tac înârzia faţă de s.c.r. Tac în avans - s.c.r. Delayed clock - CS Advanced clock - CS Figure 7. The advance phase-shif of he local clock by conrolled division - Fig. 6 shows he case when he f synchro is advanced, compared o ref. signal, and has o be delayed; - he CP acs upon he J-K inpus of he firs cell of he dividing chain, inhibiing he flip-flop during one acive clock ransiion. So, a ransiion of is oupu signal is suppressed, and he ransiions of he f synchro signal are delayed wih one period of he f aack signal. - he dashed lines indicae he saes of he circui afer he delay circui akes is acion. - Fig. 7 presens he case when he f synchro is delayed, compared o ref. signal, and has o be advanced - he CP acs upon he ese (or Se if anoher configuraion is employed for he divider) inpu of he firs cell of he dividing chain. 4
5 - If he ese is acivaed when he invered Q is in 0, an addiional ransiion is insered in he signal a oupu of his cell, generaing he advance in phase of f synchro wih a period of he f aack signal. - generalizing, an addiional ransiion is insered in he signal a he oupu of his cell if we acivae he ese when he invered Q is in 0, or if we acivae he Se when he Q oupu is in 0. - he dashed lines indicae he saes of he circui afer he advance circui akes is acion. - in boh cases he advance or delay circui operaes only once during he period of he f synchro signal. - he dynamic synchro can ac only if here are ransiions in CS; oherwise he dynamic synchro has no phase-reference (ransiion of he CS) and will eiher keep he phase-shifing sense esablished a he las phase comparison performed, or would ake no acion unil a ransiion of he CS occurs. - his fac shows he necessiy of a number, as grea as possible, of ransiions in he CS. - he phase sep wih which he correcion is performed, corresponds o a period of he f aack signal, boh for he delay and advance correcion. - expressed in degrees his equals (30) where n is he number of cells of he dividing chain: n p ; N 2 ; (5) faack N n 2 fsin cro - he phase ampliude of his sep can be modified by changing he number of cells of dividing chain and by changing, correspondingly, he f aack frequency o mainain he value of he frequency of he signal ha has o be synchronized, f synchro. -his dynamic synchronizaion circui migh be regarded as a ADPLL of order 0. Is lock-in range equals is hold-in range and is widh is given in (6).a. - is lock-in ime is expressed by (6).b, where m denoes he average ime inerval beween wo consecuive ransiions of he inpu reference signal (i.e. he duraion of a synchronizaion sep), while ΔΦ max denoes he maximum iniial phase offse ha has o be compensaed; if no fas synchro is used, ΔΦ max = 180º. f aac faac max BWLK BWHD ; ;. ;. 1 1 a s m b (6) N N p - ΔΦ max can be reduced by using he fas (coarse) synchronizaion circui, see he nex paragraph - his PLL does no reach a saic equilibrium, bu since he he modulus of he phase offse is smaller han an imposed arbirarily small value ΔΦ p, i can be considered o ensure a dynamic equilibrium. - anoher version of he dynamic synchro circui ha allows a phase-sep ΔΦ p = 360 º/N, wih N a naural number is presened in Annex 1 of his maerial and will be discussed in he laboraory classes. - his ype of synchronizaion circui is also employed by oher classes of modems o synchronize he symbol and he bi clocks. Fas (Coarse) Synchronizaion - he block diagram of he fas synchro circui is shown in figure 8, and is principle of operaion is described in figure 9. - he fas synchro operaes in hree seps: The iniial synchronizaion ha is performed only once a he beginning of he recepion of a message; The disabling of he fas synchro circui during he recepion, so ha he dynamic synchro would no be affeced; The re-enabling of he fas synchro circui a he end of he recepion of a message, so ha i should be able o ac a he beginning of recepion of he nex message. - a he beginning of he sep, he sensor of he firs ransiion is assumed o be acivaed, blocking, by he acivaion of he Q oupu of he 16-couner, he generaion of he local clock f synchro. - when he firs ransiion of he CS occurs, he ransiion sensor gives a pulse which reses he 16-couner, Q = 0, which releases he rese of he dividing chain of he dynamic synchro, hus allowing he generaion of he local clock f synchro = 2f bi. - assuming ha he divide wih N sars o coun a he arrival of he firs ransiion of he CS and ha he ime inerval beween wo ransiions of he CS is approximaely equal wih he period of f synchro, we see ha he firs negaive ransiion of he local clock will be coinciden wih he nex ransiion of he CS. This indicaes he removal of he iniial phase-shif. - Bu he N-couner (from he dynamic synchro) would acually sar couning only a he occurrence of he firs negaive ransiion of he f aack = N, i.e. wih a maximum delay of a period of he f aack signal. 5
6 eceived Coded sig nal N Sensor of he firs ran siion Sensor of ra nsiions Couner wih 16 Q C k Ck :N Ck :2 Q D ynamic synchro circui Figure 8 Block diagram of he fas synchro circui eceived Coded Signal- CS N ; N = 16 N ; N = 16 acive inacive ese elease ese Divider N ΔΦ = 360º/N Sar couning Iniial phase-shif Afer Fas-synchro Figure 9. Operaing principle of he fas synchro circui This fac makes he negaive ransiion of he f synchro o occur wih a delay of maximum ΔΦ max, compared o he arriving momen of he second ransiion of he CS, see fig. 19 and (7): N=2 n ; ΔΦ max =360º /(N )=360º/2 n ; (7) - (7) holds valid when all he cells of he N- couner are rese by he oupu of he 16- couner of he fas synchro. - if he fas synchro opeares only upon he firs m sages from he opu of he 2 n -divider, hen he maximum iniial phase-shif would be: ΔΦ imax =360º/2 m ; (8) - noe ha, if m = n, during a period of he f synchro signal, he fas synchro circui decreases he iniial phase o he value of he phase-sep of he dynamic synchro, bringing he sysem in he dynamic equilibrium zone, from where he synchronizaion is aken over by he dynamic synchro circui; if m < n, he iniial phase-shif is decreased o he value provided by (7) - once he iniial phase shif is removed, he fas synchro circui should be disabled during he res of he recepion, o allow he dynamic synchro o compensae he dynamic phase shif and he phase-shifs insered by he ransmission channel - he disabling of he fas synchro circui during he recepion, employs he fac ha he maximum ime inerval beween wo consecuive ransiions of he CS is 2-bi periods, or 4 periods of he f synchro signal. So, he 16-couner from he fas synchro circui is rese by he ransiion sensor, afer wo bi periods and is i is no able o reach he 1 value, which would disable he N-couner of he dynamic synchro circui. This accomplishes he second sep of he fas synchro operaion. - a he end of recepion, for 8 bi periods, he 16-couner is no longer rese, here are no ransiions since here is no CS; is oupu will jump o 1, reseing he N-couner of he dynamic synchro and so he fas synchro circui is re-armed fulfilling he hird sep of operaion of he fas synchro. esynchronizaion - as menioned earlier, he resynchronizaion is inended o remove he uncerainy of 180º which migh occur beween he bi-clock a he ransmission end and he bi-clock a he receiving end. - i is performed only once a he beggining of he ransmission, afer he acion of he fas synchro circui; his synchronizaion is required by he Miller code. - he biphasic code does no require i, due o is differenial srucure. This propery makes i suiable for burs-ype ransmissions, as he ones in he local compuer neworks. This goes for he CMI code as well. f bi 6
7 Annex 1 Dynamic Synchronizaion Circui wih ΔΦ p =360 /N - he synchronizaion involves he alignmen of a locally-generaed clock of frequency f s, o he recovered symbol-clock, employed as phase reference in a synchronizaion sysem, performing he wo seps: iniial synchronizaion and dynamic synchronizaion. - some applicaions require specific values of he phase-sep of he dynamic synchronizaion circui. - as an example we consider he demodulaion of he PSK or A+PSK signals which impose wo conradicory requiremens on he dynamic synchronizaion: i should ensure he highes possible accuracy, which would involve a small value of he phase-sep ΔΦ p i should have a small ime response, or a high speed wih which he circui follows he phase of he received signal, in order o be efficien in acse of phase-his or clock slips; i would require a greaer value of he phase-sep. - in many cases he values of he phase sep provided by he dynamic synchro presened in he BB lecures, i.e. ΔΦ p =360 /2 n, do no saisfy he above requiremens - herefore he phase sep should ake values wih a finer granulariy, such as ΔΦ p =360 /N, wih N any naural number. - a dynamic synchro circui, buil wih an arihmeic-adder and a shif-regiser, which ensures such a phase sep is presened below - he paricular case presened below ensures a phase sep given by (A3.1) using f aack =1344f local and performing frequency division by 1343, o advance he local clock, and o 1345, o delay i: ΔΦ p =360 / ; (9) This varian is shown in figure A.1. In his circui f local is considered o be a symbol clock f s ; i also indicaes how a bi clock f bi = 3f s is also synchronized. f bi syn chronized : 4 : 4 : 2 f aack D B C A C k M od e. D. D i C i B i A i C.D. : 6 f s syn chronized f s recovered A 3 Σ 3 Σ 2 Σ 1 Σ 0 A 2 C 0 A 1 Σ A 0 C 4 B 3 B 2 B 1 B 0 1 Ph ase C om p. Division C on rol Figure A.1. Block diagram of he dynamic synchronizaion wih AA-S HOMEWOK: - Describe he operaing principle of he circui above. Hin: if he B i = 0 he adder+.d. circui divides by 16. The f aack = f s = 1344 f s = N 0 f s, bu he mehod employs he division of his frequency by N 1 = = 1345, or by N 2 = = 1343, o accomplish he delay or advance of he local clock. Compue he phase-sep for advancing and for delaying he synchronized clock, and show ha i is approximaely equal o ΔΦ p =360 /N. 7
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