PLL Hardware Design and Software Simulation using the 32-bit version of SystemView by ELANIX Stephen Kratzet, ELANIX, Inc.

Transcription

1 Applicaion Noe AN14A Apr 8, 1997 SysemView B Y E L A N I X PLL Hardware Design and Sofware Simulaion using he 32-bi version of SysemView by ELANIX Sephen Kraze, ELANIX, Inc. Inroducion This applicaion noe describes he design of a phased locked loop (PLL). The design begins wih a small breadboard o documen he volage conrolled oscillaor's (VCO) ransfer funcion, hen he componen values for he loop filer are calculaed. The design is hen verified by compleing he breadboard. Sofware simulaion of he breadboard is described using SysemView by ELANIX, and he resuls of he simulaion are compared wih he operaion of he breadboard. A brief descripion of his paricular phase locked loop (Figure 1) follows. The frequency oupu from he VCO is divided-by-4 and compared o an accurae and sable reference frequency. The oupu of he Phase/Frequency Deecor and Filer/Inegraor combinaion adjuss he VCO as necessary (up or down in frequency) o cause he R and V inpus o be a he same frequency and in phase wih each oher. Variaions of his loop include, a division facor oher han 4, an addiional divider a he oupu of he VCO, and/or a divider beween he Ref. Freq. and he R inpu. The digial phase/freq. deecor is by is naure a sampled funcion. Is oupu is no an analog coninuous signal. I can make a correcion only once each cycle of he reference inpu. One of he jobs of he filer is o reduce his sample frequency o an ampliude low enough o provide an accepable low jier VCO oupu, while a he same ime provide a loop response ime quick enough for he inended applicaion. (No shown in he block diagram, is he requiremen o shif he volage level of he VCO oupu o one accepable o he inpu of he couner.) Breadboarding he VCO Sar he design wih he mos consrained par, he VCO. Analog VCO's generally have a non-linear ransfer funcion, over a narrow oupu frequency span. The highes oupu frequency is abou 2 1/2 imes he lowes oupu frequency. The VCO used in his example is he Moorola MC1648P. Moorola's daa book has some useful example circuis along wih graphs of heir ransfer funcions (Ref. 1). The schemaic in Figure 2 shows he oscillaor ank circui is comprised of a pair of MV144 varacor diodes and a 2.4 uh inducor. The value of he inducor was seleced wih he help of a MICROMETALS caalog "Q CURVES for iron cores". The Q curves on page 21 indicae ha a MICROMETALS T 27-6 oroid has he following characerisics: Number of urns AWG Inducance Peak Q Freq. a peak Q uh MHz uh MHz Table 1. Parameers for a T27-6 Toroid. Because he desired cener frequency of he VCO was close o 12 MHz, he oroid was wound wih 3 urns of AWG 3 wire. (Fewer urns could have been used, also.) The inducance of a oroid is proporional o he number-of-urns squared. Therefore, (wih he oroid inducance olerances being +/- 5%): 32 2 urns 3 2 urns = 2.7 µh L herefore L = 2.4 µh AN14A Apr 8, 1997 Page 1 of 9

2 Figure 1. Phase Locked Loop block diagram Figure 2. Schemaic of he Phase Locked Loop circui breadboard. AN14A Apr 8, 1997 Page 2 of 9

3 Jus he MC1648P porion of he circui was measured on he breadboard. The VCO ransfer funcion is shown in Table 2 and Figure 3. Inpu Oupu values=2 volage freq. min=.5 (vols) (MHz) max= Table 2. Measured ransfer funcion of he VCO (MC1648P) breadboard. SysemView 5.e-3 3 O u 25 p 2 u 15 M H 1 z 5 5.e Table 3. Forma of he file "TF-FM.TXT" for he Xfer Fc oken. Scaer plo of 2 exernal sources: vco-mhz.x and vco-v.x VCO Inpu (Vols) File: v-mhz.svu Figure 3. Graph of he VCO ransfer funcion in Table 2. Types of Phase Deecors There are hree ypes of phase deecors (Ref. 2). 1. Analog or muliplier (mixer). 2. Exclusive-OR. (The digial equivalen of he analog muliplier). 3. Digial phase-frequency deecor (CD446 or MC444 ype). The main advanage of he analog phase deecor is is abiliy o recover a signal from a low signal-o-noise inpu. Unforunaely, i will also lock in on harmonics of he desired inpu. For he noise free TTL signals found in a frequency synhesizer, he hird ype of phase deecor is a beer choice. The MC444 responds only o he falling edges of he inpus, eliminaing he harmonics lock-in problem. The CD446 responds o he rising edges only. The digial phase deecor is no perfec, an exra or missing pulse generaes a large error for a shor ime. Also, i is imporan, wih he MC444, o mainain he correc polariy when connecing he U1 and D1 oupus of he digial Phase/Freq. deecor o he differenial inpus of he inegraor. (I does no maer which oupu of he analog comparaor, invered or non-invered, is conneced o he couner's clock inpu.) The Differenial Inpu Filer / Inegraor There are many ypes of filers ha can be used in a PLL. For he MC444 (Ref. 3), he differenial inpu opamp inegraor can provide superior performance. One advanage is ha he differenial inpu allows he inegraor o have a separae ground from he digial Phase/Freq. deecor ground. The filer is comprised of 5 pars: (See Figure 2.) A. The main inegraor R1 and C1. (Where R1 = 2 x R1h) B. The corner frequency a which he inegraor revers o a consan loss R2, C1. C. The maximum loss afer he corner frequency: R2 / R1. D. A ee pre-filer R1h, C2, R1h. E. A varacor filer R3, C3. The "ee" filer inegraes he U1 and D1 signals o allow he op-amp o operae more accuraely on he error informaion in he very narrow U1 and D1 pulse widhs. This resuls in beer sideband filering. The cuoff frequency of he varacor filer is made high enough so i has almos no effec on he loop bandwidh. I also provides a convenien place o break he loop for open loop esing. AN14A Apr 8, 1997 Page 3 of 9

4 Differenial Inpu Filer / Inegraor -- Seleced Operaing Condiions Capacior C1 is seleced o obain reasonable resisor values for he op-amp circui. BWp deermines he loop lock-up ime, and i can be fine uned o adjus a leas some of he resisors o be close o sandard values. The damping facor (df) deermines he ampliude of overshoo in response o a sep inpu. The value of his facor is usually se beween 1. (13% overshoo) and.5 (3% overshoo) for a Type 2, 2nd Order filer. From he measuremens in Table 1: Svco = dela MHz / dela vols = (18.9MHz mhz) / (7.v - 3.v) = 2.25 MHz/vol fo = sqr(f high x F low ) = sqr(18.9mhz x 9.89MHz) = 13.7 MHz The wo iems above and he sysem consrains' resuls in he following 7 parameers ha are used o calculae he componen values of he loop filer (Table 4): VDD 4. vols Measured phase deecor oupu volage swing. Svco 2.3E+6 Hz/vol Measured VCO sensiiviy. C1 2.2E-9 farads Seleced value for he main inegraor capacior. df.77 Seleced damping facor (21 % overshoo). fr 3.2E+6 Hz Reference frequency inpu o he phase deecor. (Channel spacing) BWp 4.9 % Seleced loop bandwidh as a percenage of he ref. freq. fo 13.7E+6 Hz Approximae cener frequency of he VCO. Table 4. Seven parameers for he PLL calculaions. Filer Calculaions based on he seleced operaing condiions VCO gain consan: Kvco = 2 x Pi x Svco = 14.14e+6 rad/sec/vol Radical used o deermine he filer's naural frequency: radical = sqr(d + sqr(d) + 1) = 2.19 (where: d = (2 x df 2 ) + 1 = ) Toal reference frequency coun: N = fo / fr = 4.28 The filer's naural frequency in Hz: FNhz = BWhz / radical = 74,634 Hz The filer's naural freq. in radians/sec: fnw = 2 x Pi x fnhz = 468,942 rad/sec Phase deecor gain consan: Kph_de = VDD / (2 x Pi) =.637 vols/rad Main inegraor resisor (before being spli): R1 = (Kph_de x Kvco) / (C1 x fnw^2 x N) = 4,345 ohms Main inegraor resisor (afer being spli): R1h = R1 / 2 = 2,173 ohms The resisor in series wih C1: R2 = (2 x df) / (fnw x C1) = 1,317 ohms The inpu "ee" capacior: (Used.4 insead of Moorola's.8. If C2 ges oo large, he loop ends o oscillae.) C2 =.4 / (fnw x R1) = 196e-12 farads The varacor filer resisor: R3 = R1 = 2,173 ohms The varacor filer capacior: C3 = C2 / 4 = 49.1e-12 farads Loop bandwidh in Hz: BWhz = BWp x.1 x fr = 156,8 Hz Loop bandwidh in rad/sec: BWw = 2 x PI x BWhz = 985.2e+3 rad/sec AN14A Apr 8, 1997 Page 4 of 9

5 Figure 4 shows he bode plo of he inegraor wih jus R1, R2, and C1 insalled. I has a breakpoin a 6.5 khz a which i revers o a consan loss. The resuling loss afer he breakpoin is: R2 / (R1h x 2) = 294 / (59 x 2) =.249 Expressed in db: 2 log(.249) = db Adding C2 (he "ee cap") o he circui gives he inegraor a 2nd breakpoin a 5 khz (Figure 5). In boh Figures 4 and 5 he phase margin is displayed -- he frequency and phase a which he gain passes hrough db. Figure 4. Bode plo of he inegraor wih 1 breakpoin, (wihou he "ee cap"). Firs, a linear VCO is defined by seing he parameers of an FM oken (from he red Funcion Library) as follows: Ampliude (v) = 1 (defaul, zero-o-peak) Mod Gain (Hz/v) = 2.25e+6 Frequency (Hz) = 13.7e+6 Phase (deg) = (defaul) The Frequency, 13.7e+6, is fo, he cener of he operaing range of he VCO. The Mod Gain of 2.25e+6 is Svco, he measured VCO sensiiviy. This FM oken will now have he ransfer funcion shown in Table 5. Vols MHz ec. ec ec. ec. Table 5. The linear ransfer funcion of he FM oken. The FM oken's ransfer funcion is made non-linear by preceding i wih an Exernal Transfer Funcion (Xrnl Fc) oken. This oken performs a linear inerpolaion based on he inpu signal and he daa in he exernal ex file, shown in Table 3. The daa in Table 3 was calculaed as follows: (Fou - Fcener) / 2.25 = ( ) / 2.25 = Figure 5. Bode plo of he inegraor wih 2 breakpoins, (wih he "ee cap"). Simulaing he VCO SysemView by ELANIX was used o simulae he VCO ransfer funcion in Table 2. Referring o Tables 2, 3, and 5, he signal flow is as follows. A.5 vol inpu o he Xfer Fc oken resuls in a vol oupu. This is applied o he FM oken ha has a gain of 2.25 MHz/Vol and a cener frequency of 13.7 MHz (zero vols inpu). The FM oken will have an oupu of (3.48 * 2.25) MHz less han he 13.7 MHz cener frequency. ( ) = 5.87 MHz) To simulae ECL (emier coupled logic) levels, he FM oken's sinewave oupu is followed by a Limier oken and hen a polynomial (Poly) oken. The VCO simulaion and resuls are shown in Figures 6 and 7. These four Funcion okens will be conained in one Measysem oken and used as he VCO in a PLL simulaion. AN14A Apr 8, 1997 Page 5 of 9

6 Figure 6. Tes sysem for he VCO simulaion. SysemView Overlay of he Inpu, TransFc oupu, FM oupu, and ECL oupu 4.e-9 8.e-9 1.2e-6 1.6e-6 2.e-6 A m p l i u d e e-9 8.e-9 1.2e-6 1.6e-6 2.e-6 Time in Seconds Figure 7. Inpu, ransfer funcion, and oupu plos of he VCO simulaion. (496 samples a 512e6 samples/sec) AN14A Apr 8, 1997 Page 6 of 9

7 Simulaing he PLL breadboard Figure 8 shows he PLL as i appears in he SysemView Sysem window. The Op-Amp Inegraor, and RC filers, are okens from he RF Library. The Analog Comparaor, Couner/Divider (7444), and he Phase Deecor (MC444), are from he Logic Library. All of he oher okens are from he sandard library. Figure 1 is he parameer enry window for he loop filer. A ground signal is conneced o he Op Amps posiive inpu using a Sep source se o zero vols. A 2nd RC lowpass filer (PLL RC1) is used for he varacor circui, wih R = 2.21K and C = 47pF. Figure 11 shows he parameer enry window for he RC highpass filer (RC Deriv) used in he ECL-o- TTL level shifer. Figures 12 and 13 show a lock-in ime of abou 1 usec wih abou 2% overshoo. During his ime he VCO goes from is low frequency limi of 5.87 MHz o he locked-in frequency of 12.8 MHz. Oscilloscope measuremens of he breadboard exhibied almos exacly he same sawooh sep response ime and overshoo value. Figure 14 shows he VCO oupu sweeping in frequency and locked-in wih he 12.8 MHz specral line a lile above dbm. Figure 8. The PLL as i appears in SysemView's Sysem window. Figure 9. Figure no necessary for he 32-bi version. Figure 1. The Filer/Inegraor (Op-PLL2) parameer enry window. AN14A Apr 8, 1997 Page 7 of 9

8 SysemView Power Specrum of VCO (dbm 5 ohms) 5.e+6 1.e+6 15.e+6 2.e+6 25.e+6 2 P o w e r -2 d B m e+6 1.e+6 15.e+6 2.e+6 25.e+6 Frequency in Hz (Res = 13.67e+3 Hz) Figure 11. The RC-Diff parameer enry window, used as a 1-pole highpass filer, preceding he comparaor. SysemView A m p l i u d e e-6 25.e-6 Varacor filer oupu (13) Time in Seconds Figure 12. VCO increasing in frequency as he loop locks ono he Ref. frequency. (496 samples a 56e6 samples/sec) SysemView A m p l i u d e e-6 13.e-6 Varacor filer oupu (13) 15.5e e-6 Time in Seconds 18.e-6 18.e-6 5.e-6 5.e-6 2.5e-6 2.5e-6 Figure 13. A "zoomed in" area of Figure 11, showing he overshoo. Figure 14. VCO increasing in frequency and locked in a 12.8 MHz. (496 samples a 56e6 samples/sec) SysemView runs as a ime sampled sysem. Nyquis's sampling heorem (Ref. 4 and Ref. 5) would have us se he sample rae a a minimum of 2 x he maximum frequency. Since he highes frequency oupu of he VCO is abou 14 MHz, including he overshoo, he minimum sample rae is 2 x 14 MHz yielding 28e6 samples/sec. The sysem sample rae used in his simulaion is 56e6 samples/sec. This is 4 imes he highes frequency in he sysem (14 MHz). A lower frequency sample rae will work (28e6 samples/sec), yielding a faser simulaion, bu he waveform plos are no as accurae. In his example, increasing he sample rae above 4 or 5 imes he 14 MHz frequency does no seem o have any benefi. Addiional informaion on PLL's can be found in Alan Tam's aricle (Ref. 6), and Moorola's publicaions (Ref. 7, and Ref. 8). An evaluaion version of he sofware, SysemView by ELANIX, Inc., ha will run he examples in his aricle is available on he Inerne. Also, available is he spreadshee PLL-DIF.XLS ha calculaes he PLL filer's pars values based on 7 enered parameers. The spreadshee runs under Microsof's EXCEL. Summary The sofware simulaion of a PLL has been shown o closely mach he measured response of a breadboard version of he PLL. This simulaion enables he elecronic sysem designer o ry "wha ifs" o gain furher insighs ino he operaion of a PLL. Also, a spreadshee forma for calculaing he loop filer componen values has been presened. Addiional PLL simulaion informaion is conained in applicaion noe -- AN15 Alias (Spur) Reducion in Sampled Sysems using he 32-bi version of SysemView by ELANIX AN14A Apr 8, 1997 Page 8 of 9

9 References 1. MECL Daa, DL122/D Rev 5, Moorola, pages 4-3 hrough 4-1, (MC1648). 2. Fred Salvai, "Technique eases design of phase-locked loops" -- "A PLL primer", EDN, Augus 2, MECL Daa, DL122/D Rev 5, Moorola, page 6-3, (MC444). 4. Analog Devices, "MIXED-SIGNAL DESIGN SEMINAR, pages III-2 o III-4 5. Harris Semiconducor, "1994 HIGH SPEED SIGNAL PROCESSING SEMINAR", Glossary page 19, 24 More Informaion For more informaion on SysemView simulaion sofware please conac: ELANIX, Inc Lindero Canyon Road, Suie 721 Weslake Village CA Tel: (818) Fax: (818) Or visi our web home page ( hp:// ) o down load an evaluaion version of he sofware ha can hese simulaions as well as oher user enered designs. 6. Alan Tam, "A 18-MHz synhesizer from a $1 CMOS chip", MICROWAVES & RF, Apr Radio, RF and Video Applicaions, DL413/D, Moorola, pages Applicaion Noe, AN532A, Moorola. AN14A Apr 8, 1997 Page 9 of 9