MX629. DELTA MODULATION CODEC meets Mil-Std DATA BULLETIN. Military Communications Multiplexers, Switches, & Phones

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1 DATA BULLETIN MX629 DELTA MODULATION CODEC mees Mil-Sd Feaures Mees Mil-Sd Single Chip Full Duplex CVSD CODEC On-chip Inpu and Oupu Filers Programmable Sampling Clocks 3- or 4-bi Companding Algorihm Powersave Capabiliies Low Power, 5.0V Operaion Applicaions Miliary Communicaions Muliplexers, Swiches, & Phones The MX629 is a Coninuously Variable Slope Dela Modulaion (CVSD) Codec designed for use in miliary communicaions sysems. This device is suiable for applicaions in miliary dela muliplexers, swiches, and phones. The MX629 is designed o mee Mil-Sd specificaions. Encoder inpu and decoder oupu filers are incorporaed on-chip. Sampling clock raes can be programmed o 16, 32, or 64kbps from an inernal clock generaor or exernally injeced in he 8 o 64kbps range. The sampling clock frequency is oupu for he synchronizaion of exernal circuis. The encoder has an enable funcion for use in muliplexer applicaions. Encoder and Decoder forced idle capabiliies are provided forcing paern in encode and a V DD /2 bias in decode. The companding circui may be operaed wih an exernally selecable 3- or 4-bi algorihm. The device may be placed in sandby mode by selecing Powersave. A reference 1.024MHz oscillaor uses an exernal clock or crysal. The MX629 operaes wih a supply volage of 5.0V and is available in he following packages: 24-pin PLCC (MX629LH), 22-pin CERDIP (MX629J), and 22-pin PDIP (MX629P).

2 Dela Modulaion CODEC 2 MX629 Secion CONTENTS Page 1 Block Diagram Signal Lis Exernal Componens General Descripion Applicaion CODEC Inegraion Digial o Analog Performance Performance Specificaion Elecrical Performance Absolue Maximum Raings Operaing Limis Operaing Characerisics TIMING Packaging MX-COM, Inc. reserves he righ o change specificaions a any ime and wihou noice.

3 Dela Modulaion CODEC 3 MX629 1 Block Diagram Figure 1: Block Diagram

4 Dela Modulaion CODEC 4 MX629 2 Signal Lis J/P LH Name Signal Descripion 1 1 Xal/Clock inpu Inpu o he clock oscillaor inverer. A 1.024MHz Xal inpu or exernally derived clock is injeced here. See Clock Mode pins and Figure 2. 2 N/C No Connecion 2 3 Xal oupu The MHz oupu of he clock oscillaor inverer. 3 4 N/C No Connecion 4 5 Encoder Daa Clock inpu/ oupu A logic I/O por. Exernal encode clock inpu or inernal daa clock oupu. Clock frequency is dependen upon Clock Mode 1, 2 inpus and Xal frequency (see Clock Mode pins). 5 6 Encoder Oupu oupu The encoder digial oupu. This is a hree-sae oupu whose condiion is se by he Daa Enable and Powersave inpus. See Table Encoder Force Idle When his pin is a a logical 0 he encoder is forced o an idle sae and he encoder digial oupu is 0101, a perfec idle paern. When his pin is a logical 1 he encoder encodes as normal. Inernal 1M pullup. 7 8 Daa Enable inpu Daa is made available a he encoder oupu pin by conrol of his inpu. See Encoder Oupu pin. Inernal 1 M pullup. 8 9 N/C No Connecion 9 10 V BIAS Normally a V DD /2 bias, his pin should be exernally decoupled by capacior C4. Inernally pulled o V SS when Powersave is a logical Encoder Inpu inpu The analog signal inpu. Inernally biased a V DD /2, his inpu requires an exernal coupling capacior. The source impedance should be less han 100. Oupu channel noise levels will improve wih an even lower source impedance. See Figure V SS power Negaive Supply N/C No Connecion Decoder Oupu oupu The recovered analog signal is oupu a his pin. I is he buffered oupu of a lowpass filer and requires exernal componens. During Powersave his oupu is open circui N/C No Connecion Powersave A logic 0 a his pin pus mos pars of he codec ino a quiescen non-operaional sae. When a a logical 1, he codec operaes normally. Inernal 1 M pullup. 17 N/C No Connecion Decoder Force Idle A logic 0 a his pin gaes a paern inernally o he decoder so ha he Decoder Oupu goes o V DD /2. When his pin is a logical 1 he decoder operaes as normal. Inernal 1M pullup Decoder Inpu The received digial signal inpu. Inernal 1 M pullup Decoder Daa Clock inpu/ oupu A logic I/O por. Exernal decode clock inpu or inernal daa clock oupu, dependen upon clock mode 1,2 inpus. See Clock Mode pins Algorihm A logic 1 a his pin ses his device for a 3-bi companding algorihm. A logical 0 ses a 4-bi companding algorihm. Inernal 1 M pullup.

5 Dela Modulaion CODEC 5 MX629 J/P LH Name Signal Descripion Clock Mode 2 Clock raes refer o f = 1024MHz Xal/Clock inpu. During inernal Clock Mode 1 operaion he daa clock frequencies are available a he pors for exernal circui synchronizaion. Independen or common daa rae inpus o Encode and Decode daa clock pors may be employed in he Exernal Clocks mode. Inernal 1M pullups. See Table V DD power Posiive Supply. A single 5.0V supply is required. Table 1: Signal Lis Daa Enable Powersave Encoder Oupu 1 1 Enable 0 1 High Z (open circui) 1 0 V SS Table 2: Encoder Oupu Clock Mode 1 Clock Mode 2 Faciliy 0 0 Exernal Clocks 0 1 Inernal, 64kbps = f/ Inernal, 32kbps = f/ Inernal, 16kbps = f/64 Table 3: Clock Mode

6 Dela Modulaion CODEC 6 MX629 3 Exernal Componens Figure 2: Recommended Exernal Componens for Typical Applicaion R1 Noe 1 1M 10% C3 Noe 4 1.0F 20% R2 Noe 2 Selecable C4 Noe 5 1.0F 20% C1 Noe 3 33pF 20% C5 Noe 6 1.0F 20% C2 Noe 3 68pF 20% X1 Noe 7, MHz Table 4: Recommended Exernal Componens for Typical Applicaion Noes: 1. Oscillaor inverer bias resiser. 2. Xal Drive limiing resisor. 3. Xal circui load capacior. 4. Encoder inpu coupling capacior. The drive source impedance o his inpu should be less han 100. Oupu idle channel noise levels will improve wih even lower source impedance. 5. Bias decoupling capacior 6. V DD decoupling capacior 7. A 1.024MHz Xal/Clock inpu will yield exacly 16/32/64kbps daa clock raes. Xal circuiry shown is in accordance wih MX-COM s Xal Oscillaor Applicaion Noe. 8. For bes resuls, a crysal oscillaor design should drive he clock inverer inpu wih signal levels of a leas 40% of V DD, peak o peak. Tuning fork crysals generally canno mee his requiremen. To obain crysal oscillaor design assisance, please consul you crysal manufacurer. 4 General Descripion The MX629 is a Coninuously Variable Slope Dela Modulaion (CVSD) Codec designed for use in miliary communicaions sysems. This device is suiable for applicaions in miliary dela muliplexers, swiches and phones. The MX629 is designed o mee Mil-Sd specificaions. Encoder inpu and decoder oupu filers are incorporaed on-chip. Sampling clock raes can be programmed o 16, 32, or 64kbps from an inernal clock generaor or exernally injeced in he 8 o 64kbps range. The sampling clock frequency is oupu for he synchronizaion of exernal circuis. The encoder has an enable funcion for use in muliplexer applicaions. Encoder and Decoder forced idle capabiliies are provided forcing paern in encode and a V DD /2 bias in decode. The companding circui may be operaed wih an exernally selecable 3- or 4-bi algorihm. The device may be placed in sandby mode by selecing Powersave. A reference 1.024MHz oscillaor uses an exernal clock or crysal.

7 Dela Modulaion CODEC 7 MX629 5 Applicaion Due o he very low levels of a signal idle channel noise specified for miliary applicaions, a noisy or badly regulaed power supply could cause insabiliy, puing he overall sysem performance ou of specificaion. Adherence o he poins lised below will assis in minimizing his problem. 1. Care should be aken in he design and layou of he prined circui board. 2. All exernal componens (as recommended in Figure 2) should be kep close o he package. 3. Tracks should be kep shor, paricularly he Encoder Inpu capacior and he V BIAS capacior. 4. Xal/Clock racks should be kep well away from analog inpus and oupus. 5. Inpus and oupus should be screened whenever possible. 6. A ground plane conneced o V SS will assis in eliminaing exernal pick-up on he inpu and oupu pins. 7. I is recommended ha he power supply rails have less ha 1mV RMS of noise allowed. 8. The source impedance o he Encoder Inpu pin mus be less ha 100W; oupu idle channel, noise levels will improve wih even power source impedances. 5.1 CODEC Inegraion Figure 3: Sysem Configuraion using he MX Digial o Analog Performance Sample Rae Bi Sequence a Decoder Inpu Run of Threes (%) Oupu level (dbm0) 16kbps kbps kbps kbps Table 5: Bi Sequence Tes and Resuls

8 Dela Modulaion CODEC 8 MX629 Figure 4: Gain vs. Inpu Level (16kbps) Figure 5: Gain vs. Inpu Level (32kbps) Figure 6: S/N vs. Inpu Level (16kbps)

9 Dela Modulaion CODEC 9 MX629 Figure 7: S/N vs. Inpu Level (32kbps) Figure 8: Aenuaion disroion vs. Frequency (16kbps) Figure 9: S/N vs. Inpu Frequency (16kbps)

10 Dela Modulaion CODEC 10 MX629 Figure 10: S/N vs. Inpu Frequency (32kbps) Figure 11: Principal Inegraor Response Figure 12: Compand Envelope

11 Dela Modulaion CODEC 11 MX629 Figure 13: Aenuaion Disorion vs. Frequency (32kbps) 6 Performance Specificaion 6.1 Elecrical Performance Absolue Maximum Raings Exceeding hese maximum raings can resul in damage o he device. Min. Max. Unis Supply (V DD - V SS ) V Volage on any pin o V SS -0.3 V DD V Curren V DD ma V SS ma any oher pin ma J / P / LH Packages Toal Allowable Power Dissipaion a T AMB = 25 C mw Deraing above 25 C - 10 mw/ C above 25 C Sorage Temperaure C Operaing Temperaure C Operaing Limis Correc operaion of he device ouside hese limis is no implied. Min Typ. Max. Unis Supply (V DD - V SS ) V Operaing Temperaure C Xal Frequency MHz

12 Dela Modulaion CODEC 12 MX Operaing Characerisics For he following condiions unless oherwise specified: V DD = 5.0V a T AMB = 25 C, Audio Tes Frequency = 820Hz Xal/Clock f 0 = 1.024MHz 3-bi Compand Algorihm, Sample Clock Rae = 32kbps, Audio level 0dB ref (0 dbm0) = 489mV RMS. Noes Min. Typ. Max. Unis Saic Values Supply Volage V Supply Curren (Enabled) 5.5 ma Supply Curren (Powersave) 400 A Inpu logic V Inpu Logic V Oupu Logic V Oupu Logic V Digial inpu Impedance Logic I/O pins M Logic Inpu pins, Pullup Resisor k Digial oupu impedance 4 k Analog Inpu Impedance 4 1 k Analog Oupu Impedance Three Sae Oupu Leakage -4 4 A Inserion Loss db Dynamic Values 1,9 Encoder Analog signal Inpu levels 5, dbmo Principal Inegraor Frequency Hz Encoder Passband 3400 Hz Compand Time Consan ms Decoder Analog Signal Oupu Levels 5, dbmo Decoder Passband Hz Encoder Decoder (Full Codec) Compression Raion (Cd = 0.3 o Cd = 0.0) Passband Hz Sopband 4.2 KHz Sopband Aenuaion 4200Hz o 6000Hz 25 db >6000Hz 60 db Passband Gain 0 db Passband Ripple -3 3 db 300Hz 1400Hz -1 1 db 1400Hz 2600Hz -1 1 db 2600Hz 3400Hz -2 3 db Oupu Noise (Inpu Shor Circui) 9-55 dbmo Perfec Idle Channel Noise (Encode Forced) 9-57 dbmo 16:1

13 Dela Modulaion CODEC 13 MX629 Group Delay Disroion 4 Noes Min. Typ. Max. Unis (1000Hz-2600Hz) s (600Hz-2800Hz) s (500Hz-3000Hz) ms Xal/clock Frequency 1024 khz Noes: 1. Dynamic characerisics are specified a 5.0V unless oherwise specified. 2. All logic inpus excep Encoder and Decoder Daa clocks 3. For and encoder/decoder combinaion, Inserion loss conribued by a single componen is half his figure. 4. Driven wih a source impedance of < Recommended values See Figures 4, 5, 6, and Group Delay Disorion for he full codec is relaive o he delay wih and 820Hz, -20dB signal a he encoder inpu 7. An Emier Follower oupu sage. 8. 4V = 80%V DD, 3.5V = 70%V DD, 1.5V = 30%V DD, 1V = 20%V DD 9. Analog Volage Levels used: 0dBmO = 489mV RMS = -4dBm = 0dB. 15dBmO = 87mV RMS. 20dBmO = 49mV RMS = -24dBm TIMING Serial Bus Timings (See Figure 14) Min. Typ. Max. Unis CH Clock 1 pulse widh 1.0 s CL Clock 0 pulse widh 1.0 s IR Clock rise ime ns IF Clock fall ime 100 ns SU Daa se-up ime 450 ns H Daa hold ime 600 ns SU + H Daa rue ime 1.5 s PCO Clock o oupu delay ime 750 ns DR Daa rise ime 100 ns DF Daa fall ime 100 ns Xal inpu frequency = 1.024MHz

14 Dela Modulaion CODEC 14 MX629 ENCODER TIMING ENCODER CLOCK DATA CLOCKED CH IF CL IR CH ENCODER OUTPUT DATA PCO DECODER TIMING DECODER CLOCK DATA CLOCKED DECODER INPUT DATA SU H DATA TRUE TIME ENCODER OUTPUT MULTIPLEXING FUNCTION HIGH Z HIGH Z DR DF DATA ENABLE Figure 14: CODEC Timing 6.2 Packaging D A E B P PIN 1 G W K Y W T C J H DIM. A B C D E F G H J K P T W Y Package Tolerances MIN. TYP (9.61) (9.61) (3.25) (10.60) (10.60) (0.45) (1.19) (1.24) (0.152) (6.35) (6.35) (0.58) 45 6 MAX (10.40) (10.40) (3.70) (11.05) (11.05) (0.55) (1.22) (1.30) (0.22) F NOTE : All dimensions in inches (mm.) Angles are in degrees Figure 15: 24-pin PLCC (LH) Mechanical Ouline: Order as par no. MX629LH

15 Dela Modulaion CODEC 15 MX629 A Package Tolerances PIN 1 K H L J J1 P B C E1 Y T E DIM. A B C E E1 H J J1 K MIN. TYP. MAX (27.43) (27.94) (8.38) (9.14) (4.70) (10.67) (12.19) (9.91) (10.67) (0.51) (1.14) (0.38) (0.51) (1.02) (1.65) (1.68) L (3.25) P (2.54) T (0.25) Y 7 NOTE : All dimensions in inches (mm.) Angles are in degrees Figure 16: 22-pin PDIP (P) Mechanical Ouline: Order as par no. MX629P PIN1 K H L J A J1 F P B K1 C E1 T E DIM. A B C E E1 F H J J1 K K1 L P T Package Tolerances MIN (26.92) (9.55) (4.19) (11.84) TYP. MAX (27.43) (9.75) (5.84) (13.08) (10.36) (10.62) (25.40) (0.51) (0.46) (1.40) (1.47) (1.91) (2.03) (2.03) (2.92) (4.34) (2.54) (0.249) (0.259) NOTE : All dimensions in inches (mm.) Angles are in degrees Figure 17: 22-pin CERDIP (J) Mechanical Ouline: Order as par no. MX629J

16 CML Microcircuis COMMUNICATION SEMICONDUCTORS CML Produc Daa In he process of creaing a more global image, he hree sandard produc semiconducor companies of CML Microsysems Plc (Consumer Microcircuis Limied (UK), MX-COM, Inc (USA) and CML Microcircuis (Singapore) Pe Ld) have undergone name changes and, whils mainaining heir separae new names (CML Microcircuis (UK) Ld, CML Microcircuis (USA) Inc and CML Microcircuis (Singapore) Pe Ld), now operae under he single ile CML Microcircuis. These companies are all 100% owned operaing companies of he CML Microsysems Plc Group and hese changes are purely changes of name and do no change any underlying legal eniies and hence will have no effec on any agreemens or conacs currenly in force. CML Microcircuis Produc Prefix Codes Unil he laer par of 1996, he differeniaor beween producs manufacured and sold from MXCOM, Inc. and Consumer Microcircuis Limied were denoed by he prefixes MX and FX respecively. These producs use he same silicon ec. and oday sill carry he same prefixes. In he laer par of 1996, boh companies adoped he common prefix: CMX. This noificaion is relevan produc informaion o which i is aached. CML Microcircuis (USA) [formerly MX-COM, Inc.] Produc Texual Marking On CML Microcircuis (USA) producs, he MX-COM exual logo is being replaced by a CML exual logo. Company conac informaion is as below: CML Microcircuis (UK)Ld COMMUNICATION SEMICONDUCTORS Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0) Fax: +44 (0) uk.sales@cmlmicro.com CML Microcircuis (USA) Inc. COMMUNICATION SEMICONDUCTORS 4800 Behania Saion Road, Winson-Salem, NC 27105, USA Tel: , Fax: us.sales@cmlmicro.com CML Microcircuis (Singapore)PeLd COMMUNICATION SEMICONDUCTORS No 2 Kallang Pudding Road, 09-05/ 06 Macech Indusrial Building, Singapore Tel: Fax: sg.sales@cmlmicro.com D/CML (D)/2 May 2002

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