Impacts of the dv/dt Rate on MOSFETs Outline:

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1 Ouline: A high dv/d beween he drain and source of he MOSFET may cause problems. This documen describes he cause of his phenomenon and is counermeasures.

2 Table of Conens Ouline:... 1 Table of Conens... 2 dv/d rae of a MOSFET... 3 When a dv/d ramp occurs dv/d ramp during swiching ransiions dv/d ramp during he diode reverse recovery... 5 MOSFET swiching operaion (inducive load) Turn-on swiching operaion Turn-off swiching operaion... 8 dv/d problem... 9 dv/d problem during swiching False urn-on of he parasiic bipolar ransisor due o a high dv/d ramp dv/dv versus avalanche ruggedness...11 dv/d problem for a MOSFET in he off sae (e.g., during reverse recovery of he body diode) False urn-on of he parasiic bipolar ransisor caused by he dv/d of he diode reverse recovery Self-urn-on phenomenon due o dv/d...13 RESTRICTIONS ON PRODUCT USE / 15

3 dv/d rae of a MOSFET dv/d represens he rae of volage change over ime and is used o indicae he swiching ransien period of a MOSFET or he rae of change of is drain-source volage caused by swiching influence. An excessive dv/d rae migh cause false swiching of, or permanen damage o, a MOSFET, depending on is usage condiions. The dv/d capabiliy is raed for some MOSFETs. When a dv/d ramp occurs The dv/d ramps ha could affec normal operaion of a MOSFET are as follows: 1 The drain-source volage exhibis a dv/d ramp during swiching ransiions. 2 Inverers and oher circuis wih an inducive load ofen use a pair of MOSFETs in a half-bridge configuraion. The MOSFET drain-source volage has a dv/d ramp while is inrinsic body diode ransiions from freewheel mode o reverse recovery mode dv/d ramp during swiching ransiions The drain-source volage of a MOSFET changes during he Miller plaeau region of he swiching ransiion. A change in he gae volage causes a change in he drain curren, which, in urn, causes a change in he drain poenial and herefore a change in he gae-drain volage v GD. A reference o he dv/d ramp of he MOSFET drain-source volage means his V GD change. A gae-drain curren of C gd dv GD/d flows while he drain-source volage is changing in he Miller plaeau region of he dv/d period. In he Miller plaeau region, a large capacior is equivalenly formed beween he gae and GND. This capaciance is called he Miller capaciance. As he word plaeau implies, he gae volage does no increase during he Miller plaeau region of he swiching ransiion. Figure 1.1 shows he swiching circui wih an inducive load, and Figure 1.2 shows is waveforms. Mos dv/d problems occur wih respec o an inducive load. 3 / 15

4 Gae inpu volage V DD On Off v GS Miller period V GG Miller period V GG C gd V h 0 R dv/ d I D C gs v GS C ds GND 0 Figure 1.1 Swiching circui wih an inducive load V DD V DS(on) 0 dv/d dv/d Figure 1.2 Swiching waveforms of an inducive load 4 / 15

5 dv/d ramp during he diode reverse recovery When inverers and oher circuis wih an inducive load have a pair of MOSFETs in he upper and lower arms, a curren flows hrough an inrinsic body diode during reverse recovery while hey are swiching. This secion discusses he diode dv/d during reverse recovery. Suppose ha an inducor curren is flowing hrough he MOSFET Q 2 in Figure 1.3 and ha Q 2 hen urns off. When Q 2 urns off, he inducor curren flows back hrough he body diode of Q 1 as a freewheel curren I F, shown by 1 in Figure 1.3. A his ime, he MOSFET Q 1 has a volage equal o he forward volage V F across he body diode. Nex, when Q 2 urns on again, he curren sars flowing hrough Q 2 as shown by 2 in Figure 1.3, and he body diode of Q 1 eners reverse recovery, causing is drain-source volage o rise sharply. The rae of change of he drain-source volage equals he dv/d rae of he body diode during reverse recovery. Figure 1.4 shows he waveforms of he body diode curren and volage. Diode curren Q 1 1 I F V F Diode volage R Q 2 Diode dv/d during reverse recovery 2 Reverse recovery ime, rr Figure 1.3 Swiching of he upper and lower MOSFETs Figure 1.4 Diode reverse recovery waveforms 5 / 15

6 MOSFET swiching operaion (inducive load) This secion furher discusses he swiching operaion of a MOSFET in Figure 1.1 during which is drain-source volage has a dv/d ramp. This secion focuses on a circui wih an inducive load. Noe ha is operaion differs from ha of a circui wih a resisive load. Here, he reverse recovery curren of he freewheel diode in parallel wih he inducor is also considered during he urn-on of he MOSFET Turn-on swiching operaion Figure 1.5 shows he urn-on waveform of he circui of Figure 1.1. The MOSFET has a dv/d ramp during he period 2 o 3 (i.e., during he swiching ransiion). (1) 0 o 1 (The MOSFET is in he off sae.) The gae volage v GS increases as a funcion of he gae resisance R, he gae-source capaciance C gs and he gae-drain capaciance C gd: v GS = V GG{1-exp{-/[ R (C gs+c gd)]}} (1) (2) 1 o 2 (The MOSFET is swiching.) A 1, he gae volage of he MOSFET exceeds is gae hreshold volage V h, causing a curren o sar flowing in he drain. When he drain curren becomes equal o he load curren I O, i.e., he freewheel curren, he freewheel diode in he forward-biased mode eners reverse recovery. increases due o he reverse recovery curren of he freewheel diode. During his period, he drain-source volage of he MOSFET remains equal o V DD and he gae volage v GE increase is almos he same as in he period from 0 o 1, which is expressed by Equaion (1). (3) 2 o 3 (The MOSFET is swiching.) As he reverse recovery curren of he freewheel diode falls o zero, he drain curren of he MOSFET reaches he load curren I O. Then, he gae volage drops o V GS1 a which he drain curren equals I O. As he drain volage decreases, he d/d causes a curren o flow hrough he gae-drain capaciance C gd. This curren is expressed as G=C gd d /d. The d/d rae is deermined so ha G equals he curren (V GG-v GS)/R, which is a funcion of he gae pulse volage V GG and he gae resisance R. During his period, he gae volage v GS remains almos consan a V GS1. (Miller plaeau) (4) Afer 3 (The MOSFET is in he on sae.) Because he drain-source volage drops o almos zero a 3, he gae volage begins o rise again due o R and (C gs+ C gd). 6 / 15

7 The gae volage is calculaed as: v GS= [ V GG V GS1]{1-exp[-(- 3) / R ( C gs+c gd ) ]}+ V GS1 v DD d / d V DS(on) v GS I O 3 V h V GS Figure 1.5 Turn-on curve 7 / 15

8 Turn-off swiching operaion Impacs of he dv/d Rae on MOSFETs Figure 1.6 shows he urn-off waveform of he circui of Figure 1.1. The MOSFET has a dv/d ramp during he period 2 o 3 (i.e., during he swiching ransiion). (1) 0 o 1 (The MOSFET is in he on sae.) The gae volage v GS decreases as a funcion of he gae resisance R, he gae-source capaciance C gs and he gae-drain capaciance C gd: v GS = V GG exp{-/ [R (C gs+c gd)]} (2) (2) 1 o 2 (The MOSFET is swiching.) When he gae volage reaches V GS1 a which he drain curren of he MOSFET reaches he load curren I O, he drain volage begins o increase. As he drain volage increases, he d/d ramp causes a curren o flow hrough he gae-drain capaciance C gd. This curren is expressed as G=C gd d /d. The d/d rae is deermined so ha G equals he curren v GS/R, which is a funcion of he gae pulse volage (=0 V) and he gae resisance R. During he period 1 o 2, he gae volage v GS remains almos consan a V GS1, and he drain-source volage of he MOSFET increases up o he supply volage V DD. (3) 2 o 3 (The MOSFET is swiching.) When he drain-source volage has reached he supply volage V DD, he freewheel diode goes ino conducion. A he same ime, he drain curren begins o decrease. Due o R and (C gs+c gd), he gae volage v GS begins o decrease again and coninues o decrease unil i reaches V h. During his period, v GS is expressed as: V GS1 exp{-(- 2) / [R (C gs+c gd)]}. (4) Afer 3 (The MOSFET is in he off sae.) Because he drain curren is zero, he drain-source volage equals he supply volage V DD and d/d is zero, he gae volage begins o decrease again due o R and (C gs+ C gd). During his period, v GS is expressed as: v GS =V GS1 exp{-(- 2)/[R ( C gs + C gd )]}. d / d V DD V DS(on) v GS 0 I O V GG V h V GS Figure 1.6 Turn-off curve 8 / 15

dv/d problem An excessive dv/d rae migh cause false swiching, oscillaion or permanen damage of a MOSFET. This secion discusses hese phenomena. Figure 2.

1 Cross secion and equivalen circui of a MOSFET 1 dv/d problem during swiching If he drain-source volage changes rapidly during he urn-off of a MOSFET, is parasiic npn bipolar ransisor migh exhibi a

9 dv/d problem An excessive dv/d rae migh cause false swiching, oscillaion or permanen damage of a MOSFET. This secion discusses hese phenomena. Figure 2.1 shows he cross secion and equivalen circui of a MOSFET. Figure 2.1 Cross secion and equivalen circui of a MOSFET 1 dv/d problem during swiching If he drain-source volage changes rapidly during he urn-off of a MOSFET, is parasiic npn bipolar ransisor migh exhibi a false swiching even (Figure 2.1), making he MOSFET vulnerable o secondary breakdown and permanen damage. Upon urn-off, a high volage surge generaed by he wire sray inducance migh cause he MOSFET o reach is avalanche breakdown volage. A high dv/d rae degrades he avalanche ruggedness of a MOSFET. 2 dv/d problem during he reverse recovery of he body diode While he inrinsic body diode of a MOSFET is in reverse recovery, is drain-source volage rises. This migh falsely urn on he inernal parasiic npn bipolar ransisor, causing permanen damage o he MOSFET. 9 / 15

10 dv/d problem during swiching False urn-on of he parasiic bipolar ransisor due o a high dv/d ramp Figure 2.2 shows an equivalen circui model for he urn-on of he parasiic npn bipolar ransisor in a MOSFET due o a high dv/d. The drain-source volage changes rapidly during urn-off of a MOSFET. The dv/d in he drain-source volage causes a varying curren o flow hrough he pn juncion capaciance C and resisance R. This curren is expressed as: i= C (dv/d) The curren i causes a volage drop (i R) across he resisor R, which is applied across he base and he emier of he parasiic bipolar ransisor. The parasiic bipolar ransisor urns on if he volage drop exceeds is base-emier volage o urn on. The larger he dv/d rae, he larger he curren i and he larger he volage across he base and he emier becomes. The larger base-emier volage makes he parasiic npn bipolar ransisor more suscepible o false urn-on. A his ime, if he drain-source volage of he MOSFET is high, he parasiic npn ransisor migh ener secondary breakdown, causing permanen damage o he MOSFET. Drain i=c (dv/d) dv/d C npn Gae R Source Figure 2.2 Equivalen circui for false urn-on of he parasiic npn bipolar ransisor 10 / 15

11 dv/dv versus avalanche ruggedness A MOSFET wih a high swiching speed has high dv/d and di/d raes. The di/d ramp during he urn-off of he MOSFET causes a volage surge v due o he circui sray inducance: v=l di/d In some cases, he surge volage may cause excessive noise or oscillaion of he MOSFET. In he even of an excessive surge volage, he MOSFET may also exceed is raed volage and ener he avalanche region. A his ime, an avalanche curren passes hrough he MOSFET. An avalanche curren exceeding he curren or energy limi migh cause permanen damage o he MOSFET. Avalanche behavior: Avalanche breakdown occurs in he following wo modes. Figure 2.3 shows a es circui for avalanche behavior, and Figure 2.4 gives an equivalen circui model for an avalanche curren. Figure 2.5 shows is waveform. (A) Avalanche curren breakdown If a volage higher han he breakdown volage is applied across he drain and he source, an avalanche curren i flows in he reverse direcion of he diode and o he resisor R, as shown in he equivalen circui of Figure 2.4. As a resul, a forward volage, i R, appears across he base and he emier of he ransisor. If his volage exceeds he base-emier volage o urn on, he parasiic npn ransisor urns on, causing a curren o flow hrough he ransisor. A his ime, if he drain-source volage is high, he parasiic npn ransisor migh ener secondary breakdown, causing permanen damage o he MOSFET. (B) Avalanche energy breakdown If avalanche behavior causes a MOSFET o ener he breakdown volage BV DSS region, a curren coninues flowing from he drain o he source of he MOSFET unil he energy sored in he inducive load a he drain is consumed. Because of his curren and volage BV DSS, a power loss occurs. The resuling energy causes he device emperaure o increase, and causes permanen damage o he device if i exceeds he raed channel emperaure. V DD L Avalanche curren i Drain Gae volage D R npn Gae BV DSS R I AS V DD Source Figure 2.3 Tes circui for avalanche behavior Figure 2.4 Equivalen circui model for avalanche behavior Figure 2.5 Waveform of he equivalen circui 11 / 15

12 dv/d problem for a MOSFET in he off sae (e.g., during reverse recovery of he body diode) False urn-on of he parasiic bipolar ransisor caused by he dv/d of he diode reverse recovery For example, suppose ha an inverer circui wih an inducive load has MOSFETs in he upper and lower arms. The inrinsic body diode allows a freewheel curren o pass hrough a MOSFET. A recovery curren flows hrough he body diode when i ransiions from freewheeling mode o reverse recovery mode. In reverse recovery mode, he drain-source volage of he MOSEFT rises. The diode s recovery curren and recovery dv/d migh cause false urn-on of he parasiic npn bipolar ransisor and permanen damage o he MOSFET. Figure 2.6 shows an equivalen circui of a MOSFET. A volage change dv/d causes a curren, i= C (dv/d), o flow o he capaciance C of he pn juncion beween he drain and he gae. This causes a volage drop of i R across he resisor R. If he volage drop exceeds he base-emier volage o urn on, he parasiic npn ransisor urns on. A his ime, if he drain-source volage is high, he parasiic npn ransisor migh ener secondary breakdown. As is he case in he siuaion described in Secion 2.1.1, False urn-on of he parasiic bipolar ransisor due o a high dv/d ramp, he MOSFET migh be permanenly damaged, alhough he failure mode is differen. Drain i = C dv / d D 2 D 1 C i npn R Gae Source Figure 2.6 Equivalen circui model during he dv/d 12 / 15

13 Self-urn-on phenomenon due o dv/d Impacs of he dv/d Rae on MOSFETs For example, inverer and non-isolaed synchronous recificaion converer circuis consis of a bridge using MOSFETs. When muliple MOSFETs swich a high speed, a fas rising volage is applied across he drain and source erminals of he MOSFET in he off sae. Depending on he volage change over ime dv/d, an excessive volage is induced a he gae inpu of he MOSFET according o he raio beween is gae-drain capaciance C gd and gae-source capaciance C gs or a curren flowing o he gae resisor R via C gs. An excessive gae volage causes self-urn-on of a MOSFET. When a volage wih a dv/d ramp is applied o a MOSFET, a curren flows hrough is gae-drain capaciance C gd. A heory of operaion is omied here. i = C gd dv d The gae-drain curren, in urn, generaes a volage across he gae and source erminals: dv v GS = RC gd {1 exp ( )} (2) d (C gs + C gd )R (Here, he assumpion is ha MOSFET capaciances, Cgs and Cgd, do no change wih he volage.) C gd In he ime region << (C gs+ C gd ) R, a gae volage, v GS v(), is induced according o (C gs +C gd ) he raio beween C gs and C gd. In he ime region >> (C gs+ C gd ) R, a gae volage is induced according o he produc of a curren dv flowing hrough he gae-drain capaciance C gd, i = C gd, and he gae resisance R. The following shows an example of simulaion resuls, illusraing a self-urn-on phenomenon due o a dv/d and a gae resisor. Figure 2.7 shows a es circui. If Q 2 urns on while he body diode of Q 1 is in freewheeling mode, he body diode of Q 1 eners reverse recovery mode, causing a rise in he volage dv/d of Q 1. The dv/d curren flows o he gae of Q 1. As a resul, a volage ha appears across he gae resisor causes self-urn-on of Q 1. Figure 2.8 shows a waveform wih self-urn-on. Noe ha a large gae resisor was chosen o force self-urn-on o occur. i dg = C dg d / d R 1 MOSFET Q 1 L s C gs C gd L s L s C ds Load Inducance (500 μh) d Waveforms wihou 1=1 Ω, R 2=30 Ω vds (V) rr curren flowing hrough he body diode of Q 1 These waveforms include influence of package inducances. (ns) id (A) L s : Sray inducances of package R 2 MOSFET Q 2 L s L s 400V + - Self-urn-on 1=50 Ω, R 2=30 Ω Curren flowing hrough Q 1 due o self-urn-on 10V v GS L s vds (V) id (A) Figure 2.7 Tes circui for self-urn-on These waveforms include influence of package inducances. (ns) Figure 2.8 Self-urn-on waveform 13 / 15

14 To preven self-urn-on, a capacior can also be added beween he gae and source erminals of a MOSFET as shown in Figure 2.9. Noe, however, ha he capacior affecs he swiching speed of he MOSFET. Figure 2.10 shows he improved waveform compared o he waveform in Figure 2.8 due o he addiion of he gae-source capacior. G = C dg d / d R 4 MOSFET Figure 2.9 Adding a capacior across he gae and source erminals Improved self-urn-on 1=50Ω, R 2=30Ω, Gae-source capaciance C=3000 pf vds (V) id (A) These waveforms include influence of package inducances. (ns) Figure 2.10 Improved self-urn-on waveform 14 / 15

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<Diode Modules> RM200CY-24S HIGH POWER SWITCHING USE INSULATED TYPE

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