A FULL-RATE TRULY MONOLITHIC CMOS CDR FOR LOW-COST APPLICATIONS

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1 A FULL-RATE TRULY MONOLITHIC CMOS CDR FOR LOW-COST APPLICATIONS Bangli Liang 1, Zhigong Wang 2, Dianyong Chen 1, Bo Wang 1, Guohui Siu 1, Tad Kwasniewski 1 1 DOE, Carleon Universiy, 1125 Colonel By Dr., Oawa, ON, K1S 5B6, Canada 2 IROI, Souheas Universiy, Si-pai-lou 2, Nanjing, Jiangsu Province, , China ABSTRACT A ruly monolihic clock and daa recovery (CDR) circui for low cos low-end daa communicaion sysems has been realized in 0.6 m CMOS. The implemened CDR comprises a phase-and frequency-locked loop using an I/Q ring VCO o recover clock from incoming non-reurn-o-zero (NRZ) daa sream and a daa decision circui o reime he received daa, respecively. The novely of his design is ha siliconsaving acive inducors are used o improve he ransmied bi rae and he compaibiliy wih digial circuis for monolihic inegraion, o reduce silicon area, while he excessive noise is suppressed by fully differenial opology. The esed CDR IC achieves a locking range from 400MHz o 950MHz and a RMS jier of UI for a 622Mb/s pseudorandom bi sequence (PRBS) lengh of Index Terms CMOS, monolihic, full-rae, CDR 1. INTRODUCTION Explosive growh in daa communicaions is fueling he demand for high-speed inegraed circuis. As a vial componen, CDR plays an increasingly imporan role in high-capaciy neworks. In modem high-speed daa communicaion sysems, NRZ daa sream is normally ransmied and he clock mus be exraced from he daa. Monolihically inegraed CDR wihou any exernal componen is desired for low cos applicaions. In comparison wih narrowband regeneraive frequency divider (NRFD), phase-locked loop (PLL) is a more aracive choice for he clock recovery since i is easier o be implemened and has high inegraion, reliabiliy and flexibiliy [1]. Generally PLL-based clock recovery (CR) has a very narrow loop bandwidh for good jier aenuaion. However, he uning range of an on-chip VCO mus be wide enough o cover process, volage and emperaure (PVT) variaions. Therefore, frequency acquisiion aid is indispensable for CR implemenaion. In a phase- and frequency-locked loop (PFLL), he phase deecor (PD) and frequency deecor (FD) can be designed independenly o achieve wide capure range, small jier, and low power dissipaion [2]. For mos applicaions, he ime jier and he phase noise are wo imporan design crieria of a PLL. Unforunaely, he swiching aciviy of digial modules in mixed-signal sysems inroduces power-supply or subsrae noise, which grealy disurbs hose noise-sensiive blocks in a PLL. In paricular, noises injeced ono he volageconrolled oscillaor (VCO) pose he dominan jier source of a PLL. In his work, based on he negaive conducance (NC) configuraion, novel differenial delay cells wih acive inducor loads are used o lower phase noise and o improve lineariy of he proposed ring VCO. Moreover, he used submicron CMOS echnology is mos aracive o develop commercial low-end chips due o is high reliabiliy and low manufacuring cos. So a low jier, low phase noise, low cos CDR has been implemened in 0.6 m CMOS echnology, which can be used in OC-12 / STM-4 sysems. DIN PFD PD QPD FD MSFF DP QP DP QP DN CP LF QN CN I_CLK Q_CLK DN CP I/Q VCO QN CN Fig.1. Block diagram of he implemened CDR 2. CIRCUIT DESIGN CDR DOUT COUT As shown in Fig.1, he proposed CDR circui is composed of an I/Q VCO, a PFD, a loop filer and a daa reimer which is based on a maser-slave flip-flop. This /09/$ IEEE 1208 Auhorized licensed use limied o: Carleon Universiy. Downloaded on July 7, 2009 a 11:22 from IEEE Xplore. Resricions apply.

2 CDR does no need any edge-deecion circuis o preprocess he incoming NRZ daa sream. In he VCO, 0 o in-phase (I) and 90 o quadraure-phase (Q) clocks are generaed. The PFD has hree funcional blocks: phase deecor (FD), quadraure phase deecor (QPD) and frequency deecor (FD). All of he main blocks in he CDR are fully differenial. A differenial VCO srucure reduces he effecs of common-mode noise, he magniude of curren spikes injeced o power supply and subsrae, and ulimaely he clock jier generaion. Similarly, differenial archiecures adoped in he PFD and he loop filer can improve he performance of he CR wih a noisy supply and subsrae. Inpu, oupu buffers and iner-sage buffers are used o realize inpu maching, DC level shif, impedance ransforming and decouple he CDR core from exernal 50 environmen. Subcircuis are described below. CIN DIN MUX / PD/QPD I_CLK Vcrl Conrol Delay1 Delay2 Delay3 Delay4 Buffer CKIN I/Q Ring-VCO MLN Acive Inducor Rg MAP I1 Rg MAN MLP MFP I2 MFN MSP MSN CKOUT VBB Vlpf+ Mc1 KI1 (c) Buffer Iss KI2 Q_CLK Vlpf- Mc2 Fig.2. The proposed I/Q VCO: Block diagram, Schemaic of he proposed variable delay gain sage, (c) differenial conrol circui Volage Conrolled Ring Oscillaor As a pivoal building block in PLL, high frequency and RF VCOs can be implemened monolihically as LC oscillaors and ring oscillaors. In comparison, monolihic high-q LC oscillaors have lower phase noises bu ring VCOs offer wider uning ranges and consume smaller die areas. The realized I/Q ring VCO comprises a differenial conrol circui for VCO uning, four-sage delay cells and wo buffering amplifiers as shown in Fig.2. The adoped novel differenial variable-delay gain sage wih acive inducor loads and he employed conrol circui o generae differenial conrol volages V con+ and V con- for he gain sages of VCO are shown in Fig. 2 and (c), respecively. Modified MUX Fig.3. Schemaic of he proposed PD/QPD, and FD. Since a high performance ring VCO can be easily obained using he negaive conducance [3], he used VCO is also developed in his echnology. As shown in Fig. 2, he variable-delay gain sage is consiued by ransisor pair M AP, M AN, cross-coupled pair M FP, M FN, acive inducor load pair M LP /R g, M LN /R g and oher ransisors used as curren sources, source followers and biasing blocks. Firsly, a gain sage wih MOS loads is difficul o operae a high daa rae due o he large ime consan of load capaciance, bu a gain sage wih inducive loads can provide much larger gain-bandwidh produc. Using inducive loads, he capaciive loading can be parly uned ou, and hen he pole of each gain sage can be pushed oward high frequency end, which is he so-called shun-peaking echnique. In general, inducive loads can be implemened wih on-chip spiral inducors or acive inducors. I is very difficul o realize a high-inducance and high-q on-chip spiral inducor wih a small die area. Conrarily, acive inducors are compac and offer adequaely high operaing speed [4]. Thereupon, acive inducor pair M LP /R g, M LN /R g is inroduced here as he loads of ransisor pair M AP, M AN o maximize he operaing frequency of he proposed VCO. Secondly, he cross-coupled pair M FP, M FN inroduces a negaive average conducance ha reduces he overall oupu conducance and equivalenly increases he oupu impedance and hence he delay. Thus, his VCO can operae a he expeced frequency range wih less gain sages and he phase noise is enormously lowered. Thirdly, o keep he oupu volage swing a consan, a differenial conrol circui shown in Fig. FD 1209 Auhorized licensed use limied o: Carleon Universiy. Downloaded on July 7, 2009 a 11:22 from IEEE Xplore. Resricions apply.

3 2(c) is employed, in which differenial pair M c1, M c2 is used o seer I ss o M AP, M AN and M FP, M FN. Moreover, in he conrol circui, V con+ and V con- can be viewed as differenial conrol lines and hus provide higher noise immuniy for he conrol inpu. Finally, differenial signals are obained hrough a pair of source followers, which offers wo advanages: an easy direc-connecion wih he subsequen differenial PD and a low-noise oupu signal due o common-mode noises suppression. For a clock recovery applicaion, choosing appropriae ransisors M AP, M AN, M FP, M FN and M c1, M c2 are he key poins. To avoid lach-up, he ransconducance of M FP, M FN mus be less han ha of M AP, M AN. Addiionally, he dimension of M c1, M c2 should be adjused so carefully ha proper VCO gain, loop gain and consequenly wellbalanced uning range, lineariy, and noise performance can be opimized simulaneously. fosc>fb Lock-in poin Cycle slip fosc<fb Cycle slip Lock-in poin frequency f OSC and bi-rae frequency (daa rae) f b are differen. The FD is a differenial logic circui ha receives inpus from PD/QPD and generaes frequency difference signal a he oupu Q 3. As shown in Fig 4, when f OSC <f b, PD oupu Q 1 lags QPD oupu Q 2 and he superposiion of Q 1 and Q 3, is posiive. On he oher hand, when f OSC >f b Q 1 leads Q 2 and he superposiion of Q 1, and Q 3 is negaive, as shown in Fig.4. The superposiion of Q 1 and Q 3 indicaes a clear DC componen driving he loop owards lock Loop Filer Fig. 5 shows he schemaic of he employed loop filer. Unlike oher design [6], his loop filer inegraed on chip wihou any off-chip componen. Q 1 and Q 3 are firs added up and hen low-pass filered. The DC componen drives he loop owards lock. The ransfer funcion of he loop filer is dominaed by C 0, 2R 1, and R Loop Design + Fig.4. Schemaic iming diagrams of PD/PFD; PD, QPD, and FD. + R1 C0 R2 Vcrl The bandwidh of PLL affecs he sabiliy, he suppression of phase noise from VCO, and he oppression of spurious modulaion and pull-in ime. Since he amoun of long-erm jier ha will resul depends on he sensiiviy of he VCO o noise, low-q VCOs based on RC oscillaors, such as relaxaion or ring oscillaors, are very sensiive o noise. Thus, low-q VCOs can only obain low long-erm jier by maximizing he loop bandwidh and racking he inpu frequency as close as possible. In his design, i is se o 50MHz. By analyzing he closed and open loop responses, he phase margin is found o be 65 degree. Fig.5. Schemaic of he realized loop filer Phase Deecor and Frequency Deecor Compared o a convenional PLL wih PD only, PFLL could significanly increase acquisiion range and reduce locking ime. To opimize he operaing speed and avoid problem caused by inernal crossalk, he proposed subcircuis are all based on differenial curren mode logic (CML). In Fig. 3, a CMOS version of Pobäcker PD is proposed [4]. A every ransiion of he inpu daa, I and Q clocks are sampled by he inpu NRZ daa direcly wihou preprocessing circui. This operaion generaes bea noes wih 50% duy cycle a PD/QPD oupus when he VCO Fig.6. Die phoo of he realized CDR Auhorized licensed use limied o: Carleon Universiy. Downloaded on July 7, 2009 a 11:22 from IEEE Xplore. Resricions apply.

3. CHIP FABRICATION The designed CDR circui was fabricaed in CSMC Semiconducor Co., Ld. The chip microphoograph of he dies is shown in Fig. 6. The chip dimension including bonding pads is 1.3mm

Programmable DC Volage/Curren Generaor, a ROHDE & SCHWARZ SMP04 Signal Generaor (10MHz-40GHz), an Agilen Infinium DCA 86

Measuremen resuls: Measured frequency conrol curve of differenial uning VCO; Measured specrum of he in-locked VCO. 4.

4 3. CHIP FABRICATION The designed CDR circui was fabricaed in CSMC Semiconducor Co., Ld. The chip microphoograph of he dies is shown in Fig. 6. The chip dimension including bonding pads is 1.3mm 1.3mm. The dimension of pads is 0.1mm 0.1mm. Obviously, bonding pads and on-chip capaciors are major consumers of layou area. Programmable DC Volage/Curren Generaor, a ROHDE & SCHWARZ SMP04 Signal Generaor (10MHz-40GHz), an Agilen Infinium DCA 86100A Wide-bandwidh Oscilloscope, and a HP 8593A specrum analyzer. Fig.8. Measuremen resuls: Measured eye diagram of he recovered daa a 622Mb/s; Measured jier hisogram of he locked VCO a 622MHz. Fig.7. Measuremen resuls: Measured frequency conrol curve of differenial uning VCO; Measured specrum of he in-locked VCO. 4. MEAUREMENT RESULTS The performance of he fabricaed chips has been evaluaed via on-wafer probing on uncu wafers employing a CASCADE MICROTECH probe saion, an ADVANTEST D3186 Pulse Paern Generaor, an ADVANTEST R6142 Firsly, he performance of he VCO was evaluaed in open loop mode. The uning range of he VCO is from 360MHz o 1060MHz as displayed in Fig. 7, which is wide enough o cover large PVT variaions. Then he loop was closed, and differenial 622Mb/s l PRBS daa sreams were used as inpu. As shown in Fig.7, he specrum of he recovered clock signal was measured from he in-locked VCO, which illusraes a phase noise of dBc/Hz a 10-kHz offse. Fig. 8 gives he eyediagram of he reimed 622Mb/s NRZ daa, and he measured jier hisogram of he in-locked VCO a 622MHz is shown in Fig. 8. The circui is able o acquire lock in a frequency range beween 398MHz and 960MHz. The power consumpion of CDR core is jus abou 200mW and more 1211 Auhorized licensed use limied o: Carleon Universiy. Downloaded on July 7, 2009 a 11:22 from IEEE Xplore. Resricions apply.

5 han 160mW was dissipaed by oupu daa and clock buffer o drive 50 exernal loads of esing insrumens. The esing resuls of he realized monolihic CDR were summarized in TABLE I. TABLE I SUMMARY OF MEASUREMENT RESULTS Technology Supply Frequency Range Clock Jier Phase Noise Power Birae Applicaion CSMC 0.6 m CMOS 5V 398MHz o 960MHz 12.7ps (RMS), 82.2ps (peak o peak) dBc/Hz@10kHz 363mW 622-Mb/s SONET OC-12/SDH STM-4 5. CONCLUSIONS A low cos CDR circui for daa communicaion sysems has been monolihically implemened in CSMC 0.6 m CMOS. The realized CDR is based on a PFLL using an I/Q ring VCO. The main conribuion of his work is ha on-chip acive inducors are used o design high bi rae, low curren dissipaion, compac chips. CML based fully differenial opology is inroduced o suppress excessive noise. The validiy of he adoped design sraegies and circui echniques are confirmed by he measured daa. 6. REFERENCES [1] B. Razavi, Design of Monolihic Phase-Locked Loops and Clock Recovery Circuis-A Tuorial, Monolihic phase-locked loops and clock recovery circuis, pp.i-ix, IEEE Press, New York, [2] B. Razavi, Design of high-speed circuis for opical communicaion sysems, in IEEE Conf. Cusom Inegraed Circuis, May, 2001, pp [3] B. Razavi, Design of Analog CMOS Inegraed Circuis, McGraw-Hill Higher Educaion, 2000, pp [4] J. Tian, Z. Wang, B. Liang, Y. Hu, Y. Shi, and Y. Zheng, A Monolihic 1 GHz 0.6μm CMOS Low Jier PLL, in Proc. 7 h In. Conf. Solid-Sae and Inegraed Circuis Technology, Oc., 2004, pp [5] A. Pobäcker, U. Langmann, and H.-U. Schreiber, A Si Bipolar Phase and Frequency Deecor IC for Clock Exracion up o 8 Gb/s, in IEEE J. Solid-Sae Circuis, Dec. 1992, pp [6] J. Chrisoph Schey, G. Hanke, and U. Langmann, A , , and Gb/s Auomaic Bi-Rae Selecing Clock and Daa Recovery IC for Bi-Rae Transparen SDH Sysems, in IEEE J. Solid-Sae Circuis, Dec. 1999, pp Auhorized licensed use limied o: Carleon Universiy. Downloaded on July 7, 2009 a 11:22 from IEEE Xplore. Resricions apply.

LECTURE 1 CMOS PHASE LOCKED LOOPS

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